1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson GPIO interrupt controller
10 - Heiner Kallweit <hkallweit1@gmail.com>
13 Meson SoCs contains an interrupt controller which is able to watch the SoC
14 pads and generate an interrupt on edge or level. The controller is essentially
15 a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select
16 edge or level and polarity. It does not expose all 256 mux inputs because the
17 documentation shows that the upper part is not mapped to any pad. The actual
18 number of interrupts exposed depends on the SoC.
21 - $ref: /schemas/interrupt-controller.yaml#
26 - const: amlogic,meson-gpio-intc
29 - amlogic,meson8-gpio-intc
30 - amlogic,meson8b-gpio-intc
31 - amlogic,meson-gxbb-gpio-intc
32 - amlogic,meson-gxl-gpio-intc
33 - amlogic,meson-axg-gpio-intc
34 - amlogic,meson-g12a-gpio-intc
35 - amlogic,meson-sm1-gpio-intc
36 - amlogic,meson-a1-gpio-intc
37 - amlogic,meson-s4-gpio-intc
38 - amlogic,c3-gpio-intc
39 - const: amlogic,meson-gpio-intc
44 interrupt-controller: true
49 amlogic,channel-interrupts:
50 description: Array with the upstream hwirq numbers
53 $ref: /schemas/types.yaml#/definitions/uint32-array
58 - interrupt-controller
60 - amlogic,channel-interrupts
62 additionalProperties: false
66 interrupt-controller@9880 {
67 compatible = "amlogic,meson-gxbb-gpio-intc",
68 "amlogic,meson-gpio-intc";
71 #interrupt-cells = <2>;
72 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;