1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STi System Configuration Controlled IRQs
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 On STi based systems; External, CTI (Core Sight), PMU (Performance
14 Management), and PL310 L2 Cache IRQs are controlled using System
15 Configuration registers. This device is used to unmask them prior to use.
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
23 $ref: /schemas/types.yaml#/definitions/phandle
26 description: Array of IRQs to enable.
27 $ref: /schemas/types.yaml#/definitions/uint32-array
29 - description: Enable the IRQ of the channel one.
30 - description: Enable the IRQ of the channel two.
33 description: Array of FIQs to enable.
34 $ref: /schemas/types.yaml#/definitions/uint32-array
36 - description: Enable the IRQ of the channel one.
37 - description: Enable the IRQ of the channel two.
40 description: External IRQs can be inverted at will. This property inverts
41 these three IRQs using bitwise logic, each one being encoded respectively
42 on the first, second and fourth bit.
43 $ref: /schemas/types.yaml#/definitions/uint32
44 enum: [ 1, 2, 3, 4, 5, 6 ]
52 additionalProperties: false
56 #include <dt-bindings/interrupt-controller/irq-st.h>
58 compatible = "st,stih407-irq-syscfg";
59 st,syscfg = <&syscfg_cpu>;
60 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
61 <ST_IRQ_SYSCFG_PMU_1>;
62 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
63 <ST_IRQ_SYSCFG_DISABLED>;