Bindings/interrupt-controller/ti,pruss-intc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: TI PRU-ICSS Local Interrupt Controller
   8
   9 maintainers:
  10   - Suman Anna <s-anna@ti.com>
  11
  12 description: |
  13   Each PRU-ICSS has a single interrupt controller instance that is common
  14   to all the PRU cores. Most interrupt controllers can route 64 input events
  15   which are then mapped to 10 possible output interrupts through two levels
  16   of mapping. The input events can be triggered by either the PRUs and/or
  17   various other PRUSS internal and external peripherals. The first 2 output
  18   interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
  19   remaining 8 (2 through 9) connected to external interrupt controllers
  20   including the MPU and/or other PRUSS instances, DSPs or devices.
  21
  22   The property "ti,irqs-reserved" is used for denoting the connection
  23   differences on the output interrupts 2 through 9. If this property is not
  24   defined, it implies that all the PRUSS INTC output interrupts 2 through 9
  25   (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
  26   controller.
  27
  28   The K3 family of SoCs can handle 160 input events that can be mapped to 20
  29   different possible output interrupts. The additional output interrupts (10
  30   through 19) are connected to new sub-modules within the ICSSG instances.
  31
  32   This interrupt-controller node should be defined as a child node of the
  33   corresponding PRUSS node. The node should be named "interrupt-controller".
  34
  35 properties:
  36   $nodename:
  37     pattern: "^interrupt-controller@[0-9a-f]+$"
  38
  39   compatible:
  40     enum:
  41       - ti,pruss-intc
  42       - ti,icssg-intc
  43     description: |
  44       Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
  45                               AM335x family of SoCs,
  46                               AM437x family of SoCs,
  47                               AM57xx family of SoCs
  48                               66AK2G family of SoCs
  49       Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
  50
  51   reg:
  52     maxItems: 1
  53
  54   interrupts:
  55     minItems: 1
  56     maxItems: 8
  57     description: |
  58       All the interrupts generated towards the main host processor in the SoC.
  59       A shared interrupt can be skipped if the desired destination and usage is
  60       by a different processor/device.
  61
  62   interrupt-names:
  63     minItems: 1
  64     maxItems: 8
  65     items:
  66       pattern: host_intr[0-7]
  67     description: |
  68       Should use one of the above names for each valid host event interrupt
  69       connected to Arm interrupt controller, the name should match the
  70       corresponding host event interrupt number.
  71
  72   interrupt-controller: true
  73
  74   "#interrupt-cells":
  75     const: 3
  76     description: |
  77       Client users shall use the PRU System event number (the interrupt source
  78       that the client is interested in) [cell 1], PRU channel [cell 2] and PRU
  79       host_event (target) [cell 3] as the value of the interrupts property in
  80       their node.  The system events can be mapped to some output host
  81       interrupts through 2 levels of many-to-one mapping i.e. events to channel
  82       mapping and channels to host interrupts so through this property entire
  83       mapping is provided.
  84
  85   ti,irqs-reserved:
  86     $ref: /schemas/types.yaml#/definitions/uint8
  87     description: |
  88       Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
  89       output interrupts 2 through 9) that are not connected to the Arm interrupt
  90       controller or are shared and used by other devices or processors in the
  91       SoC. Define this property when any of 8 interrupts should not be handled
  92       by Arm interrupt controller.
  93         Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
  94               connected to MPU
  95             - AM65x and J721E SoCs have "host_intr5", "host_intr6" and
  96               "host_intr7" interrupts connected to MPU, and other ICSSG
  97               instances.
  98             - AM64x SoCs have all the 8 host interrupts connected to various
  99               other SoC entities
 100
 101 required:
 102   - compatible
 103   - reg
 104   - interrupts
 105   - interrupt-names
 106   - interrupt-controller
 107   - "#interrupt-cells"
 108
 109 additionalProperties: false
 110
 111 examples:
 112   - |
 113     /* AM33xx PRU-ICSS */
 114     pruss: pruss@0 {
 115         compatible = "ti,am3356-pruss";
 116         reg = <0x0 0x80000>;
 117         #address-cells = <1>;
 118         #size-cells = <1>;
 119         ranges;
 120
 121         pruss_intc: interrupt-controller@20000 {
 122             compatible = "ti,pruss-intc";
 123             reg = <0x20000 0x2000>;
 124             interrupts = <20 21 22 23 24 25 26 27>;
 125             interrupt-names = "host_intr0", "host_intr1",
 126                               "host_intr2", "host_intr3",
 127                               "host_intr4", "host_intr5",
 128                               "host_intr6", "host_intr7";
 129             interrupt-controller;
 130             #interrupt-cells = <3>;
 131         };
 132     };
 133
 134   - |
 135
 136     /* AM4376 PRU-ICSS */
 137     #include <dt-bindings/interrupt-controller/arm-gic.h>
 138     pruss@0 {
 139         compatible = "ti,am4376-pruss1";
 140         reg = <0x0 0x40000>;
 141         #address-cells = <1>;
 142         #size-cells = <1>;
 143         ranges;
 144
 145         interrupt-controller@20000 {
 146             compatible = "ti,pruss-intc";
 147             reg = <0x20000 0x2000>;
 148             interrupt-controller;
 149             #interrupt-cells = <3>;
 150             interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 151                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 152                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 153                    <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 154                    <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 155                    <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 156                    <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 157             interrupt-names = "host_intr0", "host_intr1",
 158                               "host_intr2", "host_intr3",
 159                               "host_intr4",
 160                               "host_intr6", "host_intr7";
 161             ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
 162         };
 163     };