Bindings/media/allegro,al5e.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/allegro,al5e.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Allegro DVT Video IP Codecs
   8
   9 maintainers:
  10   - Michael Tretter <m.tretter@pengutronix.de>
  11
  12 description: |-
  13   Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
  14   either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
  15
  16   Each actual codec engine is controlled by a microcontroller (MCU). Host
  17   software uses a provided mailbox interface to communicate with the MCU. The
  18   MCUs share an interrupt.
  19
  20 properties:
  21   compatible:
  22     oneOf:
  23       - items:
  24           - const: allegro,al5e-1.1
  25           - const: allegro,al5e
  26       - items:
  27           - const: allegro,al5d-1.1
  28           - const: allegro,al5d
  29
  30   reg:
  31     items:
  32       - description: The registers
  33       - description: The SRAM
  34
  35   reg-names:
  36     items:
  37       - const: regs
  38       - const: sram
  39
  40   interrupts:
  41     maxItems: 1
  42
  43   clocks:
  44     items:
  45       - description: Core clock
  46       - description: MCU clock
  47       - description: Core AXI master port clock
  48       - description: MCU AXI master port clock
  49       - description: AXI4-Lite slave port clock
  50
  51   clock-names:
  52     items:
  53       - const: core_clk
  54       - const: mcu_clk
  55       - const: m_axi_core_aclk
  56       - const: m_axi_mcu_aclk
  57       - const: s_axi_lite_aclk
  58
  59 required:
  60   - compatible
  61   - reg
  62   - reg-names
  63   - interrupts
  64   - clocks
  65   - clock-names
  66
  67 additionalProperties: False
  68
  69 examples:
  70   - |
  71     fpga {
  72         #address-cells = <2>;
  73         #size-cells = <2>;
  74
  75         al5e: video-codec@a0009000 {
  76             compatible = "allegro,al5e-1.1", "allegro,al5e";
  77             reg = <0 0xa0009000 0 0x1000>,
  78             <0 0xa0000000 0 0x8000>;
  79             reg-names = "regs", "sram";
  80             interrupts = <0 96 4>;
  81             clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
  82             <&clkc 71>, <&clkc 71>, <&clkc 71>;
  83             clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
  84             "m_axi_mcu_aclk", "s_axi_lite_aclk";
  85         };
  86     };
  87   - |
  88     fpga {
  89         #address-cells = <2>;
  90         #size-cells = <2>;
  91
  92         al5d: video-codec@a0029000 {
  93             compatible = "allegro,al5d-1.1", "allegro,al5d";
  94             reg = <0 0xa0029000 0 0x1000>,
  95                   <0 0xa0020000 0 0x8000>;
  96             reg-names = "regs", "sram";
  97             interrupts = <0 96 4>;
  98             clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,
  99                      <&clkc 71>, <&clkc 71>, <&clkc 71>;
 100             clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
 101             "m_axi_mcu_aclk", "s_axi_lite_aclk";
 102         };
 103     };
 104
 105 ...