Bindings/memory-controllers/ddr/jedec,lpddr3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
   8
   9 maintainers:
  10   - Krzysztof Kozlowski <krzk@kernel.org>
  11
  12 allOf:
  13   - $ref: jedec,lpddr-props.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - samsung,K3QF2F20DB
  21           - const: jedec,lpddr3
  22       - items:
  23           - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
  24           - const: jedec,lpddr3
  25
  26   '#address-cells':
  27     const: 1
  28     deprecated: true
  29
  30   manufacturer-id:
  31     $ref: /schemas/types.yaml#/definitions/uint32
  32     description: |
  33       Manufacturer ID value read from Mode Register 5.  The property is
  34       deprecated, manufacturer should be derived from the compatible.
  35     deprecated: true
  36
  37   '#size-cells':
  38     const: 0
  39     deprecated: true
  40
  41   tCKE-min-tck:
  42     $ref: /schemas/types.yaml#/definitions/uint32
  43     maximum: 15
  44     description: |
  45       CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
  46       of clock cycles.
  47
  48   tCKESR-min-tck:
  49     $ref: /schemas/types.yaml#/definitions/uint32
  50     maximum: 15
  51     description: |
  52       CKE minimum pulse width during SELF REFRESH (low pulse width during
  53       SELF REFRESH) in terms of number of clock cycles.
  54
  55   tDQSCK-min-tck:
  56     $ref: /schemas/types.yaml#/definitions/uint32
  57     maximum: 15
  58     description: |
  59       DQS output data access time from CK_t/CK_c in terms of number of clock
  60       cycles.
  61
  62   tFAW-min-tck:
  63     $ref: /schemas/types.yaml#/definitions/uint32
  64     maximum: 63
  65     description: |
  66       Four-bank activate window in terms of number of clock cycles.
  67
  68   tMRD-min-tck:
  69     $ref: /schemas/types.yaml#/definitions/uint32
  70     maximum: 15
  71     description: |
  72       Mode register set command delay in terms of number of clock cycles.
  73
  74   tR2R-C2C-min-tck:
  75     $ref: /schemas/types.yaml#/definitions/uint32
  76     enum: [0, 1]
  77     description: |
  78       Additional READ-to-READ delay in chip-to-chip cases in terms of number
  79       of clock cycles.
  80
  81   tRAS-min-tck:
  82     $ref: /schemas/types.yaml#/definitions/uint32
  83     maximum: 63
  84     description: |
  85       Row active time in terms of number of clock cycles.
  86
  87   tRC-min-tck:
  88     $ref: /schemas/types.yaml#/definitions/uint32
  89     maximum: 63
  90     description: |
  91       ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
  92
  93   tRCD-min-tck:
  94     $ref: /schemas/types.yaml#/definitions/uint32
  95     maximum: 15
  96     description: |
  97       RAS-to-CAS delay in terms of number of clock cycles.
  98
  99   tRFC-min-tck:
 100     $ref: /schemas/types.yaml#/definitions/uint32
 101     maximum: 255
 102     description: |
 103       Refresh Cycle time in terms of number of clock cycles.
 104
 105   tRL-min-tck:
 106     $ref: /schemas/types.yaml#/definitions/uint32
 107     maximum: 15
 108     description: |
 109      READ data latency in terms of number of clock cycles.
 110
 111   tRPab-min-tck:
 112     $ref: /schemas/types.yaml#/definitions/uint32
 113     maximum: 15
 114     description: |
 115       Row precharge time (all banks) in terms of number of clock cycles.
 116
 117   tRPpb-min-tck:
 118     $ref: /schemas/types.yaml#/definitions/uint32
 119     maximum: 15
 120     description: |
 121       Row precharge time (single banks) in terms of number of clock cycles.
 122
 123   tRRD-min-tck:
 124     $ref: /schemas/types.yaml#/definitions/uint32
 125     maximum: 15
 126     description: |
 127       Active bank A to active bank B in terms of number of clock cycles.
 128
 129   tRTP-min-tck:
 130     $ref: /schemas/types.yaml#/definitions/uint32
 131     maximum: 15
 132     description: |
 133       Internal READ to PRECHARGE command delay in terms of number of clock
 134       cycles.
 135
 136   tW2W-C2C-min-tck:
 137     $ref: /schemas/types.yaml#/definitions/uint32
 138     enum: [0, 1]
 139     description: |
 140       Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
 141       of clock cycles.
 142
 143   tWL-min-tck:
 144     $ref: /schemas/types.yaml#/definitions/uint32
 145     maximum: 15
 146     description: |
 147       WRITE data latency in terms of number of clock cycles.
 148
 149   tWR-min-tck:
 150     $ref: /schemas/types.yaml#/definitions/uint32
 151     maximum: 15
 152     description: |
 153       WRITE recovery time in terms of number of clock cycles.
 154
 155   tWTR-min-tck:
 156     $ref: /schemas/types.yaml#/definitions/uint32
 157     maximum: 15
 158     description: |
 159       Internal WRITE-to-READ command delay in terms of number of clock cycles.
 160
 161   tXP-min-tck:
 162     $ref: /schemas/types.yaml#/definitions/uint32
 163     maximum: 255
 164     description: |
 165       Exit power-down to next valid command delay in terms of number of clock
 166       cycles.
 167
 168   tXSR-min-tck:
 169     $ref: /schemas/types.yaml#/definitions/uint32
 170     maximum: 1023
 171     description: |
 172       SELF REFRESH exit to next valid command delay in terms of number of clock
 173       cycles.
 174
 175 patternProperties:
 176   "^timings((-[0-9])+|(@[0-9a-f]+))?$":
 177     $ref: jedec,lpddr3-timings.yaml
 178     description: |
 179       The lpddr3 node may have one or more child nodes with timings.
 180       Each timing node provides AC timing parameters of the device for a given
 181       speed-bin. The user may provide the timings for as many speed-bins as is
 182       required.
 183
 184 required:
 185   - compatible
 186   - density
 187   - io-width
 188
 189 unevaluatedProperties: false
 190
 191 examples:
 192   - |
 193     lpddr3 {
 194         compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
 195         density = <16384>;
 196         io-width = <32>;
 197
 198         tCKE-min-tck = <2>;
 199         tCKESR-min-tck = <2>;
 200         tDQSCK-min-tck = <5>;
 201         tFAW-min-tck = <5>;
 202         tMRD-min-tck = <5>;
 203         tR2R-C2C-min-tck = <0>;
 204         tRAS-min-tck = <5>;
 205         tRC-min-tck = <6>;
 206         tRCD-min-tck = <3>;
 207         tRFC-min-tck = <17>;
 208         tRL-min-tck = <14>;
 209         tRPab-min-tck = <2>;
 210         tRPpb-min-tck = <2>;
 211         tRRD-min-tck = <2>;
 212         tRTP-min-tck = <2>;
 213         tW2W-C2C-min-tck = <0>;
 214         tWL-min-tck = <8>;
 215         tWR-min-tck = <7>;
 216         tWTR-min-tck = <2>;
 217         tXP-min-tck = <2>;
 218         tXSR-min-tck = <12>;
 219
 220         timings {
 221             compatible = "jedec,lpddr3-timings";
 222             max-freq = <800000000>;
 223             min-freq = <100000000>;
 224             tCKE = <3750>;
 225             tCKESR = <3750>;
 226             tFAW = <25000>;
 227             tMRD = <7000>;
 228             tR2R-C2C = <0>;
 229             tRAS = <23000>;
 230             tRC = <33750>;
 231             tRCD = <10000>;
 232             tRFC = <65000>;
 233             tRPab = <12000>;
 234             tRPpb = <12000>;
 235             tRRD = <6000>;
 236             tRTP = <3750>;
 237             tW2W-C2C = <0>;
 238             tWR = <7500>;
 239             tWTR = <3750>;
 240             tXP = <3750>;
 241             tXSR = <70000>;
 242         };
 243     };