1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
16 The Enhanced Secure Digital Host Controller on Freescale i.MX family
17 provides an interface for MMC, SD, and SDIO types of memory cards.
19 This file documents differences between the core properties described
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
46 - const: fsl,imx6sx-usdhc
48 - const: fsl,imx7d-usdhc
49 - const: fsl,imx6sl-usdhc
53 - const: fsl,imx7d-usdhc
60 - const: fsl,imx8mm-usdhc
65 - const: fsl,imx8qxp-usdhc
73 - const: fsl,imx7d-usdhc
79 - const: fsl,imx8mm-usdhc
80 - const: fsl,imx7d-usdhc
86 - const: fsl,imx8qxp-usdhc
87 - const: fsl,imx7d-usdhc
92 - const: fsl,imxrt1050-usdhc
102 boolean, if present, indicate to use controller internal write protection.
106 $ref: /schemas/types.yaml#/definitions/uint32
108 Specify the number of delay cells for override mode.
109 This is used to set the clock delay for DLL(Delay Line) on override mode
110 to select a proper data sampling window in case the clock quality is not good
111 because the signal path is too long on the board. Please refer to eSDHC/uSDHC
112 chapter, DLL (Delay Line) section in RM for details.
116 $ref: /schemas/types.yaml#/definitions/uint32-matrix
118 Specify the voltage range in case there are software transparent level
119 shifters on the outputs of the controller. Two cells are required, first
120 cell specifies minimum slot voltage (mV), second cell specifies maximum
124 - description: value for minimum slot voltage
125 - description: value for maximum slot voltage
128 fsl,tuning-start-tap:
129 $ref: /schemas/types.yaml#/definitions/uint32
131 Specify the start delay cell point when send first CMD19 in tuning procedure.
135 $ref: /schemas/types.yaml#/definitions/uint32
137 Specify the increasing delay cell steps in tuning procedure.
138 The uSDHC use one delay cell as default increasing step to do tuning process.
139 This property allows user to change the tuning step to more than one delay
140 cell which is useful for some special boards or cards when the default
141 tuning step can't find the proper delay window within limited tuning retries.
144 fsl,strobe-dll-delay-target:
145 $ref: /schemas/types.yaml#/definitions/uint32
147 Specify the strobe dll control slave delay target.
148 This delay target programming host controller loopback read clock, and this
149 property allows user to change the delay target for the strobe input read clock.
150 If not use this property, driver default set the delay target to value 7.
151 Only eMMC HS400 mode need to take care of this property.
157 Handle clocks for the sdhc controller.
173 - const: state_100mhz
174 - const: state_200mhz
186 unevaluatedProperties: false
191 compatible = "fsl,imx51-esdhc";
192 reg = <0x70004000 0x4000>;
198 compatible = "fsl,imx51-esdhc";
199 reg = <0x70008000 0x4000>;
201 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
202 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */