Bindings/mtd/atmel-nand.txt

   1 Atmel NAND flash controller bindings
   2
   3 The NAND flash controller node should be defined under the EBI bus (see
   4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
   5 One or several NAND devices can be defined under this NAND controller.
   6 The NAND controller might be connected to an ECC engine.
   7
   8 * NAND controller bindings:
   9
  10 Required properties:
  11 - compatible: should be one of the following
  12         "atmel,at91rm9200-nand-controller"
  13         "atmel,at91sam9260-nand-controller"
  14         "atmel,at91sam9261-nand-controller"
  15         "atmel,at91sam9g45-nand-controller"
  16         "atmel,sama5d3-nand-controller"
  17         "microchip,sam9x60-nand-controller"
  18 - ranges: empty ranges property to forward EBI ranges definitions.
  19 - #address-cells: should be set to 2.
  20 - #size-cells: should be set to 1.
  21 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
  22                 controllers.
  23 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
  24                   controllers.
  25
  26 Optional properties:
  27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
  28               a PMECC engine.
  29
  30 * NAND device/chip bindings:
  31
  32 Required properties:
  33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
  34        exposes multiple CS lines (multi-dies chips), your reg property will
  35        contain X tuples of 3 entries.
  36        1st entry: the CS line this NAND chip is connected to
  37        2nd entry: the base offset of the memory region assigned to this
  38                   device (always 0)
  39        3rd entry: the memory region size (always 0x800000)
  40
  41 Optional properties:
  42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
  43 - cs-gpios: the GPIO(s) used to control the CS line.
  44 - det-gpios: the GPIO used to detect if a Smartmedia Card is present.
  45 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
  46             on sama5 SoCs.
  47
  48 All generic properties are described in the generic yaml files under
  49 Documentation/devicetree/bindings/mtd/.
  50
  51 * ECC engine (PMECC) bindings:
  52
  53 Required properties:
  54 - compatible: should be one of the following
  55         "atmel,at91sam9g45-pmecc"
  56         "atmel,sama5d4-pmecc"
  57         "atmel,sama5d2-pmecc"
  58         "microchip,sam9x60-pmecc"
  59 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
  60        block, and the second one to the PMECC_ERRLOC block.
  61
  62 * SAMA5 NFC I/O bindings:
  63
  64 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
  65 operations. This interface to this logic is placed in a separate I/O range and
  66 should thus have its own DT node.
  67
  68 - compatible: should be "atmel,sama5d3-nfc-io", "syscon".
  69 - reg: should contain the I/O range used to interact with the NFC logic.
  70
  71 Example:
  72
  73         nfc_io: nfc-io@70000000 {
  74                 compatible = "atmel,sama5d3-nfc-io", "syscon";
  75                 reg = <0x70000000 0x8000000>;
  76         };
  77
  78         pmecc: ecc-engine@ffffc070 {
  79                 compatible = "atmel,at91sam9g45-pmecc";
  80                 reg = <0xffffc070 0x490>,
  81                       <0xffffc500 0x100>;
  82         };
  83
  84         ebi: ebi@10000000 {
  85                 compatible = "atmel,sama5d3-ebi";
  86                 #address-cells = <2>;
  87                 #size-cells = <1>;
  88                 atmel,smc = <&hsmc>;
  89                 reg = <0x10000000 0x10000000
  90                        0x40000000 0x30000000>;
  91                 ranges = <0x0 0x0 0x10000000 0x10000000
  92                           0x1 0x0 0x40000000 0x10000000
  93                           0x2 0x0 0x50000000 0x10000000
  94                           0x3 0x0 0x60000000 0x10000000>;
  95                 clocks = <&mck>;
  96
  97                 nand_controller: nand-controller {
  98                         compatible = "atmel,sama5d3-nand-controller";
  99                         atmel,nfc-sram = <&nfc_sram>;
 100                         atmel,nfc-io = <&nfc_io>;
 101                         ecc-engine = <&pmecc>;
 102                         #address-cells = <2>;
 103                         #size-cells = <1>;
 104                         ranges;
 105
 106                         nand@3 {
 107                                 reg = <0x3 0x0 0x800000>;
 108                                 atmel,rb = <0>;
 109
 110                                 /*
 111                                  * Put generic NAND/MTD properties and
 112                                  * subnodes here.
 113                                  */
 114                         };
 115                 };
 116         };
 117
 118 -----------------------------------------------------------------------
 119
 120 Deprecated bindings (should not be used in new device trees):
 121
 122 Required properties:
 123 - compatible: The possible values are:
 124         "atmel,at91rm9200-nand"
 125         "atmel,sama5d2-nand"
 126         "atmel,sama5d4-nand"
 127 - reg : should specify localbus address and size used for the chip,
 128         and hardware ECC controller if available.
 129         If the hardware ECC is PMECC, it should contain address and size for
 130         PMECC and PMECC Error Location controller.
 131         The PMECC lookup table address and size in ROM is optional. If not
 132         specified, driver will build it in runtime.
 133 - atmel,nand-addr-offset : offset for the address latch.
 134 - atmel,nand-cmd-offset : offset for the command latch.
 135 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 136   representing partitions.
 137
 138 - gpios : specifies the gpio pins to control the NAND device. detect is an
 139   optional gpio and may be set to 0 if not present.
 140
 141 Optional properties:
 142 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
 143 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
 144   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
 145   "soft_bch".
 146 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
 147   capable of BCH encoding and decoding, on devices where it is present.
 148 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
 149   Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
 150   is "atmel,sama5d2-nand", 32 is also valid.
 151 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
 152   are: 512, 1024.
 153 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
 154   for different sector size. First one is for sector size 512, the next is for
 155   sector size 1024. If not specified, driver will build the table in runtime.
 156 - nand-bus-width : 8 or 16 bus width if not present 8
 157 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 158
 159 Nand Flash Controller(NFC) is an optional sub-node
 160 Required properties:
 161 - compatible : "atmel,sama5d3-nfc".
 162 - reg : should specify the address and size used for NFC command registers,
 163         NFC registers and NFC SRAM. NFC SRAM address and size can be absent
 164         if don't want to use it.
 165 - clocks: phandle to the peripheral clock
 166 Optional properties:
 167 - atmel,write-by-sram: boolean to enable NFC write by SRAM.
 168
 169 Examples:
 170 nand0: nand@40000000,0 {
 171         compatible = "atmel,at91rm9200-nand";
 172         #address-cells = <1>;
 173         #size-cells = <1>;
 174         reg = <0x40000000 0x10000000
 175                0xffffe800 0x200
 176               >;
 177         atmel,nand-addr-offset = <21>;  /* ale */
 178         atmel,nand-cmd-offset = <22>;   /* cle */
 179         nand-on-flash-bbt;
 180         nand-ecc-mode = "soft";
 181         gpios = <&pioC 13 0     /* rdy */
 182                  &pioC 14 0     /* nce */
 183                  0              /* cd */
 184                 >;
 185         partition@0 {
 186                 ...
 187         };
 188 };
 189
 190 /* for PMECC supported chips */
 191 nand0: nand@40000000 {
 192         compatible = "atmel,at91rm9200-nand";
 193         #address-cells = <1>;
 194         #size-cells = <1>;
 195         reg = < 0x40000000 0x10000000   /* bus addr & size */
 196                 0xffffe000 0x00000600   /* PMECC addr & size */
 197                 0xffffe600 0x00000200   /* PMECC ERRLOC addr & size */
 198                 0x00100000 0x00100000   /* ROM addr & size */
 199                 >;
 200         atmel,nand-addr-offset = <21>;  /* ale */
 201         atmel,nand-cmd-offset = <22>;   /* cle */
 202         nand-on-flash-bbt;
 203         nand-ecc-mode = "hw";
 204         atmel,has-pmecc;        /* enable PMECC */
 205         atmel,pmecc-cap = <2>;
 206         atmel,pmecc-sector-size = <512>;
 207         atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
 208         gpios = <&pioD 5 0      /* rdy */
 209                  &pioD 4 0      /* nce */
 210                  0              /* cd */
 211                 >;
 212         partition@0 {
 213                 ...
 214         };
 215 };
 216
 217 /* for NFC supported chips */
 218 nand0: nand@40000000 {
 219         compatible = "atmel,at91rm9200-nand";
 220         #address-cells = <1>;
 221         #size-cells = <1>;
 222         ranges;
 223         ...
 224         nfc@70000000 {
 225                 compatible = "atmel,sama5d3-nfc";
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228                 clocks = <&hsmc_clk>
 229                 reg = <
 230                         0x70000000 0x10000000   /* NFC Command Registers */
 231                         0xffffc000 0x00000070   /* NFC HSMC regs */
 232                         0x00200000 0x00100000   /* NFC SRAM banks */
 233                 >;
 234         };
 235 };