1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros QCA83xx switch family
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
20 mdio-bus configurations are not supported by the hardware.
21 Each phy has at most 3 LEDs connected and can be declared
22 using the standard LEDs structure.
33 qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
34 qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
35 qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
36 qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
43 GPIO to be used to reset the whole device
46 qca,ignore-power-on-sel:
47 $ref: /schemas/types.yaml#/definitions/flag
49 Ignore power-on pin strapping to configure LED open-drain or EEPROM
50 presence. This is needed for devices with incorrect configuration or when
51 the OEM has decided not to use pin strapping and falls back to SW regs.
54 $ref: /schemas/types.yaml#/definitions/flag
56 Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
57 be set, otherwise the driver will fail at probe. This is required if the
58 OEM does not use pin strapping to set this mode and prefers to set it
59 using SW regs. The pin strappings related to LED open-drain mode are
60 B68 on the QCA832x and B49 on the QCA833x.
63 $ref: /schemas/net/mdio.yaml#
64 unevaluatedProperties: false
65 description: Qca8k switch have an internal mdio to access switch port.
66 If this is not present, the legacy mapping is used and the
67 internal mdio access is used.
68 With the legacy mapping the reg corresponding to the internal
69 mdio is the switch reg with an offset of -1.
74 "^(ethernet-)?ports$":
76 additionalProperties: true
78 "^(ethernet-)?port@[0-6]$":
80 description: Ethernet switch ports
85 qca,sgmii-rxclk-falling-edge:
86 $ref: /schemas/types.yaml#/definitions/flag
88 Set the receive clock phase to falling edge. Mostly commonly used on
89 the QCA8327 with CPU port 0 set to SGMII.
91 qca,sgmii-txclk-falling-edge:
92 $ref: /schemas/types.yaml#/definitions/flag
94 Set the transmit clock phase to falling edge.
97 $ref: /schemas/types.yaml#/definitions/flag
99 For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
100 Signal Detection. On the QCA8327 this should not be enabled, otherwise
101 the SGMII port will not initialize. When used on the QCA8337, revision 3
102 or greater, a warning will be displayed. When the CPU port is set to
103 SGMII on the QCA8337, it is advised to set this unless a communication
106 unevaluatedProperties: false
118 unevaluatedProperties: false
122 #include <dt-bindings/gpio/gpio.h>
123 #include <dt-bindings/leds/common.h>
126 #address-cells = <1>;
129 external_phy_port1: ethernet-phy@0 {
133 external_phy_port2: ethernet-phy@1 {
137 external_phy_port3: ethernet-phy@2 {
141 external_phy_port4: ethernet-phy@3 {
145 external_phy_port5: ethernet-phy@4 {
150 compatible = "qca,qca8337";
151 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
155 #address-cells = <1>;
172 phy-handle = <&external_phy_port1>;
178 phy-handle = <&external_phy_port2>;
184 phy-handle = <&external_phy_port3>;
190 phy-handle = <&external_phy_port4>;
196 phy-handle = <&external_phy_port5>;
202 #include <dt-bindings/gpio/gpio.h>
205 #address-cells = <1>;
209 compatible = "qca,qca8337";
210 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
214 #address-cells = <1>;
231 phy-mode = "internal";
232 phy-handle = <&internal_phy_port1>;
235 #address-cells = <1>;
240 color = <LED_COLOR_ID_WHITE>;
241 function = LED_FUNCTION_LAN;
242 default-state = "keep";
247 color = <LED_COLOR_ID_AMBER>;
248 function = LED_FUNCTION_LAN;
249 default-state = "keep";
257 phy-mode = "internal";
258 phy-handle = <&internal_phy_port2>;
264 phy-mode = "internal";
265 phy-handle = <&internal_phy_port3>;
271 phy-mode = "internal";
272 phy-handle = <&internal_phy_port4>;
278 phy-mode = "internal";
279 phy-handle = <&internal_phy_port5>;
287 qca,sgmii-rxclk-falling-edge;
297 #address-cells = <1>;
300 internal_phy_port1: ethernet-phy@0 {
304 internal_phy_port2: ethernet-phy@1 {
308 internal_phy_port3: ethernet-phy@2 {
312 internal_phy_port4: ethernet-phy@3 {
316 internal_phy_port5: ethernet-phy@4 {