]> git.ipfire.org Git - thirdparty/u-boot.git/blob - Bindings/pci/fsl,imx6q-pcie-common.yaml
Squashed 'dts/upstream/' content from commit aaba2d45dc2a
[thirdparty/u-boot.git] / Bindings / pci / fsl,imx6q-pcie-common.yaml
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Freescale i.MX6 PCIe RC/EP controller
8
9 maintainers:
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
12
13 description:
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
15 properties.
16
17 properties:
18 clocks:
19 minItems: 3
20 maxItems: 4
21
22 clock-names:
23 minItems: 3
24 maxItems: 4
25
26 num-lanes:
27 const: 1
28
29 fsl,imx7d-pcie-phy:
30 $ref: /schemas/types.yaml#/definitions/phandle
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
32 required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
33 and imx8mq-pcie-ep.
34
35 power-domains:
36 minItems: 1
37 items:
38 - description: The phandle pointing to the DISPLAY domain for
39 imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
40 imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
41 - description: The phandle pointing to the PCIE_PHY power domains
42 for imx6sx-pcie and imx6sx-pcie-ep.
43
44 power-domain-names:
45 minItems: 1
46 items:
47 - const: pcie
48 - const: pcie_phy
49
50 resets:
51 minItems: 2
52 maxItems: 3
53 description: Phandles to PCIe-related reset lines exposed by SRC
54 IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,
55 imx8mq-pcie, and imx8mq-pcie-ep.
56
57 reset-names:
58 minItems: 2
59 maxItems: 3
60
61 fsl,tx-deemph-gen1:
62 description: Gen1 De-emphasis value (optional required).
63 $ref: /schemas/types.yaml#/definitions/uint32
64 default: 0
65
66 fsl,tx-deemph-gen2-3p5db:
67 description: Gen2 (3.5db) De-emphasis value (optional required).
68 $ref: /schemas/types.yaml#/definitions/uint32
69 default: 0
70
71 fsl,tx-deemph-gen2-6db:
72 description: Gen2 (6db) De-emphasis value (optional required).
73 $ref: /schemas/types.yaml#/definitions/uint32
74 default: 20
75
76 fsl,tx-swing-full:
77 description: Gen2 TX SWING FULL value (optional required).
78 $ref: /schemas/types.yaml#/definitions/uint32
79 default: 127
80
81 fsl,tx-swing-low:
82 description: TX launch amplitude swing_low value (optional required).
83 $ref: /schemas/types.yaml#/definitions/uint32
84 default: 127
85
86 fsl,max-link-speed:
87 description: Specify PCI Gen for link capability (optional required).
88 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
89 requirements and thus for gen2 capability a gen2 compliant clock
90 generator should be used and configured.
91 $ref: /schemas/types.yaml#/definitions/uint32
92 enum: [1, 2, 3, 4]
93 default: 1
94
95 phys:
96 maxItems: 1
97
98 phy-names:
99 const: pcie-phy
100
101 vpcie-supply:
102 description: Should specify the regulator in charge of PCIe port power.
103 The regulator will be enabled when initializing the PCIe host and
104 disabled either as part of the init process or when shutting down
105 the host (optional required).
106
107 vph-supply:
108 description: Should specify the regulator in charge of VPH one of
109 the three PCIe PHY powers. This regulator can be supplied by both
110 1.8v and 3.3v voltage supplies (optional required).
111
112 required:
113 - clocks
114 - clock-names
115 - num-lanes
116
117 allOf:
118 - if:
119 properties:
120 compatible:
121 contains:
122 enum:
123 - fsl,imx6sx-pcie
124 - fsl,imx6sx-pcie-ep
125 then:
126 properties:
127 clock-names:
128 items:
129 - {}
130 - {}
131 - const: pcie_phy
132 - const: pcie_inbound_axi
133 power-domains:
134 minItems: 2
135 power-domain-names:
136 minItems: 2
137
138 - if:
139 properties:
140 compatible:
141 contains:
142 enum:
143 - fsl,imx8mq-pcie
144 - fsl,imx8mq-pcie-ep
145 then:
146 properties:
147 clock-names:
148 items:
149 - {}
150 - {}
151 - const: pcie_phy
152 - const: pcie_aux
153 - if:
154 properties:
155 compatible:
156 not:
157 contains:
158 enum:
159 - fsl,imx6sx-pcie
160 - fsl,imx8mq-pcie
161 - fsl,imx6sx-pcie-ep
162 - fsl,imx8mq-pcie-ep
163 then:
164 properties:
165 clocks:
166 maxItems: 3
167 clock-names:
168 maxItems: 3
169
170 - if:
171 properties:
172 compatible:
173 contains:
174 enum:
175 - fsl,imx6q-pcie
176 - fsl,imx6qp-pcie
177 - fsl,imx7d-pcie
178 - fsl,imx6q-pcie-ep
179 - fsl,imx6qp-pcie-ep
180 - fsl,imx7d-pcie-ep
181 then:
182 properties:
183 clock-names:
184 maxItems: 3
185 contains:
186 const: pcie_phy
187
188 - if:
189 properties:
190 compatible:
191 contains:
192 enum:
193 - fsl,imx8mm-pcie
194 - fsl,imx8mp-pcie
195 - fsl,imx8mm-pcie-ep
196 - fsl,imx8mp-pcie-ep
197 then:
198 properties:
199 clock-names:
200 maxItems: 3
201 contains:
202 const: pcie_aux
203 - if:
204 properties:
205 compatible:
206 contains:
207 enum:
208 - fsl,imx6q-pcie
209 - fsl,imx6qp-pcie
210 - fsl,imx6q-pcie-ep
211 - fsl,imx6qp-pcie-ep
212 then:
213 properties:
214 power-domains: false
215 power-domain-names: false
216
217 - if:
218 not:
219 properties:
220 compatible:
221 contains:
222 enum:
223 - fsl,imx6sx-pcie
224 - fsl,imx6q-pcie
225 - fsl,imx6qp-pcie
226 - fsl,imx6sx-pcie-ep
227 - fsl,imx6q-pcie-ep
228 - fsl,imx6qp-pcie-ep
229 then:
230 properties:
231 power-domains:
232 maxItems: 1
233 power-domain-names: false
234
235 - if:
236 properties:
237 compatible:
238 contains:
239 enum:
240 - fsl,imx6q-pcie
241 - fsl,imx6sx-pcie
242 - fsl,imx6qp-pcie
243 - fsl,imx7d-pcie
244 - fsl,imx8mq-pcie
245 - fsl,imx6q-pcie-ep
246 - fsl,imx6sx-pcie-ep
247 - fsl,imx6qp-pcie-ep
248 - fsl,imx7d-pcie-ep
249 - fsl,imx8mq-pcie-ep
250 then:
251 properties:
252 resets:
253 minItems: 3
254 reset-names:
255 items:
256 - const: pciephy
257 - const: apps
258 - const: turnoff
259 else:
260 properties:
261 resets:
262 maxItems: 2
263 reset-names:
264 items:
265 - const: apps
266 - const: turnoff
267
268 additionalProperties: true
269
270 ...