1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
26 - qcom,pcie-ipq8064-v2
28 - qcom,pcie-ipq8074-gen3
41 - qcom,pcie-sm8450-pcie0
42 - qcom,pcie-sm8450-pcie1
45 - const: qcom,pcie-msm8998
46 - const: qcom,pcie-msm8996
67 # Common definitions for clocks, clock-names and reset.
68 # Platform constraints are described later.
96 description: A phandle to the core analog power supply
99 description: A phandle to the core analog power supply for PHY
102 description: A phandle to the core analog power supply for IC which generates reference clock
105 description: A phandle to the PCIe endpoint power supply
118 description: GPIO controlled connection to PERST# signal
122 description: GPIO controlled connection to WAKE# signal
144 - $ref: /schemas/pci/pci-bus.yaml#
153 - qcom,pcie-ipq8064v2
163 - const: dbi # DesignWare PCIe registers
164 - const: elbi # External local bus interface registers
165 - const: parf # Qualcomm specific registers
166 - const: config # PCIe configuration space
174 - qcom,pcie-ipq8074-gen3
182 - const: dbi # DesignWare PCIe registers
183 - const: elbi # External local bus interface registers
184 - const: atu # ATU address space
185 - const: parf # Qualcomm specific registers
186 - const: config # PCIe configuration space
204 - const: parf # Qualcomm specific registers
205 - const: dbi # DesignWare PCIe registers
206 - const: elbi # External local bus interface registers
207 - const: config # PCIe configuration space
208 - const: mhi # MHI registers
222 - qcom,pcie-sm8450-pcie0
223 - qcom,pcie-sm8450-pcie1
233 - const: parf # Qualcomm specific registers
234 - const: dbi # DesignWare PCIe registers
235 - const: elbi # External local bus interface registers
236 - const: atu # ATU address space
237 - const: config # PCIe configuration space
238 - const: mhi # MHI registers
247 - qcom,pcie-ipq8064v2
256 - const: core # Clocks the pcie hw block
257 - const: iface # Configuration AHB clock
258 - const: phy # Clocks the pcie PHY block
259 - const: aux # Clocks the pcie AUX block, not on apq8064
260 - const: ref # Clocks the pcie ref block, not on apq8064
267 - const: axi # AXI reset
268 - const: ahb # AHB reset
269 - const: por # POR reset
270 - const: pci # PCI reset
271 - const: phy # PHY reset
272 - const: ext # EXT reset, not on apq8064
291 - const: iface # Configuration AHB clock
292 - const: master_bus # Master AXI clock
293 - const: slave_bus # Slave AXI clock
294 - const: aux # Auxiliary (AUX) clock
299 - const: core # Core reset
314 - const: aux # Auxiliary (AUX) clock
315 - const: master_bus # Master AXI clock
316 - const: slave_bus # Slave AXI clock
322 - const: axi_m # AXI master reset
323 - const: axi_s # AXI slave reset
324 - const: pipe # PIPE reset
325 - const: axi_m_vmid # VMID reset
326 - const: axi_s_xpu # XPU reset
327 - const: parf # PARF reset
328 - const: phy # PHY reset
329 - const: axi_m_sticky # AXI sticky reset
330 - const: pipe_sticky # PIPE sticky reset
331 - const: pwr # PWR reset
332 - const: ahb # AHB reset
333 - const: phy_ahb # PHY AHB reset
348 - const: pipe # Pipe Clock driving internal logic
349 - const: aux # Auxiliary (AUX) clock
350 - const: cfg # Configuration clock
351 - const: bus_master # Master AXI clock
352 - const: bus_slave # Slave AXI clock
369 - const: iface # PCIe to SysNOC BIU clock
370 - const: axi_m # AXI Master clock
371 - const: axi_s # AXI Slave clock
372 - const: ahb # AHB clock
373 - const: aux # Auxiliary clock
379 - const: pipe # PIPE reset
380 - const: sleep # Sleep reset
381 - const: sticky # Core Sticky reset
382 - const: axi_m # AXI Master reset
383 - const: axi_s # AXI Slave reset
384 - const: ahb # AHB Reset
385 - const: axi_m_sticky # AXI Master Sticky reset
393 - qcom,pcie-ipq8074-gen3
401 - const: iface # PCIe to SysNOC BIU clock
402 - const: axi_m # AXI Master clock
403 - const: axi_s # AXI Slave clock
404 - const: axi_bridge # AXI bridge clock
411 - const: pipe # PIPE reset
412 - const: sleep # Sleep reset
413 - const: sticky # Core Sticky reset
414 - const: axi_m # AXI Master reset
415 - const: axi_s # AXI Slave reset
416 - const: ahb # AHB Reset
417 - const: axi_m_sticky # AXI Master Sticky reset
418 - const: axi_s_sticky # AXI Slave Sticky reset
433 - const: iface # AHB clock
434 - const: aux # Auxiliary clock
435 - const: master_bus # AXI Master clock
436 - const: slave_bus # AXI Slave clock
442 - const: axi_m # AXI Master reset
443 - const: axi_s # AXI Slave reset
444 - const: axi_m_sticky # AXI Master Sticky reset
445 - const: pipe_sticky # PIPE sticky reset
446 - const: pwr # PWR reset
447 - const: ahb # AHB reset
462 - const: pipe # PIPE clock
463 - const: pipe_mux # PIPE MUX
464 - const: phy_pipe # PIPE output clock
465 - const: ref # REFERENCE clock
466 - const: aux # Auxiliary clock
467 - const: cfg # Configuration clock
468 - const: bus_master # Master AXI clock
469 - const: bus_slave # Slave AXI clock
470 - const: slave_q2a # Slave Q2A clock
471 - const: tbu # PCIe TBU clock
472 - const: ddrss_sf_tbu # PCIe SF TBU clock
473 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
474 - const: aggre1 # Aggre NoC PCIe1 AXI clock
479 - const: pci # PCIe core reset
489 # Unfortunately the "optional" ref clock is used in the middle of the list
496 - const: pipe # PIPE clock
497 - const: aux # Auxiliary clock
498 - const: cfg # Configuration clock
499 - const: bus_master # Master AXI clock
500 - const: bus_slave # Slave AXI clock
501 - const: slave_q2a # Slave Q2A clock
502 - const: ref # REFERENCE clock
503 - const: tbu # PCIe TBU clock
510 - const: pipe # PIPE clock
511 - const: aux # Auxiliary clock
512 - const: cfg # Configuration clock
513 - const: bus_master # Master AXI clock
514 - const: bus_slave # Slave AXI clock
515 - const: slave_q2a # Slave Q2A clock
516 - const: tbu # PCIe TBU clock
522 - const: pci # PCIe core reset
534 # Unfortunately the "optional" ref clock is used in the middle of the list
541 - const: pipe # PIPE clock
542 - const: aux # Auxiliary clock
543 - const: cfg # Configuration clock
544 - const: bus_master # Master AXI clock
545 - const: bus_slave # Slave AXI clock
546 - const: slave_q2a # Slave Q2A clock
547 - const: ref # REFERENCE clock
548 - const: tbu # PCIe TBU clock
549 - const: ddrss_sf_tbu # PCIe SF TBU clock
556 - const: pipe # PIPE clock
557 - const: aux # Auxiliary clock
558 - const: cfg # Configuration clock
559 - const: bus_master # Master AXI clock
560 - const: bus_slave # Slave AXI clock
561 - const: slave_q2a # Slave Q2A clock
562 - const: tbu # PCIe TBU clock
563 - const: ddrss_sf_tbu # PCIe SF TBU clock
569 - const: pci # PCIe core reset
585 - const: aux # Auxiliary clock
586 - const: cfg # Configuration clock
587 - const: bus_master # Master AXI clock
588 - const: bus_slave # Slave AXI clock
589 - const: slave_q2a # Slave Q2A clock
590 - const: tbu # PCIe TBU clock
591 - const: ddrss_sf_tbu # PCIe SF TBU clock
592 - const: aggre1 # Aggre NoC PCIe1 AXI clock
593 - const: aggre0 # Aggre NoC PCIe0 AXI clock
598 - const: pci # PCIe core reset
605 - qcom,pcie-sm8450-pcie0
613 - const: pipe # PIPE clock
614 - const: pipe_mux # PIPE MUX
615 - const: phy_pipe # PIPE output clock
616 - const: ref # REFERENCE clock
617 - const: aux # Auxiliary clock
618 - const: cfg # Configuration clock
619 - const: bus_master # Master AXI clock
620 - const: bus_slave # Slave AXI clock
621 - const: slave_q2a # Slave Q2A clock
622 - const: ddrss_sf_tbu # PCIe SF TBU clock
623 - const: aggre0 # Aggre NoC PCIe0 AXI clock
624 - const: aggre1 # Aggre NoC PCIe1 AXI clock
629 - const: pci # PCIe core reset
636 - qcom,pcie-sm8450-pcie1
644 - const: pipe # PIPE clock
645 - const: pipe_mux # PIPE MUX
646 - const: phy_pipe # PIPE output clock
647 - const: ref # REFERENCE clock
648 - const: aux # Auxiliary clock
649 - const: cfg # Configuration clock
650 - const: bus_master # Master AXI clock
651 - const: bus_slave # Slave AXI clock
652 - const: slave_q2a # Slave Q2A clock
653 - const: ddrss_sf_tbu # PCIe SF TBU clock
654 - const: aggre1 # Aggre NoC PCIe1 AXI clock
659 - const: pci # PCIe core reset
675 - const: aux # Auxiliary clock
676 - const: cfg # Configuration clock
677 - const: bus_master # Master AXI clock
678 - const: bus_slave # Slave AXI clock
679 - const: slave_q2a # Slave Q2A clock
680 - const: ddrss_sf_tbu # PCIe SF TBU clock
681 - const: noc_aggr # Aggre NoC PCIe AXI clock
682 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
689 - const: pci # PCIe core reset
690 - const: link_down # PCIe link down reset
707 - const: aux # Auxiliary clock
708 - const: cfg # Configuration clock
709 - const: bus_master # Master AXI clock
710 - const: bus_slave # Slave AXI clock
711 - const: slave_q2a # Slave Q2A clock
712 - const: ddrss_sf_tbu # PCIe SF TBU clock
713 - const: noc_aggr_4 # NoC aggregate 4 clock
714 - const: noc_aggr_south_sf # NoC aggregate South SF clock
715 - const: cnoc_qx # Configuration NoC QX clock
720 - const: pci # PCIe core reset
735 - const: pipe # PIPE clock
736 - const: aux # Auxiliary clock
737 - const: cfg # Configuration clock
738 - const: bus_master # Master AXI clock
739 - const: bus_slave # Slave AXI clock
740 - const: slave_q2a # Slave Q2A clock
741 - const: sleep # PCIe Sleep clock
746 - const: pci # PCIe core reset
761 - const: aux # Auxiliary clock
762 - const: cfg # Configuration clock
763 - const: bus_master # Master AXI clock
764 - const: bus_slave # Slave AXI clock
765 - const: slave_q2a # Slave Q2A clock
770 - const: pci # PCIe core reset
794 - qcom,pcie-ipq8064v2
796 - qcom,pcie-ipq8074-gen3
827 - qcom,pcie-sm8450-pcie0
828 - qcom,pcie-sm8450-pcie1
880 - qcom,pcie-ipq8064-v2
882 - qcom,pcie-ipq8074-gen3
893 unevaluatedProperties: false
897 #include <dt-bindings/interrupt-controller/arm-gic.h>
899 compatible = "qcom,pcie-ipq8064";
900 reg = <0x1b500000 0x1000>,
903 <0x0ff00000 0x100000>;
904 reg-names = "dbi", "elbi", "parf", "config";
906 linux,pci-domain = <0>;
907 bus-range = <0x00 0xff>;
909 #address-cells = <3>;
911 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
912 <0x82000000 0 0 0x08000000 0 0x07e00000>;
913 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
914 interrupt-names = "msi";
915 #interrupt-cells = <1>;
916 interrupt-map-mask = <0 0 0 0x7>;
917 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
918 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
919 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
920 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
926 clock-names = "core", "iface", "phy", "aux", "ref";
933 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
934 pinctrl-0 = <&pcie_pins_default>;
935 pinctrl-names = "default";
936 vdda-supply = <&pm8921_s3>;
937 vdda_phy-supply = <&pm8921_lvs6>;
938 vdda_refclk-supply = <&ext_3p3v>;
941 #include <dt-bindings/interrupt-controller/arm-gic.h>
942 #include <dt-bindings/gpio/gpio.h>
944 compatible = "qcom,pcie-apq8084";
945 reg = <0xfc520000 0x2000>,
949 reg-names = "parf", "dbi", "elbi", "config";
951 linux,pci-domain = <0>;
952 bus-range = <0x00 0xff>;
954 #address-cells = <3>;
956 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
957 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
958 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "msi";
960 #interrupt-cells = <1>;
961 interrupt-map-mask = <0 0 0 0x7>;
962 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
963 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
964 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
965 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
970 clock-names = "iface", "master_bus", "slave_bus", "aux";
972 reset-names = "core";
973 power-domains = <&gcc 1>;
974 vdda-supply = <&pma8084_l3>;
976 phy-names = "pciephy";
977 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
978 pinctrl-0 = <&pcie0_pins_default>;
979 pinctrl-names = "default";