Bindings/phy/phy-hi3798cv200-combphy.txt

   1 HiSilicon STB PCIE/SATA/USB3 PHY
   2
   3 Required properties:
   4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
   5 - reg: Should be the address space for COMBPHY configuration and state
   6   registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
   7   PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
   8 - #phy-cells: Should be 1.  The cell number is used to select the phy mode
   9   as defined in <dt-bindings/phy/phy.h>.
  10 - clocks: The phandle to clock provider and clock specifier pair.
  11 - resets: The phandle to reset controller and reset specifier pair.
  12
  13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
  14
  15 Optional properties:
  16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
  17   but a fixed mode setting, the property should be present to specify
  18   the particular mode.
  19 - hisilicon,mode-select-bits: If the phy device support mode select,
  20   this property should be present to specify the register bits in
  21   peripheral controller, as a 3 integers tuple:
  22   <register_offset bit_shift bit_mask>.
  23
  24 Notes:
  25 - Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
  26   one of them should be present.
  27 - The device node should be a child of peripheral controller that contains
  28   COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
  29   Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
  30   bindings.
  31
  32 Examples:
  33
  34 perictrl: peripheral-controller@8a20000 {
  35         compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
  36                      "simple-mfd";
  37         reg = <0x8a20000 0x1000>;
  38         #address-cells = <1>;
  39         #size-cells = <1>;
  40         ranges = <0x0 0x8a20000 0x1000>;
  41
  42         combphy0: phy@850 {
  43                 compatible = "hisilicon,hi3798cv200-combphy";
  44                 reg = <0x850 0x8>;
  45                 #phy-cells = <1>;
  46                 clocks = <&crg HISTB_COMBPHY0_CLK>;
  47                 resets = <&crg 0x188 4>;
  48                 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
  49         };
  50
  51         combphy1: phy@858 {
  52                 compatible = "hisilicon,hi3798cv200-combphy";
  53                 reg = <0x858 0x8>;
  54                 #phy-cells = <1>;
  55                 clocks = <&crg HISTB_COMBPHY1_CLK>;
  56                 resets = <&crg 0x188 12>;
  57                 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
  58         };
  59 };