1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
26 - qcom,sdm845-qmp-pcie-phy
27 - qcom,sdx55-qmp-pcie-phy
28 - qcom,sdx65-qmp-gen4x2-pcie-phy
29 - qcom,sm8150-qmp-gen3x1-pcie-phy
30 - qcom,sm8150-qmp-gen3x2-pcie-phy
31 - qcom,sm8250-qmp-gen3x1-pcie-phy
32 - qcom,sm8250-qmp-gen3x2-pcie-phy
33 - qcom,sm8250-qmp-modem-pcie-phy
34 - qcom,sm8350-qmp-gen3x1-pcie-phy
35 - qcom,sm8450-qmp-gen3x1-pcie-phy
36 - qcom,sm8450-qmp-gen4x2-pcie-phy
37 - qcom,sm8550-qmp-gen3x2-pcie-phy
38 - qcom,sm8550-qmp-gen4x2-pcie-phy
54 - enum: [rchng, refgen]
76 vdda-qref-supply: true
79 description: PCIe 4-lane configuration
80 $ref: /schemas/types.yaml#/definitions/phandle-array
83 - description: phandle of TCSR syscon
84 - description: offset of PCIe 4-lane configuration register
85 - description: offset of configuration bit for this PHY
109 additionalProperties: false
117 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
122 - description: port a
123 - description: port b
125 - qcom,4ln-config-sel
136 - qcom,sc8180x-qmp-pcie-phy
137 - qcom,sdm845-qhp-pcie-phy
138 - qcom,sdm845-qmp-pcie-phy
139 - qcom,sdx55-qmp-pcie-phy
140 - qcom,sm8150-qmp-gen3x1-pcie-phy
141 - qcom,sm8150-qmp-gen3x2-pcie-phy
142 - qcom,sm8250-qmp-gen3x1-pcie-phy
143 - qcom,sm8250-qmp-gen3x2-pcie-phy
144 - qcom,sm8250-qmp-modem-pcie-phy
145 - qcom,sm8350-qmp-gen3x1-pcie-phy
146 - qcom,sm8450-qmp-gen3x1-pcie-phy
147 - qcom,sm8450-qmp-gen3x2-pcie-phy
148 - qcom,sm8550-qmp-gen3x2-pcie-phy
149 - qcom,sm8550-qmp-gen4x2-pcie-phy
162 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
163 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
164 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
177 - qcom,sa8775p-qmp-gen4x2-pcie-phy
178 - qcom,sa8775p-qmp-gen4x4-pcie-phy
191 - qcom,sm8550-qmp-gen4x2-pcie-phy
207 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
209 pcie2b_phy: phy@1c18000 {
210 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
211 reg = <0x01c18000 0x2000>;
213 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
214 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
215 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
216 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
217 <&gcc GCC_PCIE_2B_PIPE_CLK>,
218 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
219 clock-names = "aux", "cfg_ahb", "ref", "rchng",
222 power-domains = <&gcc PCIE_2B_GDSC>;
224 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
227 vdda-phy-supply = <&vreg_l6d>;
228 vdda-pll-supply = <&vreg_l4d>;
231 clock-output-names = "pcie_2b_pipe_clk";
236 pcie2a_phy: phy@1c24000 {
237 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
238 reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
240 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
241 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
242 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
243 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
244 <&gcc GCC_PCIE_2A_PIPE_CLK>,
245 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
246 clock-names = "aux", "cfg_ahb", "ref", "rchng",
249 power-domains = <&gcc PCIE_2A_GDSC>;
251 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
254 vdda-phy-supply = <&vreg_l6d>;
255 vdda-pll-supply = <&vreg_l4d>;
257 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
260 clock-output-names = "pcie_2a_pipe_clk";