1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay pin controller
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
13 Intel Keem Bay SoC integrates a pin controller which enables control
14 of pin directions, input/output values and configuration
15 for a total of 80 pins.
19 const: intel,keembay-pinctrl
30 description: The number of GPIOs exposed.
35 Specifies the interrupt lines to be used by the controller.
36 Each interrupt line is shared by upto 4 GPIO lines.
39 interrupt-controller: true
47 additionalProperties: false
50 Child nodes can be specified to contain pin configuration information,
51 which can then be utilized by pinctrl client devices.
52 The following properties are supported.
57 The name(s) of the pins to be configured in the child node.
58 Supported pin names are "GPIO0" up to "GPIO79".
67 description: IO pads drive strength in milli Ampere.
77 description: GPIO slew rate control.
82 additionalProperties: false
91 - interrupt-controller
96 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 #include <dt-bindings/interrupt-controller/irq.h>
100 compatible = "intel,keembay-pinctrl";
101 reg = <0x600b0000 0x88>,
106 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
120 compatible = "intel,keembay-pinctrl";
121 reg = <0x600c0000 0x88>,
126 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-controller;
135 #interrupt-cells = <2>;