1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7981 Pin Controller
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek's MT7981 Pin controller is used to control SoC pins.
18 - mediatek,mt7981-pinctrl
41 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
42 the amount of cells must be specified as 2. See the below mentioned gpio
43 binding representation for description of particular cells.
48 description: GPIO valid number range.
50 interrupt-controller: true
71 additionalProperties: false
76 additionalProperties: false
78 pinmux configuration nodes.
80 The following table shows the effective values of "group", "function"
81 properties and chip pinout pins
83 groups function pins (in pin#)
84 ---------------------------------------------------------------------
85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
89 "watchdog" "watchdog" 2
90 "pcie_pereset" "pcie" 3
91 "jtag" "jtag" 4, 5, 6, 7, 8
92 "wm_jtag_0" "jtag" 4, 5, 6, 7, 8
93 "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13
94 "uart2_0" "uart" 4, 5, 6, 7
96 "pta_ext_0" "pta" 4, 5, 6
98 "net_wo0_uart_txd_0" "uart" 8
99 "spi1_0" "spi" 4, 5, 6, 7
102 "wm_aice1" "wa_aice" 9, 10
107 "net_wo0_uart_txd_1" "uart" 14
108 "net_wo0_uart_txd_2" "uart" 15
110 "pcm" "pcm" 9, 10, 11, 12, 13, 25
111 "watchdog1" "watchdog" 13
112 "udi" "udi" 9, 10, 11, 12, 13
114 "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23,
117 "snfi" "flash" 16, 17, 18, 19, 20, 21
118 "spi0" "spi" 16, 17, 18, 19
119 "spi0_wp_hold" "spi" 20, 21
120 "spi1_1" "spi" 22, 23, 24, 25
121 "spi2" "spi" 26, 27, 28, 29
122 "spi2_wp_hold" "spi" 30, 31
123 "uart1_0" "uart" 16, 17, 18, 19
124 "uart1_1" "uart" 26, 27, 28, 29
125 "uart2_1" "uart" 22, 23, 24, 25
126 "pta_ext_1" "pta" 22, 23, 24
127 "wm_aurt_1" "uart" 20, 21
128 "wm_aurt_2" "uart" 30, 31
129 "wm_jtag_1" "jtag" 20, 21, 22, 23, 24
130 "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29
131 "wa_aice3" "wa_aice" 28, 20
132 "wm_aice2" "wa_aice" 30, 31
133 "i2c0_1" "i2c" 30, 31
134 "u2_phy_i2c" "i2c" 30, 31
135 "uart0" "uart" 32, 33
136 "sgmii1_phy_i2c" "i2c" 32, 33
137 "u3_phy_i2c" "i2c" 32, 33
138 "sgmii0_phy_i2c" "i2c" 32, 33
140 "pcie_wake" "pcie" 35
141 "i2c0_2" "i2c" 36, 37
142 "smi_mdc_mdio" "eth" 36, 37
143 "gbe_ext_mdc_mdio" "eth" 36, 37
144 "wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48,
145 49, 50, 51, 52, 53, 54, 55, 56
147 "wf0_mode3" "eth" 45, 46, 47, 48, 49, 51
152 "mt7531_int" "eth" 38
153 "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22,
156 $ref: /schemas/pinctrl/pinmux-node.yaml
160 A string containing the name of the function to mux to the group.
161 enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led,
162 pwm, spi, uart, watchdog, flash, pcie]
165 An array of strings. Each string contains the name of a group.
179 enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2]
187 enum: [dfd, dfd_ntrst]
195 enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1]
203 enum: [pta_ext_0, pta_ext_1]
243 enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3,
252 enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c,
253 sgmii0_phy_i2c, i2c0_2]
261 enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0,
271 enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1]
281 enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2,
292 enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0,
293 net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0,
294 uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0]
311 enum: [emmc_45, snfi]
321 enum: [pcie_clk, pcie_wake, pcie_pereset]
326 additionalProperties: false
327 description: pinconf configuration nodes.
328 $ref: /schemas/pinctrl/pincfg-node.yaml
333 An array of strings. Each string contains the name of a pin.
335 enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N,
336 JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N,
337 WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK,
338 WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI,
339 SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK,
340 SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI,
341 SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD,
342 UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MDIO,
343 GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB,
344 WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3,
345 WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8,
354 description: normal pull up.
355 - enum: [100, 101, 102, 103]
357 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
358 dt-bindings/pinctrl/mt65xx.h.
363 description: normal pull down.
364 - enum: [100, 101, 102, 103]
366 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
367 dt-bindings/pinctrl/mt65xx.h.
379 input-schmitt-enable: true
381 input-schmitt-disable: true
384 enum: [2, 4, 6, 8, 10, 12, 14, 16]
386 mediatek,pull-up-adv:
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
389 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
390 are described as below:
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
394 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
395 $ref: /schemas/types.yaml#/definitions/uint32
398 mediatek,pull-down-adv:
400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
401 Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
402 are described as below:
403 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
404 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
405 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
406 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
407 $ref: /schemas/types.yaml#/definitions/uint32
413 additionalProperties: false
417 #include <dt-bindings/interrupt-controller/irq.h>
418 #include <dt-bindings/interrupt-controller/arm-gic.h>
419 #include <dt-bindings/pinctrl/mt65xx.h>
422 #address-cells = <2>;
424 pio: pinctrl@11d00000 {
425 compatible = "mediatek,mt7981-pinctrl";
426 reg = <0 0x11d00000 0 0x1000>,
427 <0 0x11c00000 0 0x1000>,
428 <0 0x11c10000 0 0x1000>,
429 <0 0x11d20000 0 0x1000>,
430 <0 0x11e00000 0 0x1000>,
431 <0 0x11e20000 0 0x1000>,
432 <0 0x11f00000 0 0x1000>,
433 <0 0x11f10000 0 0x1000>,
434 <0 0x1000b000 0 0x1000>;
435 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
436 "iocfg_rb", "iocfg_lb", "iocfg_bl",
437 "iocfg_tm", "iocfg_tl", "eint";
440 gpio-ranges = <&pio 0 0 56>;
441 interrupt-controller;
442 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-parent = <&gic>;
444 #interrupt-cells = <2>;
446 mdio_pins: mdio-pins {
449 groups = "smi_mdc_mdio";
453 spi0_flash_pins: spi0-pins {
456 groups = "spi0", "spi0_wp_hold";
460 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
461 drive-strength = <MTK_DRIVE_8mA>;
462 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
466 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
467 drive-strength = <MTK_DRIVE_8mA>;
468 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
472 pcie_pins: pcie-pins {
475 groups = "pcie_clk", "pcie_wake", "pcie_pereset";