1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. MDM9615 TLMM block
10 - Bjorn Andersson <andersson@kernel.org>
12 description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 const: qcom,mdm9615-pinctrl
26 interrupt-controller: true
27 '#interrupt-cells': true
36 additionalProperties: false
41 - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
44 $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
45 additionalProperties: false
48 qcom-mdm9615-pinctrl-state:
51 Pinctrl node's client devices use subnodes for desired pin configuration.
52 Client device subnodes use below standard properties.
53 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54 unevaluatedProperties: false
59 List of gpio pins affected by the properties specified in this
62 pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
68 Specify the alternative function to be configured for the specified
71 enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
72 sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]
79 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 tlmm: pinctrl@1000000 {
81 compatible = "qcom,mdm9615-pinctrl";
82 reg = <0x01000000 0x300000>;
83 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
85 gpio-ranges = <&msmgpio 0 0 88>;
88 #interrupt-cells = <2>;
91 pins = "gpio8", "gpio9", "gpio10", "gpio11";
100 function = "gsbi5_i2c";
101 drive-strength = <8>;
107 function = "gsbi5_i2c";
108 drive-strength = <2>;