Bindings/pinctrl/qcom,sc8180x-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SC8180X TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.
  14
  15 allOf:
  16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sc8180x-tlmm
  21
  22   reg:
  23     maxItems: 3
  24
  25   reg-names:
  26     items:
  27       - const: west
  28       - const: east
  29       - const: south
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   interrupt-controller: true
  35   '#interrupt-cells': true
  36   gpio-controller: true
  37   gpio-reserved-ranges: true
  38   '#gpio-cells': true
  39   gpio-ranges: true
  40   wakeup-parent: true
  41
  42 required:
  43   - compatible
  44   - reg
  45   - reg-names
  46
  47 additionalProperties: false
  48
  49 patternProperties:
  50   "-state$":
  51     oneOf:
  52       - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
  53       - patternProperties:
  54           "-pins$":
  55             $ref: "#/$defs/qcom-sc8180x-tlmm-state"
  56         additionalProperties: false
  57
  58 $defs:
  59   qcom-sc8180x-tlmm-state:
  60     type: object
  61     description:
  62       Pinctrl node's client devices use subnodes for desired pin configuration.
  63       Client device subnodes use below standard properties.
  64     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  65     unevaluatedProperties: false
  66
  67     properties:
  68       pins:
  69         description:
  70           List of gpio pins affected by the properties specified in this
  71           subnode.
  72         items:
  73           oneOf:
  74             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
  75             - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
  76         minItems: 1
  77         maxItems: 16
  78
  79       function:
  80         description:
  81           Specify the alternative function to be configured for the specified
  82           pins.
  83
  84         enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
  85                 atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
  86                 atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
  87                 cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
  88                 cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
  89                 cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
  90                 dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
  91                 gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
  92                 hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
  93                 mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
  94                 mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
  95                 pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
  96                 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
  97                 qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
  98                 qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
  99                 qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
 100                 qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
 101                 sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
 102                 tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
 103                 usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
 104                 wlan1_adc, wlan2_adc, wmss_reset ]
 105
 106     required:
 107       - pins
 108
 109 examples:
 110   - |
 111     #include <dt-bindings/interrupt-controller/arm-gic.h>
 112     pinctrl@3100000 {
 113         compatible = "qcom,sc8180x-tlmm";
 114         reg = <0x03100000 0x300000>,
 115               <0x03500000 0x700000>,
 116               <0x03d00000 0x300000>;
 117         reg-names = "west", "east", "south";
 118         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 119         gpio-controller;
 120         #gpio-cells = <2>;
 121         interrupt-controller;
 122         #interrupt-cells = <2>;
 123         gpio-ranges = <&tlmm 0 0 190>;
 124
 125         gpio-wo-subnode-state {
 126             pins = "gpio1";
 127             function = "gpio";
 128         };
 129
 130         uart-w-subnodes-state {
 131             rx-pins {
 132                 pins = "gpio4";
 133                 function = "qup6";
 134                 bias-pull-up;
 135             };
 136
 137             tx-pins {
 138                 pins = "gpio5";
 139                 function = "qup6";
 140                 bias-disable;
 141             };
 142         };
 143     };
 144 ...