1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
16 decimal integer) as specified by User's Manual of respective SoC.
22 - const: samsung,exynosautov9-uart
23 - const: samsung,exynos850-uart
27 - samsung,s3c6400-uart
28 - samsung,s5pv210-uart
29 - samsung,exynos4210-uart
30 - samsung,exynos5433-uart
31 - samsung,exynos850-uart
38 The size (in bytes) of the IO accesses that should be performed
47 description: N = 0 is allowed for SoCs without internal baud clock mux.
51 - pattern: '^clk_uart_baud[0-3]$'
52 - pattern: '^clk_uart_baud[0-3]$'
53 - pattern: '^clk_uart_baud[0-3]$'
54 - pattern: '^clk_uart_baud[0-3]$'
58 - description: DMA controller phandle and request line for RX
59 - description: DMA controller phandle and request line for TX
67 description: RX interrupt and optionally TX interrupt.
74 samsung,uart-fifosize:
75 description: The fifo size supported by the UART channel.
76 $ref: /schemas/types.yaml#/definitions/uint32
94 - samsung,s5pv210-uart
104 - pattern: '^clk_uart_baud[0-1]$'
105 - pattern: '^clk_uart_baud[0-1]$'
114 - samsung,exynos4210-uart
115 - samsung,exynos5433-uart
123 - const: clk_uart_baud0
125 unevaluatedProperties: false
129 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
131 uart0: serial@7f005000 {
132 compatible = "samsung,s3c6400-uart";
133 reg = <0x7f005000 0x100>;
134 interrupt-parent = <&vic1>;
136 clock-names = "uart", "clk_uart_baud2",
138 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
140 samsung,uart-fifosize = <16>;