Bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
   8
   9 maintainers:
  10   - Herve Codina <herve.codina@bootlin.com>
  11
  12 description:
  13   The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
  14   Its purpose is to route some TDM time-slots to other internal serial
  15   controllers.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - enum:
  21           - fsl,mpc885-tsa
  22           - fsl,mpc866-tsa
  23       - const: fsl,cpm1-tsa
  24
  25   reg:
  26     items:
  27       - description: SI (Serial Interface) register base
  28       - description: SI RAM base
  29
  30   reg-names:
  31     items:
  32       - const: si_regs
  33       - const: si_ram
  34
  35   '#address-cells':
  36     const: 1
  37
  38   '#size-cells':
  39     const: 0
  40
  41 patternProperties:
  42   '^tdm@[0-1]$':
  43     description:
  44       The TDM managed by this controller
  45     type: object
  46
  47     additionalProperties: false
  48
  49     properties:
  50       reg:
  51         minimum: 0
  52         maximum: 1
  53         description:
  54           The TDM number for this TDM, 0 for TDMa and 1 for TDMb
  55
  56       fsl,common-rxtx-pins:
  57         $ref: /schemas/types.yaml#/definitions/flag
  58         description:
  59           The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
  60           clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
  61           Without the 'fsl,common-rxtx-pins' property, the four pins are used.
  62           With the 'fsl,common-rxtx-pins' property, two pins are used.
  63
  64       clocks:
  65         minItems: 2
  66         items:
  67           - description: External clock connected to L1RSYNC pin
  68           - description: External clock connected to L1RCLK pin
  69           - description: External clock connected to L1TSYNC pin
  70           - description: External clock connected to L1TCLK pin
  71
  72       clock-names:
  73         minItems: 2
  74         items:
  75           - const: l1rsync
  76           - const: l1rclk
  77           - const: l1tsync
  78           - const: l1tclk
  79
  80       fsl,rx-frame-sync-delay-bits:
  81         enum: [0, 1, 2, 3]
  82         default: 0
  83         description: |
  84           Receive frame sync delay in number of bits.
  85           Indicates the delay between the Rx sync and the first bit of the Rx
  86           frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
  87
  88       fsl,tx-frame-sync-delay-bits:
  89         enum: [0, 1, 2, 3]
  90         default: 0
  91         description: |
  92           Transmit frame sync delay in number of bits.
  93           Indicates the delay between the Tx sync and the first bit of the Tx
  94           frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
  95
  96       fsl,clock-falling-edge:
  97         $ref: /schemas/types.yaml#/definitions/flag
  98         description:
  99           Data is sent on falling edge of the clock (and received on the rising
 100           edge). If 'clock-falling-edge' is not present, data is sent on the
 101           rising edge (and received on the falling edge).
 102
 103       fsl,fsync-rising-edge:
 104         $ref: /schemas/types.yaml#/definitions/flag
 105         description:
 106           Frame sync pulses are sampled with the rising edge of the channel
 107           clock. If 'fsync-rising-edge' is not present, pulses are sampled with
 108           the falling edge.
 109
 110       fsl,double-speed-clock:
 111         $ref: /schemas/types.yaml#/definitions/flag
 112         description:
 113           The channel clock is twice the data rate.
 114
 115     patternProperties:
 116       '^fsl,[rt]x-ts-routes$':
 117         $ref: /schemas/types.yaml#/definitions/uint32-matrix
 118         description: |
 119           A list of tuple that indicates the Tx or Rx time-slots routes.
 120         items:
 121           items:
 122             - description:
 123                 The number of time-slots
 124               minimum: 1
 125               maximum: 64
 126             - description: |
 127                 The source (Tx) or destination (Rx) serial interface
 128                 (dt-bindings/soc/cpm1-fsl,tsa.h defines these values)
 129                  - 0: No destination
 130                  - 1: SCC2
 131                  - 2: SCC3
 132                  - 3: SCC4
 133                  - 4: SMC1
 134                  - 5: SMC2
 135               enum: [0, 1, 2, 3, 4, 5]
 136         minItems: 1
 137         maxItems: 64
 138
 139     allOf:
 140       # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
 141       # Else, the 4 clocks must be present.
 142       - if:
 143           required:
 144             - fsl,common-rxtx-pins
 145         then:
 146           properties:
 147             clocks:
 148               maxItems: 2
 149             clock-names:
 150               maxItems: 2
 151         else:
 152           properties:
 153             clocks:
 154               minItems: 4
 155             clock-names:
 156               minItems: 4
 157
 158     required:
 159       - reg
 160       - clocks
 161       - clock-names
 162
 163 required:
 164   - compatible
 165   - reg
 166   - reg-names
 167   - '#address-cells'
 168   - '#size-cells'
 169
 170 additionalProperties: false
 171
 172 examples:
 173   - |
 174     #include <dt-bindings/soc/cpm1-fsl,tsa.h>
 175
 176     tsa@ae0 {
 177         compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
 178         reg = <0xae0 0x10>,
 179               <0xc00 0x200>;
 180         reg-names = "si_regs", "si_ram";
 181
 182         #address-cells = <1>;
 183         #size-cells = <0>;
 184
 185         tdm@0 {
 186             /* TDMa */
 187             reg = <0>;
 188
 189             clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
 190             clock-names = "l1rsync", "l1rclk";
 191
 192             fsl,common-rxtx-pins;
 193             fsl,fsync-rising-edge;
 194
 195             fsl,tx-ts-routes = <2 0>,             /* TS 0..1 */
 196                            <24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */
 197                            <1 0>,                 /* TS 26 */
 198                            <5 FSL_CPM_TSA_SCC3>;  /* TS 27..31 */
 199
 200             fsl,rx-ts-routes = <2 0>,             /* TS 0..1 */
 201                            <24 FSL_CPM_TSA_SCC4>, /* 2..25 */
 202                            <1 0>,                 /* TS 26 */
 203                            <5 FSL_CPM_TSA_SCC3>;  /* TS 27..31 */
 204         };
 205     };