Bindings/soc/qcom/qcom,aoss-qmp.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Always-On Subsystem side channel
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description:
  13   This binding describes the hardware component responsible for side channel
  14   requests to the always-on subsystem (AOSS), used for certain power management
  15   requests that is not handled by the standard RPMh interface. Each client in the
  16   SoC has its own block of message RAM and IRQ for communication with the AOSS.
  17   The protocol used to communicate in the message RAM is known as Qualcomm
  18   Messaging Protocol (QMP)
  19
  20   The AOSS side channel exposes control over a set of resources, used to control
  21   a set of debug related clocks and to affect the low power state of resources
  22   related to the secondary subsystems.
  23
  24 properties:
  25   compatible:
  26     items:
  27       - enum:
  28           - qcom,qdu1000-aoss-qmp
  29           - qcom,sa8775p-aoss-qmp
  30           - qcom,sc7180-aoss-qmp
  31           - qcom,sc7280-aoss-qmp
  32           - qcom,sc8180x-aoss-qmp
  33           - qcom,sc8280xp-aoss-qmp
  34           - qcom,sdm845-aoss-qmp
  35           - qcom,sm6350-aoss-qmp
  36           - qcom,sm8150-aoss-qmp
  37           - qcom,sm8250-aoss-qmp
  38           - qcom,sm8350-aoss-qmp
  39           - qcom,sm8450-aoss-qmp
  40           - qcom,sm8550-aoss-qmp
  41           - qcom,sm8650-aoss-qmp
  42           - qcom,x1e80100-aoss-qmp
  43       - const: qcom,aoss-qmp
  44
  45   reg:
  46     maxItems: 1
  47     description:
  48       The base address and size of the message RAM for this client's
  49       communication with the AOSS
  50
  51   interrupts:
  52     maxItems: 1
  53     description:
  54       Should specify the AOSS message IRQ for this client
  55
  56   mboxes:
  57     maxItems: 1
  58     description:
  59       Reference to the mailbox representing the outgoing doorbell in APCS for
  60       this client, as described in mailbox/mailbox.txt
  61
  62   "#clock-cells":
  63     const: 0
  64     description:
  65       The single clock represents the QDSS clock.
  66
  67 required:
  68   - compatible
  69   - reg
  70   - interrupts
  71   - mboxes
  72   - "#clock-cells"
  73
  74 additionalProperties: false
  75
  76 patternProperties:
  77   "^(cx|mx|ebi)$":
  78     type: object
  79     description:
  80       The AOSS side channel also provides the controls for three cooling devices,
  81       these are expressed as subnodes of the QMP node. The name of the node is
  82       used to identify the resource and must therefore be "cx", "mx" or "ebi".
  83
  84     properties:
  85       "#cooling-cells":
  86         const: 2
  87
  88     required:
  89       - "#cooling-cells"
  90
  91     additionalProperties: false
  92
  93 examples:
  94   - |
  95     #include <dt-bindings/interrupt-controller/arm-gic.h>
  96
  97     aoss_qmp: qmp@c300000 {
  98       compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
  99       reg = <0x0c300000 0x100000>;
 100       interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
 101       mboxes = <&apss_shared 0>;
 102
 103       #clock-cells = <0>;
 104
 105       cx_cdev: cx {
 106         #cooling-cells = <2>;
 107       };
 108
 109       mx_cdev: mx {
 110         #cooling-cells = <2>;
 111       };
 112     };
 113 ...