Bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Socionext UniPhier SoC AHCI glue layer
   8
   9 maintainers:
  10   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
  11
  12 description: |+
  13   AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
  14   logic handling signals to AHCI host controller inside AHCI component.
  15
  16 properties:
  17   compatible:
  18     items:
  19       - enum:
  20           - socionext,uniphier-pro4-ahci-glue
  21           - socionext,uniphier-pxs2-ahci-glue
  22           - socionext,uniphier-pxs3-ahci-glue
  23       - const: simple-mfd
  24
  25   reg:
  26     maxItems: 1
  27
  28   "#address-cells":
  29     const: 1
  30
  31   "#size-cells":
  32     const: 1
  33
  34   ranges: true
  35
  36 patternProperties:
  37   "^reset-controller@[0-9a-f]+$":
  38     $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
  39
  40   "phy@[0-9a-f]+$":
  41     $ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
  42
  43 required:
  44   - compatible
  45   - reg
  46
  47 additionalProperties: false
  48
  49 examples:
  50   - |
  51     sata-controller@65700000 {
  52         compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
  53         reg = <0x65b00000 0x400>;
  54         #address-cells = <1>;
  55         #size-cells = <1>;
  56         ranges = <0 0x65700000 0x100>;
  57
  58         reset-controller@0 {
  59             compatible = "socionext,uniphier-pxs3-ahci-reset";
  60             reg = <0x0 0x4>;
  61             clock-names = "link";
  62             clocks = <&sys_clk 28>;
  63             reset-names = "link";
  64             resets = <&sys_rst 28>;
  65             #reset-cells = <1>;
  66         };
  67
  68         phy@10 {
  69             compatible = "socionext,uniphier-pxs3-ahci-phy";
  70             reg = <0x10 0x10>;
  71             clock-names = "link", "phy";
  72             clocks = <&sys_clk 28>, <&sys_clk 30>;
  73             reset-names = "link", "phy";
  74             resets = <&sys_rst 28>, <&sys_rst 30>;
  75             #phy-cells = <0>;
  76         };
  77     };