Bindings/spi/qcom,spi-geni-qcom.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
   8
   9 maintainers:
  10   - Andy Gross <agross@kernel.org>
  11   - Bjorn Andersson <bjorn.andersson@linaro.org>
  12   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  13
  14 description:
  15   The QUP v3 core is a GENI based AHB slave that provides a common data path
  16   (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
  17   mini-core.
  18
  19   SPI in master mode supports up to 50MHz, up to four chip selects,
  20   programmable data path from 4 bits to 32 bits and numerous protocol variants.
  21
  22   SPI Controller nodes must be child of GENI based Qualcomm Universal
  23   Peripharal. Please refer GENI based QUP wrapper controller node bindings
  24   described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
  25
  26 allOf:
  27   - $ref: /schemas/spi/spi-controller.yaml#
  28
  29 properties:
  30   compatible:
  31     const: qcom,geni-spi
  32
  33   clocks:
  34     maxItems: 1
  35
  36   clock-names:
  37     const: se
  38
  39   dmas:
  40     maxItems: 2
  41
  42   dma-names:
  43     items:
  44       - const: tx
  45       - const: rx
  46
  47   interconnects:
  48     minItems: 2
  49     maxItems: 3
  50
  51   interconnect-names:
  52     minItems: 2
  53     items:
  54       - const: qup-core
  55       - const: qup-config
  56       - const: qup-memory
  57
  58   interrupts:
  59     maxItems: 1
  60
  61   operating-points-v2: true
  62
  63   power-domains:
  64     maxItems: 1
  65
  66   reg:
  67     maxItems: 1
  68
  69 required:
  70   - compatible
  71   - clocks
  72   - clock-names
  73   - interrupts
  74   - reg
  75
  76 unevaluatedProperties: false
  77
  78 examples:
  79   - |
  80     #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  81     #include <dt-bindings/interconnect/qcom,sc7180.h>
  82     #include <dt-bindings/interrupt-controller/arm-gic.h>
  83     #include <dt-bindings/power/qcom-rpmpd.h>
  84
  85     spi@880000 {
  86         compatible = "qcom,geni-spi";
  87         reg = <0x00880000 0x4000>;
  88         clock-names = "se";
  89         clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&qup_spi0_default>;
  92         interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
  93         #address-cells = <1>;
  94         #size-cells = <0>;
  95         power-domains = <&rpmhpd SC7180_CX>;
  96         operating-points-v2 = <&qup_opp_table>;
  97         interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
  98                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
  99         interconnect-names = "qup-core", "qup-config";
 100     };
 101
 102   - |
 103     #include <dt-bindings/dma/qcom-gpi.h>
 104
 105     spi@884000 {
 106         compatible = "qcom,geni-spi";
 107         reg = <0x00884000 0x4000>;
 108         clock-names = "se";
 109         clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 110         dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 111                <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 112         dma-names = "tx", "rx";
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&qup_spi1_default>;
 115         interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 116         #address-cells = <1>;
 117         #size-cells = <0>;
 118     };