Bindings/timer/sifive,clint.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SiFive Core Local Interruptor
   8
   9 maintainers:
  10   - Palmer Dabbelt <palmer@dabbelt.com>
  11   - Anup Patel <anup.patel@wdc.com>
  12
  13 description:
  14   SiFive (and other RISC-V) SOCs include an implementation of the SiFive
  15   Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
  16   interrupts. It directly connects to the timer and inter-processor interrupt
  17   lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
  18   interrupt controller is the parent interrupt controller for CLINT device.
  19   The clock frequency of CLINT is specified via "timebase-frequency" DT
  20   property of "/cpus" DT node. The "timebase-frequency" DT property is
  21   described in Documentation/devicetree/bindings/riscv/cpus.yaml
  22
  23   T-Head C906/C910 CPU cores include an implementation of CLINT too, however
  24   their implementation lacks a memory-mapped MTIME register, thus not
  25   compatible with SiFive ones.
  26
  27 properties:
  28   compatible:
  29     oneOf:
  30       - items:
  31           - enum:
  32               - canaan,k210-clint       # Canaan Kendryte K210
  33               - sifive,fu540-c000-clint # SiFive FU540
  34               - starfive,jh7100-clint   # StarFive JH7100
  35               - starfive,jh7110-clint   # StarFive JH7110
  36           - const: sifive,clint0        # SiFive CLINT v0 IP block
  37       - items:
  38           - enum:
  39               - allwinner,sun20i-d1-clint
  40               - sophgo,cv1800b-clint
  41               - thead,th1520-clint
  42           - const: thead,c900-clint
  43       - items:
  44           - const: sifive,clint0
  45           - const: riscv,clint0
  46         deprecated: true
  47         description: For the QEMU virt machine only
  48
  49     description:
  50       Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
  51       when compatible with a SiFive CLINT.  Please refer to
  52       sifive-blocks-ip-versioning.txt for details regarding the latter.
  53
  54   reg:
  55     maxItems: 1
  56
  57   interrupts-extended:
  58     minItems: 1
  59     maxItems: 4095
  60
  61 additionalProperties: false
  62
  63 required:
  64   - compatible
  65   - reg
  66   - interrupts-extended
  67
  68 examples:
  69   - |
  70     timer@2000000 {
  71       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
  72       interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
  73                             <&cpu2intc 3>, <&cpu2intc 7>,
  74                             <&cpu3intc 3>, <&cpu3intc 7>,
  75                             <&cpu4intc 3>, <&cpu4intc 7>;
  76        reg = <0x2000000 0x10000>;
  77     };
  78 ...