1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Universal Flash Storage (UFS) Controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
42 - const: jedec,ufs-2.0
78 $ref: /schemas/types.yaml#/definitions/phandle
79 description: phandle to the Inline Crypto Engine node
106 GPIO connected to the RESET pin of the UFS memory device.
113 - $ref: ufs-common.yaml
123 - qcom,sc8280xp-ufshc
137 - const: bus_aggr_clk
139 - const: core_clk_unipro
141 - const: tx_lane0_sync_clk
142 - const: rx_lane0_sync_clk
143 - const: rx_lane1_sync_clk
166 - const: bus_aggr_clk
168 - const: core_clk_unipro
170 - const: tx_lane0_sync_clk
171 - const: rx_lane0_sync_clk
172 - const: rx_lane1_sync_clk
173 - const: ice_core_clk
195 - const: core_clk_src
198 - const: bus_aggr_clk
200 - const: core_clk_unipro_src
201 - const: core_clk_unipro
202 - const: core_clk_ice
204 - const: tx_lane0_sync_clk
205 - const: rx_lane0_sync_clk
226 - const: bus_aggr_clk
228 - const: core_clk_unipro
230 - const: tx_lane0_sync_clk
231 - const: rx_lane0_sync_clk
232 - const: ice_core_clk
241 # TODO: define clock bindings for qcom,msm8994-ufshc
262 unevaluatedProperties: false
266 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
267 #include <dt-bindings/clock/qcom,rpmh.h>
268 #include <dt-bindings/gpio/gpio.h>
269 #include <dt-bindings/interconnect/qcom,sm8450.h>
270 #include <dt-bindings/interrupt-controller/arm-gic.h>
273 #address-cells = <2>;
277 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
279 reg = <0 0x01d84000 0 0x3000>;
280 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
281 phys = <&ufs_mem_phy_lanes>;
282 phy-names = "ufsphy";
283 lanes-per-direction = <2>;
285 resets = <&gcc GCC_UFS_PHY_BCR>;
287 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
289 vcc-supply = <&vreg_l7b_2p5>;
290 vcc-max-microamp = <1100000>;
291 vccq-supply = <&vreg_l9b_1p2>;
292 vccq-max-microamp = <1200000>;
294 power-domains = <&gcc UFS_PHY_GDSC>;
295 iommus = <&apps_smmu 0xe0 0x0>;
296 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
297 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
298 interconnect-names = "ufs-ddr", "cpu-ufs";
300 clock-names = "core_clk",
308 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
309 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
310 <&gcc GCC_UFS_PHY_AHB_CLK>,
311 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
312 <&rpmhcc RPMH_CXO_CLK>,
313 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
314 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
315 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
316 freq-table-hz = <75000000 300000000>,
319 <75000000 300000000>,
320 <75000000 300000000>,