Documentation/admin-guide/perf/thunderx2-pmu.rst

   1 =============================================================
   2 Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
   3 =============================================================
   4
   5 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
   6 PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC).
   7
   8 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
   9 Events are counted for the default channel (i.e. channel 0) and prorated
  10 to the total number of channels/tiles.
  11
  12 The DMC and L3C support up to 4 counters. Counters are independently
  13 programmable and can be started and stopped individually. Each counter
  14 can be set to a different event. Counters are 32-bit and do not support
  15 an overflow interrupt; they are read every 2 seconds.
  16
  17 PMU UNCORE (perf) driver:
  18
  19 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
  20 L3C devices.  Each PMU can be used to count up to 4 events
  21 simultaneously. The PMUs provide a description of their available events
  22 and configuration options under sysfs, see
  23 /sys/devices/uncore_<l3c_S/dmc_S/>; S is the socket id.
  24
  25 The driver does not support sampling, therefore "perf record" will not
  26 work. Per-task perf sessions are also not supported.
  27
  28 Examples::
  29
  30   # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
  31
  32   # perf stat -a -e \
  33   uncore_dmc_0/cnt_cycles/,\
  34   uncore_dmc_0/data_transfers/,\
  35   uncore_dmc_0/read_txns/,\
  36   uncore_dmc_0/write_txns/ sleep 1
  37
  38   # perf stat -a -e \
  39   uncore_l3c_0/read_request/,\
  40   uncore_l3c_0/read_hit/,\
  41   uncore_l3c_0/inv_request/,\
  42   uncore_l3c_0/inv_hit/ sleep 1