Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) 2023 Renesas Electronics Corp.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Andestech AX45MP L2 Cache Controller
   9
  10 maintainers:
  11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  12
  13 description:
  14   A level-2 cache (L2C) is used to improve the system performance by providing
  15   a large amount of cache line entries and reasonable access delays. The L2C
  16   is shared between cores, and a non-inclusive non-exclusive policy is used.
  17
  18 select:
  19   properties:
  20     compatible:
  21       contains:
  22         enum:
  23           - andestech,ax45mp-cache
  24
  25   required:
  26     - compatible
  27
  28 properties:
  29   compatible:
  30     items:
  31       - const: andestech,ax45mp-cache
  32       - const: cache
  33
  34   reg:
  35     maxItems: 1
  36
  37   interrupts:
  38     maxItems: 1
  39
  40   cache-line-size:
  41     const: 64
  42
  43   cache-level:
  44     const: 2
  45
  46   cache-sets:
  47     const: 1024
  48
  49   cache-size:
  50     enum: [131072, 262144, 524288, 1048576, 2097152]
  51
  52   cache-unified: true
  53
  54   next-level-cache: true
  55
  56 additionalProperties: false
  57
  58 required:
  59   - compatible
  60   - reg
  61   - interrupts
  62   - cache-line-size
  63   - cache-level
  64   - cache-sets
  65   - cache-size
  66   - cache-unified
  67
  68 examples:
  69   - |
  70     #include <dt-bindings/interrupt-controller/irq.h>
  71
  72     cache-controller@13400000 {
  73         compatible = "andestech,ax45mp-cache", "cache";
  74         reg = <0x13400000 0x100000>;
  75         interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
  76         cache-line-size = <64>;
  77         cache-level = <2>;
  78         cache-sets = <1024>;
  79         cache-size = <262144>;
  80         cache-unified;
  81     };