Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek DSI Controller
   8
   9 maintainers:
  10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  11   - Philipp Zabel <p.zabel@pengutronix.de>
  12   - Jitao Shi <jitao.shi@mediatek.com>
  13
  14 description: |
  15   The MediaTek DSI function block is a sink of the display subsystem and can
  16   drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
  17   channel output.
  18
  19 allOf:
  20   - $ref: /schemas/display/dsi-controller.yaml#
  21
  22 properties:
  23   compatible:
  24     oneOf:
  25       - enum:
  26           - mediatek,mt2701-dsi
  27           - mediatek,mt7623-dsi
  28           - mediatek,mt8167-dsi
  29           - mediatek,mt8173-dsi
  30           - mediatek,mt8183-dsi
  31           - mediatek,mt8186-dsi
  32           - mediatek,mt8188-dsi
  33       - items:
  34           - enum:
  35               - mediatek,mt6795-dsi
  36           - const: mediatek,mt8173-dsi
  37
  38   reg:
  39     maxItems: 1
  40
  41   interrupts:
  42     maxItems: 1
  43
  44   power-domains:
  45     maxItems: 1
  46
  47   clocks:
  48     items:
  49       - description: Engine Clock
  50       - description: Digital Clock
  51       - description: HS Clock
  52
  53   clock-names:
  54     items:
  55       - const: engine
  56       - const: digital
  57       - const: hs
  58
  59   resets:
  60     maxItems: 1
  61
  62   phys:
  63     maxItems: 1
  64
  65   phy-names:
  66     items:
  67       - const: dphy
  68
  69   port:
  70     $ref: /schemas/graph.yaml#/properties/port
  71     description:
  72       Output port node. This port should be connected to the input
  73       port of an attached DSI panel or DSI-to-eDP encoder chip.
  74
  75 required:
  76   - compatible
  77   - reg
  78   - interrupts
  79   - power-domains
  80   - clocks
  81   - clock-names
  82   - phys
  83   - phy-names
  84   - port
  85
  86 unevaluatedProperties: false
  87
  88 examples:
  89   - |
  90     #include <dt-bindings/clock/mt8183-clk.h>
  91     #include <dt-bindings/interrupt-controller/arm-gic.h>
  92     #include <dt-bindings/interrupt-controller/irq.h>
  93     #include <dt-bindings/power/mt8183-power.h>
  94     #include <dt-bindings/phy/phy.h>
  95     #include <dt-bindings/reset/mt8183-resets.h>
  96
  97     soc {
  98         #address-cells = <2>;
  99         #size-cells = <2>;
 100
 101         dsi0: dsi@14014000 {
 102             compatible = "mediatek,mt8183-dsi";
 103             reg = <0 0x14014000 0 0x1000>;
 104             interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
 105             power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 106             clocks = <&mmsys CLK_MM_DSI0_MM>,
 107                 <&mmsys CLK_MM_DSI0_IF>,
 108                 <&mipi_tx0>;
 109             clock-names = "engine", "digital", "hs";
 110             resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
 111             phys = <&mipi_tx0>;
 112             phy-names = "dphy";
 113             port {
 114                 dsi0_out: endpoint {
 115                     remote-endpoint = <&panel_in>;
 116                 };
 117             };
 118         };
 119     };
 120
 121 ...