Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra186 (and later) Display Hub
   8
   9 maintainers:
  10   - Thierry Reding <thierry.reding@gmail.com>
  11   - Jon Hunter <jonathanh@nvidia.com>
  12
  13 properties:
  14   $nodename:
  15     pattern: "^display-hub@[0-9a-f]+$"
  16
  17   compatible:
  18     enum:
  19       - nvidia,tegra186-display
  20       - nvidia,tegra194-display
  21
  22   '#address-cells':
  23     const: 1
  24
  25   '#size-cells':
  26     const: 1
  27
  28   reg:
  29     maxItems: 1
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   clocks:
  35     minItems: 2
  36     maxItems: 3
  37
  38   clock-names:
  39     minItems: 2
  40     maxItems: 3
  41
  42   resets:
  43     items:
  44       - description: display hub reset
  45       - description: window group 0 reset
  46       - description: window group 1 reset
  47       - description: window group 2 reset
  48       - description: window group 3 reset
  49       - description: window group 4 reset
  50       - description: window group 5 reset
  51
  52   reset-names:
  53     items:
  54       - const: misc
  55       - const: wgrp0
  56       - const: wgrp1
  57       - const: wgrp2
  58       - const: wgrp3
  59       - const: wgrp4
  60       - const: wgrp5
  61
  62   power-domains:
  63     maxItems: 1
  64
  65   ranges:
  66     maxItems: 1
  67
  68 patternProperties:
  69   "^display@[0-9a-f]+$":
  70     type: object
  71
  72 allOf:
  73   - if:
  74       properties:
  75         compatible:
  76           contains:
  77             const: nvidia,tegra186-display
  78     then:
  79       properties:
  80         clocks:
  81           items:
  82             - description: display core clock
  83             - description: display stream compression clock
  84             - description: display hub clock
  85
  86         clock-names:
  87           items:
  88             - const: disp
  89             - const: dsc
  90             - const: hub
  91     else:
  92       properties:
  93         clocks:
  94           items:
  95             - description: display core clock
  96             - description: display hub clock
  97
  98         clock-names:
  99           items:
 100             - const: disp
 101             - const: hub
 102
 103 additionalProperties: false
 104
 105 required:
 106   - compatible
 107   - reg
 108   - clocks
 109   - clock-names
 110   - resets
 111   - reset-names
 112   - power-domains
 113   - "#address-cells"
 114   - "#size-cells"
 115   - ranges
 116
 117 examples:
 118   - |
 119     #include <dt-bindings/clock/tegra186-clock.h>
 120     #include <dt-bindings/interrupt-controller/arm-gic.h>
 121     #include <dt-bindings/memory/tegra186-mc.h>
 122     #include <dt-bindings/power/tegra186-powergate.h>
 123     #include <dt-bindings/reset/tegra186-reset.h>
 124
 125     display-hub@15200000 {
 126         compatible = "nvidia,tegra186-display";
 127         reg = <0x15200000 0x00040000>;
 128         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
 129                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
 130                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
 131                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
 132                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
 133                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
 134                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
 135         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 136                       "wgrp3", "wgrp4", "wgrp5";
 137         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
 138                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
 139                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
 140         clock-names = "disp", "dsc", "hub";
 141
 142         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 143
 144         #address-cells = <1>;
 145         #size-cells = <1>;
 146
 147         ranges = <0x15200000 0x15200000 0x40000>;
 148
 149         display@15200000 {
 150             compatible = "nvidia,tegra186-dc";
 151             reg = <0x15200000 0x10000>;
 152             interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 153             clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
 154             clock-names = "dc";
 155             resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
 156             reset-names = "dc";
 157
 158             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 159             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
 160                             <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 161             interconnect-names = "dma-mem", "read-1";
 162             iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 163
 164             nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 165             nvidia,head = <0>;
 166         };
 167
 168         display@15210000 {
 169             compatible = "nvidia,tegra186-dc";
 170             reg = <0x15210000 0x10000>;
 171             interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 172             clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
 173             clock-names = "dc";
 174             resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
 175             reset-names = "dc";
 176
 177             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
 178             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
 179                             <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 180             interconnect-names = "dma-mem", "read-1";
 181             iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 182
 183             nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 184             nvidia,head = <1>;
 185         };
 186
 187         display@15220000 {
 188             compatible = "nvidia,tegra186-dc";
 189             reg = <0x15220000 0x10000>;
 190             interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 191             clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
 192             clock-names = "dc";
 193             resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
 194             reset-names = "dc";
 195
 196             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
 197             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
 198                             <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 199             interconnect-names = "dma-mem", "read-1";
 200             iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 201
 202             nvidia,outputs = <&sor0 &sor1>;
 203             nvidia,head = <2>;
 204         };
 205     };
 206
 207   - |
 208     #include <dt-bindings/clock/tegra194-clock.h>
 209     #include <dt-bindings/interrupt-controller/arm-gic.h>
 210     #include <dt-bindings/memory/tegra194-mc.h>
 211     #include <dt-bindings/power/tegra194-powergate.h>
 212     #include <dt-bindings/reset/tegra194-reset.h>
 213
 214     display-hub@15200000 {
 215         compatible = "nvidia,tegra194-display";
 216         reg = <0x15200000 0x00040000>;
 217         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
 218                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
 219                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
 220                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
 221                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
 222                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
 223                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
 224         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 225                       "wgrp3", "wgrp4", "wgrp5";
 226         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
 227                  <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
 228         clock-names = "disp", "hub";
 229
 230         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 231
 232         #address-cells = <1>;
 233         #size-cells = <1>;
 234
 235         ranges = <0x15200000 0x15200000 0x40000>;
 236
 237         display@15200000 {
 238             compatible = "nvidia,tegra194-dc";
 239             reg = <0x15200000 0x10000>;
 240             interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 241             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
 242             clock-names = "dc";
 243             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
 244             reset-names = "dc";
 245
 246             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 247             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
 248                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 249             interconnect-names = "dma-mem", "read-1";
 250
 251             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 252             nvidia,head = <0>;
 253         };
 254
 255         display@15210000 {
 256             compatible = "nvidia,tegra194-dc";
 257             reg = <0x15210000 0x10000>;
 258             interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 259             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
 260             clock-names = "dc";
 261             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
 262             reset-names = "dc";
 263
 264             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
 265             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
 266                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 267             interconnect-names = "dma-mem", "read-1";
 268
 269             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 270             nvidia,head = <1>;
 271         };
 272
 273         display@15220000 {
 274             compatible = "nvidia,tegra194-dc";
 275             reg = <0x15220000 0x10000>;
 276             interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 277             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
 278             clock-names = "dc";
 279             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
 280             reset-names = "dc";
 281
 282             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 283             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
 284                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 285             interconnect-names = "dma-mem", "read-1";
 286
 287             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 288             nvidia,head = <2>;
 289         };
 290
 291         display@15230000 {
 292             compatible = "nvidia,tegra194-dc";
 293             reg = <0x15230000 0x10000>;
 294             interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 295             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
 296             clock-names = "dc";
 297             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
 298             reset-names = "dc";
 299
 300             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 301             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
 302                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
 303             interconnect-names = "dma-mem", "read-1";
 304
 305             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 306             nvidia,head = <3>;
 307         };
 308     };