1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
15 that is not widely used, the definitions of which are listed here:
17 hart: A hardware execution context, which contains all the state
18 mandated by the RISC-V ISA: a PC and some registers. This
19 terminology is designed to disambiguate software's view of execution
20 contexts from any particular microarchitectural implementation
21 strategy. For example, an Intel laptop containing one socket with
22 two cores, each of which has two hyperthreads, could be described as
37 Identifies that the hart uses the RISC-V instruction set
38 and identifies the type of the hart.
42 - $ref: "/schemas/types.yaml#/definitions/string"
48 Identifies the MMU address translation mode used on this
49 hart. These values originate from the RISC-V Privileged
50 Specification document, available from
51 https://riscv.org/specifications/
55 - $ref: "/schemas/types.yaml#/definitions/string"
60 Identifies the specific RISC-V instruction set architecture
61 supported by the hart. These are documented in the RISC-V
62 User-Level ISA document, available from
63 https://riscv.org/specifications/
65 While the isa strings in ISA specification are case
66 insensitive, letters in the riscv,isa string must be all
67 lowercase to simplify parsing.
73 Specifies the clock frequency of the system timer in Hz.
74 This value is common to all harts on a single system image.
78 description: Describes the CPU's local interrupt controller
87 interrupt-controller: true
92 - interrupt-controller
97 - interrupt-controller
101 // Example 1: SiFive Freedom U540G Development Kit
103 #address-cells = <1>;
105 timebase-frequency = <1000000>;
107 clock-frequency = <0>;
108 compatible = "sifive,rocket0", "riscv";
110 i-cache-block-size = <64>;
111 i-cache-sets = <128>;
112 i-cache-size = <16384>;
114 riscv,isa = "rv64imac";
115 cpu_intc0: interrupt-controller {
116 #interrupt-cells = <1>;
117 compatible = "riscv,cpu-intc";
118 interrupt-controller;
122 clock-frequency = <0>;
123 compatible = "sifive,rocket0", "riscv";
124 d-cache-block-size = <64>;
126 d-cache-size = <32768>;
130 i-cache-block-size = <64>;
132 i-cache-size = <32768>;
135 mmu-type = "riscv,sv39";
137 riscv,isa = "rv64imafdc";
139 cpu_intc1: interrupt-controller {
140 #interrupt-cells = <1>;
141 compatible = "riscv,cpu-intc";
142 interrupt-controller;
148 // Example 2: Spike ISA Simulator with 1 Hart
150 #address-cells = <1>;
155 compatible = "riscv";
156 riscv,isa = "rv64imafdc";
157 mmu-type = "riscv,sv48";
158 interrupt-controller {
159 #interrupt-cells = <1>;
160 interrupt-controller;
161 compatible = "riscv,cpu-intc";