Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
   9
  10 maintainers:
  11  - Mukesh Savaliya <msavaliy@codeaurora.org>
  12  - Akash Asthana <akashast@codeaurora.org>
  13
  14 description:
  15  The QSPI controller allows SPI protocol communication in single, dual, or quad
  16  wire transmission modes for read/write access to slaves such as NOR flash.
  17
  18 allOf:
  19   - $ref: /spi/spi-controller.yaml#
  20
  21 properties:
  22   compatible:
  23     items:
  24       - const: qcom,sdm845-qspi
  25       - const: qcom,qspi-v1
  26
  27   reg:
  28     maxItems: 1
  29
  30   interrupts:
  31     maxItems: 1
  32
  33   clock-names:
  34     items:
  35       - const: iface
  36       - const: core
  37
  38   clocks:
  39     items:
  40       - description: AHB clock
  41       - description: QSPI core clock
  42
  43   interconnects:
  44     minItems: 1
  45     maxItems: 2
  46
  47   interconnect-names:
  48     items:
  49       - const: qspi-config
  50       - const: qspi-memory
  51
  52 required:
  53   - compatible
  54   - reg
  55   - interrupts
  56   - clock-names
  57   - clocks
  58
  59 examples:
  60   - |
  61     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  62     #include <dt-bindings/interrupt-controller/arm-gic.h>
  63
  64     soc: soc@0 {
  65         #address-cells = <2>;
  66         #size-cells = <2>;
  67
  68         qspi: spi@88df000 {
  69             compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
  70             reg = <0 0x88df000 0 0x600>;
  71             #address-cells = <1>;
  72             #size-cells = <0>;
  73             interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  74             clock-names = "iface", "core";
  75             clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
  76                          <&gcc GCC_QSPI_CORE_CLK>;
  77
  78             flash@0 {
  79                 compatible = "jedec,spi-nor";
  80                 reg = <0>;
  81                 spi-max-frequency = <25000000>;
  82                 spi-tx-bus-width = <2>;
  83                 spi-rx-bus-width = <2>;
  84             };
  85
  86         };
  87     };
  88 ...