Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: USB2 ChipIdea USB controller
   8
   9 maintainers:
  10   - Xu Yang <xu.yang_2@nxp.com>
  11   - Peng Fan <peng.fan@nxp.com>
  12
  13 properties:
  14   compatible:
  15     oneOf:
  16       - enum:
  17           - chipidea,usb2
  18           - lsi,zevio-usb
  19           - nvidia,tegra20-ehci
  20           - nvidia,tegra20-udc
  21           - nvidia,tegra30-ehci
  22           - nvidia,tegra30-udc
  23           - nvidia,tegra114-udc
  24           - nvidia,tegra124-udc
  25           - qcom,ci-hdrc
  26       - items:
  27           - enum:
  28               - nvidia,tegra114-ehci
  29               - nvidia,tegra124-ehci
  30               - nvidia,tegra210-ehci
  31           - const: nvidia,tegra30-ehci
  32       - items:
  33           - enum:
  34               - fsl,imx23-usb
  35               - fsl,imx25-usb
  36               - fsl,imx28-usb
  37               - fsl,imx35-usb
  38               - fsl,imx50-usb
  39               - fsl,imx51-usb
  40               - fsl,imx53-usb
  41               - fsl,imx6q-usb
  42               - fsl,imx6sl-usb
  43               - fsl,imx6sx-usb
  44               - fsl,imx6ul-usb
  45               - fsl,imx7d-usb
  46               - fsl,vf610-usb
  47           - const: fsl,imx27-usb
  48       - items:
  49           - enum:
  50               - fsl,imx8dxl-usb
  51               - fsl,imx8ulp-usb
  52           - const: fsl,imx7ulp-usb
  53           - const: fsl,imx6ul-usb
  54       - items:
  55           - enum:
  56               - fsl,imx8mm-usb
  57               - fsl,imx8mn-usb
  58           - const: fsl,imx7d-usb
  59           - const: fsl,imx27-usb
  60       - items:
  61           - enum:
  62               - fsl,imx6sll-usb
  63               - fsl,imx7ulp-usb
  64           - const: fsl,imx6ul-usb
  65           - const: fsl,imx27-usb
  66       - items:
  67           - const: xlnx,zynq-usb-2.20a
  68           - const: chipidea,usb2
  69
  70   reg:
  71     minItems: 1
  72     maxItems: 2
  73
  74   interrupts:
  75     minItems: 1
  76     maxItems: 2
  77
  78   clocks:
  79     minItems: 1
  80     maxItems: 3
  81
  82   clock-names:
  83     minItems: 1
  84     maxItems: 3
  85
  86   dr_mode: true
  87
  88   power-domains:
  89     maxItems: 1
  90
  91   resets:
  92     maxItems: 1
  93
  94   reset-names:
  95     maxItems: 1
  96
  97   "#reset-cells":
  98     const: 1
  99
 100   phy_type: true
 101
 102   itc-setting:
 103     description:
 104       interrupt threshold control register control, the setting should be
 105       aligned with ITC bits at register USBCMD.
 106     $ref: /schemas/types.yaml#/definitions/uint32
 107
 108   ahb-burst-config:
 109     description:
 110       it is vendor dependent, the required value should be aligned with
 111       AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is
 112       used to change AHB burst configuration, check the chipidea spec for
 113       meaning of each value. If this property is not existed, it will use
 114       the reset value.
 115     $ref: /schemas/types.yaml#/definitions/uint32
 116     minimum: 0x0
 117     maximum: 0x7
 118
 119   tx-burst-size-dword:
 120     description:
 121       it is vendor dependent, the tx burst size in dword (4 bytes), This
 122       register represents the maximum length of a the burst in 32-bit
 123       words while moving data from system memory to the USB bus, the value
 124       of this property will only take effect if property "ahb-burst-config"
 125       is set to 0, if this property is missing the reset default of the
 126       hardware implementation will be used.
 127     $ref: /schemas/types.yaml#/definitions/uint32
 128     minimum: 0x0
 129     maximum: 0x20
 130
 131   rx-burst-size-dword:
 132     description:
 133       it is vendor dependent, the rx burst size in dword (4 bytes), This
 134       register represents the maximum length of a the burst in 32-bit words
 135       while moving data from the USB bus to system memory, the value of
 136       this property will only take effect if property "ahb-burst-config"
 137       is set to 0, if this property is missing the reset default of the
 138       hardware implementation will be used.
 139     $ref: /schemas/types.yaml#/definitions/uint32
 140     minimum: 0x0
 141     maximum: 0x20
 142
 143   extcon:
 144     description:
 145       Phandles to external connector devices. First phandle should point
 146       to external connector, which provide "USB" cable events, the second
 147       should point to external connector device, which provide "USB-HOST"
 148       cable events. If one of the external connector devices is not
 149       required, empty <0> phandle should be specified.
 150     $ref: /schemas/types.yaml#/definitions/phandle-array
 151     minItems: 1
 152     items:
 153       - description: vbus extcon
 154       - description: id extcon
 155
 156   phy-clkgate-delay-us:
 157     description:
 158       The delay time (us) between putting the PHY into low power mode and
 159       gating the PHY clock.
 160
 161   non-zero-ttctrl-ttha:
 162     description:
 163       After setting this property, the value of register ttctrl.ttha
 164       will be 0x7f; if not, the value will be 0x0, this is the default
 165       value. It needs to be very carefully for setting this property, it
 166       is recommended that consult with your IC engineer before setting
 167       this value.  On the most of chipidea platforms, the "usage_tt" flag
 168       at RTL is 0, so this property only affects siTD.
 169
 170       If this property is not set, the max packet size is 1023 bytes, and
 171       if the total of packet size for previous transactions are more than
 172       256 bytes, it can't accept any transactions within this frame. The
 173       use case is single transaction, but higher frame rate.
 174
 175       If this property is set, the max packet size is 188 bytes, it can
 176       handle more transactions than above case, it can accept transactions
 177       until it considers the left room size within frame is less than 188
 178       bytes, software needs to make sure it does not send more than 90%
 179       maximum_periodic_data_per_frame. The use case is multiple
 180       transactions, but less frame rate.
 181     type: boolean
 182
 183   mux-controls:
 184     description:
 185       The mux control for toggling host/device output of this controller.
 186       It's expected that a mux state of 0 indicates device mode and a mux
 187       state of 1 indicates host mode.
 188     maxItems: 1
 189
 190   mux-control-names:
 191     const: usb_switch
 192
 193   operating-points-v2:
 194     description: A phandle to the OPP table containing the performance states.
 195     $ref: /schemas/types.yaml#/definitions/phandle
 196
 197   pinctrl-names:
 198     description:
 199       Names for optional pin modes in "default", "host", "device".
 200       In case of HSIC-mode, "idle" and "active" pin modes are mandatory.
 201       In this case, the "idle" state needs to pull down the data and
 202       strobe pin and the "active" state needs to pull up the strobe pin.
 203     oneOf:
 204       - items:
 205           - const: idle
 206           - const: active
 207       - items:
 208           - const: default
 209           - enum:
 210               - host
 211               - device
 212       - items:
 213           - const: default
 214
 215   pinctrl-0:
 216     maxItems: 1
 217
 218   pinctrl-1:
 219     maxItems: 1
 220
 221   phys:
 222     maxItems: 1
 223
 224   phy-names:
 225     const: usb-phy
 226
 227   phy-select:
 228     description:
 229       Phandler of TCSR node with two argument that indicate register
 230       offset, and phy index
 231     $ref: /schemas/types.yaml#/definitions/phandle-array
 232     items:
 233       - description: phandle to TCSR node
 234       - description: register offset
 235       - description: phy index
 236
 237   vbus-supply:
 238     description: reference to the VBUS regulator.
 239
 240   fsl,usbmisc:
 241     description:
 242       Phandler of non-core register device, with one argument that
 243       indicate usb controller index
 244     $ref: /schemas/types.yaml#/definitions/phandle-array
 245     items:
 246       - items:
 247           - description: phandle to usbmisc node
 248           - description: index of usb controller
 249
 250   fsl,anatop:
 251     description: phandle for the anatop node.
 252     $ref: /schemas/types.yaml#/definitions/phandle
 253
 254   disable-over-current:
 255     type: boolean
 256     description: disable over current detect
 257
 258   over-current-active-low:
 259     type: boolean
 260     description: over current signal polarity is active low
 261
 262   over-current-active-high:
 263     type: boolean
 264     description:
 265       Over current signal polarity is active high. It's recommended to
 266       specify the over current polarity.
 267
 268   power-active-high:
 269     type: boolean
 270     description: power signal polarity is active high
 271
 272   external-vbus-divider:
 273     type: boolean
 274     description: enables off-chip resistor divider for Vbus
 275
 276   samsung,picophy-pre-emp-curr-control:
 277     description:
 278       HS Transmitter Pre-Emphasis Current Control. This signal controls
 279       the amount of current sourced to the USB_OTG*_DP and USB_OTG*_DN
 280       pins after a J-to-K or K-to-J transition. The range is from 0x0 to
 281       0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0
 282       bits of USBNC_n_PHY_CFG1.
 283     $ref: /schemas/types.yaml#/definitions/uint32
 284     minimum: 0x0
 285     maximum: 0x3
 286
 287   samsung,picophy-dc-vol-level-adjust:
 288     description:
 289       HS DC Voltage Level Adjustment. Adjust the high-speed transmitter DC
 290       level voltage. The range is from 0x0 to 0xf, the default value is
 291       0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
 292     $ref: /schemas/types.yaml#/definitions/uint32
 293     minimum: 0x0
 294     maximum: 0xf
 295
 296   fsl,picophy-rise-fall-time-adjust:
 297     description:
 298       HS Transmitter Rise/Fall Time Adjustment. Adjust the rise/fall times
 299       of the high-speed transmitter waveform. It has no unit. The rise/fall
 300       time will be increased or decreased by a certain percentage relative
 301       to design default time. (0:-10%; 1:design default; 2:+15%; 3:+20%)
 302       Details can refer to TXRISETUNE0 bit of USBNC_n_PHY_CFG1.
 303     $ref: /schemas/types.yaml#/definitions/uint32
 304     minimum: 0
 305     maximum: 3
 306     default: 1
 307
 308   usb-phy:
 309     description: phandle for the PHY device. Use "phys" instead.
 310     $ref: /schemas/types.yaml#/definitions/phandle
 311     deprecated: true
 312
 313   fsl,usbphy:
 314     description: phandle of usb phy that connects to the port. Use "phys" instead.
 315     $ref: /schemas/types.yaml#/definitions/phandle
 316     deprecated: true
 317
 318   nvidia,phy:
 319     description: phandle of usb phy that connects to the port. Use "phys" instead.
 320     $ref: /schemas/types.yaml#/definitions/phandle
 321     deprecated: true
 322
 323   nvidia,needs-double-reset:
 324     description: Indicates double reset or not.
 325     type: boolean
 326     deprecated: true
 327
 328   port:
 329     description:
 330       Any connector to the data bus of this controller should be modelled
 331       using the OF graph bindings specified, if the "usb-role-switch"
 332       property is used.
 333     $ref: /schemas/graph.yaml#/properties/port
 334
 335   reset-gpios:
 336     maxItems: 1
 337
 338   ulpi:
 339     type: object
 340     additionalProperties: false
 341     patternProperties:
 342       "^phy(-[0-9])?$":
 343         description: The phy child node for Qcom chips.
 344         type: object
 345         $ref: /schemas/phy/qcom,usb-hs-phy.yaml
 346
 347 dependencies:
 348   port: [ usb-role-switch ]
 349   mux-controls: [ mux-control-names ]
 350
 351 required:
 352   - compatible
 353   - reg
 354   - interrupts
 355
 356 allOf:
 357   - $ref: usb-hcd.yaml#
 358   - $ref: usb-drd.yaml#
 359   - if:
 360       properties:
 361         phy_type:
 362           const: hsic
 363       required:
 364         - phy_type
 365     then:
 366       properties:
 367         pinctrl-names:
 368           items:
 369             - const: idle
 370             - const: active
 371     else:
 372       properties:
 373         pinctrl-names:
 374           minItems: 1
 375           maxItems: 2
 376           oneOf:
 377             - items:
 378                 - const: default
 379                 - enum:
 380                     - host
 381                     - device
 382             - items:
 383                 - const: default
 384   - if:
 385       properties:
 386         compatible:
 387           contains:
 388             enum:
 389               - chipidea,usb2
 390               - lsi,zevio-usb
 391               - nvidia,tegra20-udc
 392               - nvidia,tegra30-udc
 393               - nvidia,tegra114-udc
 394               - nvidia,tegra124-udc
 395               - qcom,ci-hdrc
 396               - xlnx,zynq-usb-2.20a
 397     then:
 398       properties:
 399         fsl,usbmisc: false
 400         disable-over-current: false
 401         over-current-active-low: false
 402         over-current-active-high: false
 403         power-active-high: false
 404         external-vbus-divider: false
 405         samsung,picophy-pre-emp-curr-control: false
 406         samsung,picophy-dc-vol-level-adjust: false
 407
 408 unevaluatedProperties: false
 409
 410 examples:
 411   - |
 412     #include <dt-bindings/interrupt-controller/arm-gic.h>
 413     #include <dt-bindings/clock/berlin2.h>
 414
 415     usb@f7ed0000 {
 416         compatible = "chipidea,usb2";
 417         reg = <0xf7ed0000 0x10000>;
 418         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 419         clocks = <&chip CLKID_USB0>;
 420         phys = <&usb_phy0>;
 421         phy-names = "usb-phy";
 422         vbus-supply = <&reg_usb0_vbus>;
 423         itc-setting = <0x4>; /* 4 micro-frames */
 424          /* Incremental burst of unspecified length */
 425         ahb-burst-config = <0x0>;
 426         tx-burst-size-dword = <0x10>; /* 64 bytes */
 427         rx-burst-size-dword = <0x10>;
 428         extcon = <0>, <&usb_id>;
 429         phy-clkgate-delay-us = <400>;
 430         mux-controls = <&usb_switch>;
 431         mux-control-names = "usb_switch";
 432     };
 433
 434   # Example for HSIC:
 435   - |
 436     #include <dt-bindings/interrupt-controller/arm-gic.h>
 437     #include <dt-bindings/clock/imx6qdl-clock.h>
 438
 439     usb@2184400 {
 440         compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 441         reg = <0x02184400 0x200>;
 442         interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 443         clocks = <&clks IMX6QDL_CLK_USBOH3>;
 444         fsl,usbphy = <&usbphynop1>;
 445         fsl,usbmisc = <&usbmisc 2>;
 446         phy_type = "hsic";
 447         dr_mode = "host";
 448         ahb-burst-config = <0x0>;
 449         tx-burst-size-dword = <0x10>;
 450         rx-burst-size-dword = <0x10>;
 451         pinctrl-names = "idle", "active";
 452         pinctrl-0 = <&pinctrl_usbh2_idle>;
 453         pinctrl-1 = <&pinctrl_usbh2_active>;
 454         #address-cells = <1>;
 455         #size-cells = <0>;
 456
 457         ethernet@1 {
 458             compatible = "usb424,9730";
 459             reg = <1>;
 460         };
 461     };
 462
 463 ...