5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
56 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
60 bool "ARM architecture"
61 select ARCH_SUPPORTS_LTO
62 select CREATE_ARCH_SYMLINK
63 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select NEEDS_MANUAL_RELOC
71 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
73 select SYS_CACHE_SHIFT_4
74 select SUPPORT_OF_CONTROL
77 bool "MicroBlaze architecture"
78 select SUPPORT_OF_CONTROL
80 imply SPL_REGMAP if SPL
81 imply SPL_TIMER if SPL
86 bool "MIPS architecture"
87 select HAVE_ARCH_IOREMAP
88 select HAVE_PRIVATE_LIBGCC
89 select SUPPORT_OF_CONTROL
90 select SPL_SEPARATE_BSS if SPL
93 bool "Nios II architecture"
98 select SUPPORT_OF_CONTROL
102 bool "PowerPC architecture"
103 select HAVE_PRIVATE_LIBGCC
104 select SUPPORT_OF_CONTROL
105 select SYS_BOOT_GET_CMDLINE
106 select SYS_BOOT_GET_KBD
109 bool "RISC-V architecture"
110 select CREATE_ARCH_SYMLINK
111 select SUPPORT_OF_CONTROL
114 imply SPL_SEPARATE_BSS if SPL
127 imply SPL_LIBCOMMON_SUPPORT
128 imply SPL_LIBGENERIC_SUPPORT
134 select ARCH_SUPPORTS_LTO
135 select BOARD_LATE_INIT
139 select DM_FUZZING_ENGINE
147 select GZIP_COMPRESSED
150 select OF_BOARD_SETUP
153 select SUPPORT_OF_CONTROL
154 select SYSRESET_CMD_POWEROFF
155 select SYS_CACHE_SHIFT_4
157 select SUPPORT_EXTENSION_SCAN
174 imply FUZZING_ENGINE_SANDBOX
181 imply PARTITION_TYPE_GUID
184 imply UDP_FUNCTION_FASTBOOT
197 imply ACPI_PMC_SANDBOX
207 imply GENERATE_ACPI_TABLE
211 bool "SuperH architecture"
212 select HAVE_PRIVATE_LIBGCC
213 select SUPPORT_OF_CONTROL
216 bool "x86 architecture"
219 select CREATE_ARCH_SYMLINK
221 select HAVE_ARCH_IOMAP
222 select HAVE_PRIVATE_LIBGCC
226 select SUPPORT_OF_CONTROL
227 select SYS_CACHE_SHIFT_6
229 select USE_PRIVATE_LIBGCC
232 imply HAS_ROM if X86_RESET_VECTOR
235 imply CMD_FPGA_LOADMK
258 imply USB_ETHER_SMSC95XX
263 imply ACPIGEN if !QEMU && !EFI_APP
264 imply SYSINFO if GENERATE_SMBIOS_TABLE
265 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
268 # Thing to enable for when SPL/TPL are enabled: SPL
271 imply SPL_DRIVERS_MISC
274 imply SPL_LIBCOMMON_SUPPORT
275 imply SPL_LIBGENERIC_SUPPORT
277 imply SPL_SPI_FLASH_SUPPORT
285 imply TPL_DRIVERS_MISC
288 imply TPL_LIBCOMMON_SUPPORT
289 imply TPL_LIBGENERIC_SUPPORT
297 bool "Xtensa architecture"
298 select CREATE_ARCH_SYMLINK
299 select SUPPORT_OF_CONTROL
306 This option should contain the architecture name to build the
307 appropriate arch/<CONFIG_SYS_ARCH> directory.
308 All the architectures should specify this option correctly.
313 This option should contain the CPU name to build the correct
314 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
316 This is optional. For those targets without the CPU directory,
317 leave this option empty.
322 This option should contain the SoC name to build the directory
323 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
325 This is optional. For those targets without the SoC directory,
326 leave this option empty.
331 This option should contain the vendor name of the target board.
333 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
334 directory is compiled.
335 If CONFIG_SYS_BOARD is also set, the sources under
336 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
338 This is optional. For those targets without the vendor directory,
339 leave this option empty.
344 This option should contain the name of the target board.
345 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
346 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
347 whether CONFIG_SYS_VENDOR is set or not.
349 This is optional. For those targets without the board directory,
350 leave this option empty.
352 config SYS_CONFIG_NAME
355 This option should contain the base name of board header file.
356 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
357 should be included from include/config.h.
359 config SYS_DISABLE_DCACHE_OPS
362 This option disables dcache flush and dcache invalidation
363 operations. For example, on coherent systems where cache
364 operatios are not required, enable this option to avoid them.
365 Note that, its up to the individual architectures to implement
369 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
370 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
371 default 0xFF000000 if MPC8xx
372 default 0xF0000000 if ARCH_MPC8313
373 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
374 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
375 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
376 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
378 default SYS_CCSRBAR_DEFAULT
380 Address for the Internal Memory-Mapped Registers (IMMR) window used
381 to configure the features of many Freescale / NXP SoCs.
383 config SKIP_LOWLEVEL_INIT
384 bool "Skip the calls to certain low level initialization functions"
385 depends on ARM || MIPS || RISCV
387 If enabled, then certain low level initializations (like setting up
388 the memory controller) are omitted and/or U-Boot does not relocate
390 Normally this variable MUST NOT be defined. The only exception is
391 when U-Boot is loaded (to RAM) by some other boot loader or by a
392 debugger which performs these initializations itself.
394 config SPL_SKIP_LOWLEVEL_INIT
395 bool "Skip the calls to certain low level initialization functions"
396 depends on SPL && (ARM || MIPS || RISCV)
398 If enabled, then certain low level initializations (like setting up
399 the memory controller) are omitted and/or U-Boot does not relocate
401 Normally this variable MUST NOT be defined. The only exception is
402 when U-Boot is loaded (to RAM) by some other boot loader or by a
403 debugger which performs these initializations itself.
405 config TPL_SKIP_LOWLEVEL_INIT
406 bool "Skip the calls to certain low level initialization functions"
407 depends on SPL && ARM
409 If enabled, then certain low level initializations (like setting up
410 the memory controller) are omitted and/or U-Boot does not relocate
412 Normally this variable MUST NOT be defined. The only exception is
413 when U-Boot is loaded (to RAM) by some other boot loader or by a
414 debugger which performs these initializations itself.
416 config SKIP_LOWLEVEL_INIT_ONLY
417 bool "Skip the call to lowlevel_init during early boot ONLY"
420 This allows just the call to lowlevel_init() to be skipped. The
421 normal CP15 init (such as enabling the instruction cache) is still
424 config SPL_SKIP_LOWLEVEL_INIT_ONLY
425 bool "Skip the call to lowlevel_init during early boot ONLY"
426 depends on SPL && ARM
428 This allows just the call to lowlevel_init() to be skipped. The
429 normal CP15 init (such as enabling the instruction cache) is still
432 config TPL_SKIP_LOWLEVEL_INIT_ONLY
433 bool "Skip the call to lowlevel_init during early boot ONLY"
434 depends on TPL && ARM
436 This allows just the call to lowlevel_init() to be skipped. The
437 normal CP15 init (such as enabling the instruction cache) is still
440 config SYS_HAS_NONCACHED_MEMORY
441 bool "Enable reserving a non-cached memory area for drivers"
442 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
444 This is useful for drivers that would otherwise require a lot of
445 explicit cache maintenance. For some drivers it's also impossible to
446 properly maintain the cache. For example if the regions that need to
447 be flushed are not a multiple of the cache-line size, *and* padding
448 cannot be allocated between the regions to align them (i.e. if the
449 HW requires a contiguous array of regions, and the size of each
450 region is not cache-aligned), then a flush of one region may result
451 in overwriting data that hardware has written to another region in
452 the same cache-line. This can happen for example in network drivers
453 where descriptors for buffers are typically smaller than the CPU
454 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
456 config SYS_NONCACHED_MEMORY
457 hex "Size in bytes of the non-cached memory area"
458 depends on SYS_HAS_NONCACHED_MEMORY
461 Size of non-cached memory area. This area of memory will be typically
462 located right below the malloc() area and mapped uncached in the MMU.
464 source "arch/arc/Kconfig"
465 source "arch/arm/Kconfig"
466 source "arch/m68k/Kconfig"
467 source "arch/microblaze/Kconfig"
468 source "arch/mips/Kconfig"
469 source "arch/nios2/Kconfig"
470 source "arch/powerpc/Kconfig"
471 source "arch/sandbox/Kconfig"
472 source "arch/sh/Kconfig"
473 source "arch/x86/Kconfig"
474 source "arch/xtensa/Kconfig"
475 source "arch/riscv/Kconfig"
477 if ARM || M68K || PPC
479 source "arch/Kconfig.nxp"
483 source "board/keymile/Kconfig"
485 if MIPS || MICROBLAZE
488 prompt "Endianness selection"
490 Some MIPS boards can be configured for either little or big endian
491 byte order. These modes require different U-Boot images. In general there
492 is one preferred byteorder for a particular system but some systems are
493 just as commonly used in the one or the other endianness.
495 config SYS_BIG_ENDIAN
497 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
499 config SYS_LITTLE_ENDIAN
501 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE