arch/Kconfig

   1 config ARCH_MAP_SYSMEM
   2         depends on SANDBOX
   3         def_bool y
   4
   5 config CREATE_ARCH_SYMLINK
   6         bool
   7
   8 config HAVE_ARCH_IOREMAP
   9         bool
  10
  11 config SYS_CACHE_SHIFT_4
  12         bool
  13
  14 config SYS_CACHE_SHIFT_5
  15         bool
  16
  17 config SYS_CACHE_SHIFT_6
  18         bool
  19
  20 config SYS_CACHE_SHIFT_7
  21         bool
  22
  23 config SYS_CACHELINE_SIZE
  24         int
  25         default 128 if SYS_CACHE_SHIFT_7
  26         default 64 if SYS_CACHE_SHIFT_6
  27         default 32 if SYS_CACHE_SHIFT_5
  28         default 16 if SYS_CACHE_SHIFT_4
  29         # Fall-back for MIPS
  30         default 32 if MIPS
  31
  32 config LINKER_LIST_ALIGN
  33         int
  34         default 32 if SANDBOX
  35         default 8 if ARM64 || X86
  36         default 4
  37         help
  38           Force the each linker list to be aligned to this boundary. This
  39           is required if ll_entry_get() is used, since otherwise the linker
  40           may add padding into the table, thus breaking it.
  41           See linker_lists.rst for full details.
  42
  43 choice
  44         prompt "Architecture select"
  45         default SANDBOX
  46
  47 config ARC
  48         bool "ARC architecture"
  49         select ARC_TIMER
  50         select CLK
  51         select DM
  52         select HAVE_PRIVATE_LIBGCC
  53         select SUPPORT_OF_CONTROL
  54         select SYS_CACHE_SHIFT_7
  55         select TIMER
  56         select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
  57         select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
  58
  59 config ARM
  60         bool "ARM architecture"
  61         select ARCH_SUPPORTS_LTO
  62         select CREATE_ARCH_SYMLINK
  63         select HAVE_PRIVATE_LIBGCC if !ARM64
  64         select SUPPORT_ACPI
  65         select SUPPORT_OF_CONTROL
  66
  67 config M68K
  68         bool "M68000 architecture"
  69         select HAVE_PRIVATE_LIBGCC
  70         select NEEDS_MANUAL_RELOC
  71         select SYS_BOOT_GET_CMDLINE
  72         select SYS_BOOT_GET_KBD
  73         select SYS_CACHE_SHIFT_4
  74         select SUPPORT_OF_CONTROL
  75
  76 config MICROBLAZE
  77         bool "MicroBlaze architecture"
  78         select SUPPORT_OF_CONTROL
  79         imply CMD_TIMER
  80         imply SPL_REGMAP if SPL
  81         imply SPL_TIMER if SPL
  82         imply TIMER
  83         imply XILINX_TIMER
  84
  85 config MIPS
  86         bool "MIPS architecture"
  87         select HAVE_ARCH_IOREMAP
  88         select HAVE_PRIVATE_LIBGCC
  89         select SUPPORT_OF_CONTROL
  90         select SPL_SEPARATE_BSS if SPL
  91
  92 config NIOS2
  93         bool "Nios II architecture"
  94         select CPU
  95         select DM
  96         select DM_EVENT
  97         select OF_CONTROL
  98         select SUPPORT_OF_CONTROL
  99         imply CMD_DM
 100
 101 config PPC
 102         bool "PowerPC architecture"
 103         select HAVE_PRIVATE_LIBGCC
 104         select SUPPORT_OF_CONTROL
 105         select SYS_BOOT_GET_CMDLINE
 106         select SYS_BOOT_GET_KBD
 107
 108 config RISCV
 109         bool "RISC-V architecture"
 110         select CREATE_ARCH_SYMLINK
 111         select SUPPORT_OF_CONTROL
 112         select OF_CONTROL
 113         select DM
 114         select DM_EVENT
 115         imply SPL_SEPARATE_BSS if SPL
 116         imply DM_SERIAL
 117         imply DM_MMC
 118         imply DM_SPI
 119         imply DM_SPI_FLASH
 120         imply BLK
 121         imply CLK
 122         imply MTD
 123         imply TIMER
 124         imply CMD_DM
 125         imply SPL_DM
 126         imply SPL_OF_CONTROL
 127         imply SPL_LIBCOMMON_SUPPORT
 128         imply SPL_LIBGENERIC_SUPPORT
 129         imply SPL_SERIAL
 130         imply SPL_TIMER
 131
 132 config SANDBOX
 133         bool "Sandbox"
 134         select ARCH_SUPPORTS_LTO
 135         select BOARD_LATE_INIT
 136         select BZIP2
 137         select CMD_POWEROFF
 138         select DM
 139         select DM_EVENT
 140         select DM_FUZZING_ENGINE
 141         select DM_GPIO
 142         select DM_I2C
 143         select DM_KEYBOARD
 144         select DM_MMC
 145         select DM_SERIAL
 146         select DM_SPI
 147         select DM_SPI_FLASH
 148         select GZIP_COMPRESSED
 149         select IO_TRACE
 150         select LZO
 151         select OF_BOARD_SETUP
 152         select PCI_ENDPOINT
 153         select SPI
 154         select SUPPORT_OF_CONTROL
 155         select SYSRESET_CMD_POWEROFF
 156         select SYS_CACHE_SHIFT_4
 157         select IRQ
 158         select SUPPORT_EXTENSION_SCAN
 159         select SUPPORT_ACPI
 160         imply BITREVERSE
 161         select BLOBLIST
 162         imply LTO
 163         imply CMD_DM
 164         imply CMD_EXCEPTION
 165         imply CMD_GETTIME
 166         imply CMD_HASH
 167         imply CMD_IO
 168         imply CMD_IOTRACE
 169         imply CMD_LZMADEC
 170         imply CMD_SF
 171         imply CMD_SF_TEST
 172         imply CRC32_VERIFY
 173         imply FAT_WRITE
 174         imply FIRMWARE
 175         imply FUZZING_ENGINE_SANDBOX
 176         imply HASH_VERIFY
 177         imply LZMA
 178         imply TEE
 179         imply AVB_VERIFY
 180         imply LIBAVB
 181         imply CMD_AVB
 182         imply PARTITION_TYPE_GUID
 183         imply SCP03
 184         imply CMD_SCP03
 185         imply UDP_FUNCTION_FASTBOOT
 186         imply VIRTIO_MMIO
 187         imply VIRTIO_PCI
 188         imply VIRTIO_SANDBOX
 189         imply VIRTIO_BLK
 190         imply VIRTIO_NET
 191         imply DM_SOUND
 192         imply PCI_SANDBOX_EP
 193         imply PCH
 194         imply PHYLIB
 195         imply DM_MDIO
 196         imply DM_MDIO_MUX
 197         imply ACPI_PMC
 198         imply ACPI_PMC_SANDBOX
 199         imply CMD_PMC
 200         imply CMD_CLONE
 201         imply SILENT_CONSOLE
 202         imply BOOTARGS_SUBST
 203         imply PHY_FIXED
 204         imply DM_DSA
 205         imply CMD_EXTENSION
 206         imply KEYBOARD
 207         imply PHYSMEM
 208         imply GENERATE_ACPI_TABLE
 209         imply BINMAN
 210
 211 config SH
 212         bool "SuperH architecture"
 213         select HAVE_PRIVATE_LIBGCC
 214         select SUPPORT_OF_CONTROL
 215
 216 config X86
 217         bool "x86 architecture"
 218         select SUPPORT_SPL
 219         select SUPPORT_TPL
 220         select CREATE_ARCH_SYMLINK
 221         select DM
 222         select HAVE_ARCH_IOMAP
 223         select HAVE_PRIVATE_LIBGCC
 224         select OF_CONTROL
 225         select PCI
 226         select SUPPORT_ACPI
 227         select SUPPORT_OF_CONTROL
 228         select SYS_CACHE_SHIFT_6
 229         select TIMER
 230         select USE_PRIVATE_LIBGCC
 231         select X86_TSC_TIMER
 232         select IRQ
 233         imply HAS_ROM if X86_RESET_VECTOR
 234         imply BLK
 235         imply CMD_DM
 236         imply CMD_FPGA_LOADMK
 237         imply CMD_GETTIME
 238         imply CMD_IO
 239         imply CMD_IRQ
 240         imply CMD_PCI
 241         imply CMD_SF
 242         imply CMD_SF_TEST
 243         imply CMD_ZBOOT
 244         imply DM_GPIO
 245         imply DM_KEYBOARD
 246         imply DM_MMC
 247         imply DM_RTC
 248         imply DM_SCSI
 249         imply DM_SERIAL
 250         imply DM_SPI
 251         imply DM_SPI_FLASH
 252         imply DM_USB
 253         imply VIDEO
 254         imply SYSRESET
 255         imply SPL_SYSRESET
 256         imply SYSRESET_X86
 257         imply USB_ETHER_ASIX
 258         imply USB_ETHER_SMSC95XX
 259         imply USB_HOST_ETHER
 260         imply PCH
 261         imply PHYSMEM
 262         imply RTC_MC146818
 263         imply ACPIGEN if !QEMU && !EFI_APP
 264         imply SYSINFO if GENERATE_SMBIOS_TABLE
 265         imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
 266         imply TIMESTAMP
 267
 268         # Thing to enable for when SPL/TPL are enabled: SPL
 269         imply SPL_DM
 270         imply SPL_OF_LIBFDT
 271         imply SPL_DRIVERS_MISC
 272         imply SPL_GPIO
 273         imply SPL_PINCTRL
 274         imply SPL_LIBCOMMON_SUPPORT
 275         imply SPL_LIBGENERIC_SUPPORT
 276         imply SPL_SERIAL
 277         imply SPL_SPI_FLASH_SUPPORT
 278         imply SPL_SPI
 279         imply SPL_OF_CONTROL
 280         imply SPL_TIMER
 281         imply SPL_REGMAP
 282         imply SPL_SYSCON
 283         # TPL
 284         imply TPL_DM
 285         imply TPL_DRIVERS_MISC
 286         imply TPL_GPIO
 287         imply TPL_PINCTRL
 288         imply TPL_LIBCOMMON_SUPPORT
 289         imply TPL_LIBGENERIC_SUPPORT
 290         imply TPL_SERIAL
 291         imply TPL_OF_CONTROL
 292         imply TPL_TIMER
 293         imply TPL_REGMAP
 294         imply TPL_SYSCON
 295
 296 config XTENSA
 297         bool "Xtensa architecture"
 298         select CREATE_ARCH_SYMLINK
 299         select SUPPORT_OF_CONTROL
 300
 301 endchoice
 302
 303 config SYS_ARCH
 304         string
 305         help
 306           This option should contain the architecture name to build the
 307           appropriate arch/<CONFIG_SYS_ARCH> directory.
 308           All the architectures should specify this option correctly.
 309
 310 config SYS_CPU
 311         string
 312         help
 313           This option should contain the CPU name to build the correct
 314           arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
 315
 316           This is optional.  For those targets without the CPU directory,
 317           leave this option empty.
 318
 319 config SYS_SOC
 320         string
 321         help
 322           This option should contain the SoC name to build the directory
 323           arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
 324
 325           This is optional.  For those targets without the SoC directory,
 326           leave this option empty.
 327
 328 config SYS_VENDOR
 329         string
 330         help
 331           This option should contain the vendor name of the target board.
 332           If it is set and
 333           board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
 334           directory is compiled.
 335           If CONFIG_SYS_BOARD is also set, the sources under
 336           board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
 337
 338           This is optional.  For those targets without the vendor directory,
 339           leave this option empty.
 340
 341 config SYS_BOARD
 342         string
 343         help
 344           This option should contain the name of the target board.
 345           If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
 346           or board/<CONFIG_SYS_BOARD> directory is compiled depending on
 347           whether CONFIG_SYS_VENDOR is set or not.
 348
 349           This is optional.  For those targets without the board directory,
 350           leave this option empty.
 351
 352 config SYS_CONFIG_NAME
 353         string
 354         help
 355           This option should contain the base name of board header file.
 356           The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
 357           should be included from include/config.h.
 358
 359 config SYS_DISABLE_DCACHE_OPS
 360         bool
 361         help
 362          This option disables dcache flush and dcache invalidation
 363          operations. For example, on coherent systems where cache
 364          operatios are not required, enable this option to avoid them.
 365          Note that, its up to the individual architectures to implement
 366          this functionality.
 367
 368 config SYS_IMMR
 369         hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
 370         depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
 371         default 0xFF000000 if MPC8xx
 372         default 0xF0000000 if ARCH_MPC8313
 373         default 0xE0000000 if MPC83xx && !ARCH_MPC8313
 374         default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
 375         default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
 376                               ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
 377                               ARCH_P2020
 378         default SYS_CCSRBAR_DEFAULT
 379         help
 380           Address for the Internal Memory-Mapped Registers (IMMR) window used
 381           to configure the features of many Freescale / NXP SoCs.
 382
 383 config MONITOR_IS_IN_RAM
 384         bool "U-Boot is loaded in to RAM by a pre-loader"
 385         depends on M68K || NIOS2
 386
 387 menu "Skipping low level initialization functions"
 388         depends on ARM || MIPS || RISCV
 389
 390 config SKIP_LOWLEVEL_INIT
 391         bool "Skip calls to certain low level initialization functions"
 392         help
 393           If enabled, then certain low level initializations (like setting up
 394           the memory controller) are omitted and/or U-Boot does not relocate
 395           itself into RAM.
 396           Normally this variable MUST NOT be defined. The only exception is
 397           when U-Boot is loaded (to RAM) by some other boot loader or by a
 398           debugger which performs these initializations itself.
 399
 400 config SPL_SKIP_LOWLEVEL_INIT
 401         bool "Skip calls to certain low level initialization functions in SPL"
 402         depends on SPL
 403         help
 404           If enabled, then certain low level initializations (like setting up
 405           the memory controller) are omitted and/or U-Boot does not relocate
 406           itself into RAM.
 407           Normally this variable MUST NOT be defined. The only exception is
 408           when U-Boot is loaded (to RAM) by some other boot loader or by a
 409           debugger which performs these initializations itself.
 410
 411 config TPL_SKIP_LOWLEVEL_INIT
 412         bool "Skip calls to certain low level initialization functions in TPL"
 413         depends on SPL && ARM
 414         help
 415           If enabled, then certain low level initializations (like setting up
 416           the memory controller) are omitted and/or U-Boot does not relocate
 417           itself into RAM.
 418           Normally this variable MUST NOT be defined. The only exception is
 419           when U-Boot is loaded (to RAM) by some other boot loader or by a
 420           debugger which performs these initializations itself.
 421
 422 config SKIP_LOWLEVEL_INIT_ONLY
 423         bool "Skip call to lowlevel_init during early boot ONLY"
 424         depends on ARM
 425         help
 426           This allows just the call to lowlevel_init() to be skipped. The
 427           normal CP15 init (such as enabling the instruction cache) is still
 428           performed.
 429
 430 config SPL_SKIP_LOWLEVEL_INIT_ONLY
 431         bool "Skip call to lowlevel_init during early SPL boot ONLY"
 432         depends on SPL && ARM
 433         help
 434           This allows just the call to lowlevel_init() to be skipped. The
 435           normal CP15 init (such as enabling the instruction cache) is still
 436           performed.
 437
 438 config TPL_SKIP_LOWLEVEL_INIT_ONLY
 439         bool "Skip call to lowlevel_init during early TPL boot ONLY"
 440         depends on TPL && ARM
 441         help
 442           This allows just the call to lowlevel_init() to be skipped. The
 443           normal CP15 init (such as enabling the instruction cache) is still
 444           performed.
 445
 446 endmenu
 447
 448 config SYS_HAS_NONCACHED_MEMORY
 449         bool "Enable reserving a non-cached memory area for drivers"
 450         depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
 451         help
 452           This is useful for drivers that would otherwise require a lot of
 453           explicit cache maintenance. For some drivers it's also impossible to
 454           properly maintain the cache. For example if the regions that need to
 455           be flushed are not a multiple of the cache-line size, *and* padding
 456           cannot be allocated between the regions to align them (i.e.  if the
 457           HW requires a contiguous array of regions, and the size of each
 458           region is not cache-aligned), then a flush of one region may result
 459           in overwriting data that hardware has written to another region in
 460           the same cache-line. This can happen for example in network drivers
 461           where descriptors for buffers are typically smaller than the CPU
 462           cache-line (e.g.  16 bytes vs. 32 or 64 bytes).
 463
 464 config SYS_NONCACHED_MEMORY
 465         hex "Size in bytes of the non-cached memory area"
 466         depends on SYS_HAS_NONCACHED_MEMORY
 467         default 0x100000
 468         help
 469           Size of non-cached memory area. This area of memory will be typically
 470           located right below the malloc() area and mapped uncached in the MMU.
 471
 472 source "arch/arc/Kconfig"
 473 source "arch/arm/Kconfig"
 474 source "arch/m68k/Kconfig"
 475 source "arch/microblaze/Kconfig"
 476 source "arch/mips/Kconfig"
 477 source "arch/nios2/Kconfig"
 478 source "arch/powerpc/Kconfig"
 479 source "arch/sandbox/Kconfig"
 480 source "arch/sh/Kconfig"
 481 source "arch/x86/Kconfig"
 482 source "arch/xtensa/Kconfig"
 483 source "arch/riscv/Kconfig"
 484
 485 if ARM || M68K || PPC
 486
 487 source "arch/Kconfig.nxp"
 488
 489 endif
 490
 491 source "board/keymile/Kconfig"
 492
 493 if MIPS || MICROBLAZE
 494
 495 choice
 496         prompt "Endianness selection"
 497         help
 498           Some MIPS boards can be configured for either little or big endian
 499           byte order. These modes require different U-Boot images. In general there
 500           is one preferred byteorder for a particular system but some systems are
 501           just as commonly used in the one or the other endianness.
 502
 503 config SYS_BIG_ENDIAN
 504         bool "Big endian"
 505         depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
 506
 507 config SYS_LITTLE_ENDIAN
 508         bool "Little endian"
 509         depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
 510
 511 endchoice
 512
 513 endif