arch/Kconfig

   1 config ARCH_MAP_SYSMEM
   2         depends on SANDBOX
   3         def_bool y
   4
   5 config CREATE_ARCH_SYMLINK
   6         bool
   7
   8 config HAVE_ARCH_IOREMAP
   9         bool
  10
  11 config SYS_CACHE_SHIFT_4
  12         bool
  13
  14 config SYS_CACHE_SHIFT_5
  15         bool
  16
  17 config SYS_CACHE_SHIFT_6
  18         bool
  19
  20 config SYS_CACHE_SHIFT_7
  21         bool
  22
  23 config SYS_CACHELINE_SIZE
  24         int
  25         default 128 if SYS_CACHE_SHIFT_7
  26         default 64 if SYS_CACHE_SHIFT_6
  27         default 32 if SYS_CACHE_SHIFT_5
  28         default 16 if SYS_CACHE_SHIFT_4
  29         # Fall-back for MIPS
  30         default 32 if MIPS
  31
  32 config LINKER_LIST_ALIGN
  33         int
  34         default 32 if SANDBOX
  35         default 8 if ARM64 || X86
  36         default 4
  37         help
  38           Force the each linker list to be aligned to this boundary. This
  39           is required if ll_entry_get() is used, since otherwise the linker
  40           may add padding into the table, thus breaking it.
  41           See linker_lists.rst for full details.
  42
  43 choice
  44         prompt "Architecture select"
  45         default SANDBOX
  46
  47 config ARC
  48         bool "ARC architecture"
  49         select ARC_TIMER
  50         select CLK
  51         select DM
  52         select HAVE_PRIVATE_LIBGCC
  53         select SUPPORT_OF_CONTROL
  54         select SYS_CACHE_SHIFT_7
  55         select TIMER
  56         select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
  57         select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
  58
  59 config ARM
  60         bool "ARM architecture"
  61         select ARCH_SUPPORTS_LTO
  62         select CREATE_ARCH_SYMLINK
  63         select HAVE_PRIVATE_LIBGCC if !ARM64
  64         select SUPPORT_ACPI
  65         select SUPPORT_OF_CONTROL
  66
  67 config M68K
  68         bool "M68000 architecture"
  69         select HAVE_PRIVATE_LIBGCC
  70         select NEEDS_MANUAL_RELOC
  71         select SYS_BOOT_GET_CMDLINE
  72         select SYS_BOOT_GET_KBD
  73         select SYS_CACHE_SHIFT_4
  74         select SUPPORT_OF_CONTROL
  75
  76 config MICROBLAZE
  77         bool "MicroBlaze architecture"
  78         select SUPPORT_OF_CONTROL
  79         imply CMD_TIMER
  80         imply SPL_REGMAP if SPL
  81         imply SPL_TIMER if SPL
  82         imply TIMER
  83         imply XILINX_TIMER
  84
  85 config MIPS
  86         bool "MIPS architecture"
  87         select HAVE_ARCH_IOREMAP
  88         select HAVE_PRIVATE_LIBGCC
  89         select SUPPORT_OF_CONTROL
  90         select SPL_SEPARATE_BSS if SPL
  91
  92 config NIOS2
  93         bool "Nios II architecture"
  94         select CPU
  95         select DM
  96         imply DM_EVENT
  97         select OF_CONTROL
  98         select SUPPORT_OF_CONTROL
  99         imply CMD_DM
 100
 101 config PPC
 102         bool "PowerPC architecture"
 103         select HAVE_PRIVATE_LIBGCC
 104         select SUPPORT_OF_CONTROL
 105         select SYS_BOOT_GET_CMDLINE
 106         select SYS_BOOT_GET_KBD
 107
 108 config RISCV
 109         bool "RISC-V architecture"
 110         select CREATE_ARCH_SYMLINK
 111         select SUPPORT_OF_CONTROL
 112         select OF_CONTROL
 113         select DM
 114         imply SPL_SEPARATE_BSS if SPL
 115         imply DM_SERIAL
 116         imply DM_EVENT
 117         imply DM_MMC
 118         imply DM_SPI
 119         imply DM_SPI_FLASH
 120         imply BLK
 121         imply CLK
 122         imply MTD
 123         imply TIMER
 124         imply CMD_DM
 125         imply SPL_DM
 126         imply SPL_OF_CONTROL
 127         imply SPL_LIBCOMMON_SUPPORT
 128         imply SPL_LIBGENERIC_SUPPORT
 129         imply SPL_SERIAL
 130         imply SPL_TIMER
 131
 132 config SANDBOX
 133         bool "Sandbox"
 134         select ARCH_SUPPORTS_LTO
 135         select BOARD_LATE_INIT
 136         select BZIP2
 137         select CMD_POWEROFF
 138         select DM
 139         select DM_FUZZING_ENGINE
 140         select DM_GPIO
 141         select DM_I2C
 142         select DM_KEYBOARD
 143         select DM_MMC
 144         select DM_SERIAL
 145         select DM_SPI
 146         select DM_SPI_FLASH
 147         select GZIP_COMPRESSED
 148         select IO_TRACE
 149         select LZO
 150         select OF_BOARD_SETUP
 151         select PCI_ENDPOINT
 152         select SPI
 153         select SUPPORT_OF_CONTROL
 154         select SYSRESET_CMD_POWEROFF
 155         select SYS_CACHE_SHIFT_4
 156         select IRQ
 157         select SUPPORT_EXTENSION_SCAN
 158         select SUPPORT_ACPI
 159         imply BITREVERSE
 160         select BLOBLIST
 161         imply LTO
 162         imply CMD_DM
 163         imply CMD_EXCEPTION
 164         imply CMD_GETTIME
 165         imply CMD_HASH
 166         imply CMD_IO
 167         imply CMD_IOTRACE
 168         imply CMD_LZMADEC
 169         imply CMD_SF
 170         imply CMD_SF_TEST
 171         imply CRC32_VERIFY
 172         imply FAT_WRITE
 173         imply FIRMWARE
 174         imply FUZZING_ENGINE_SANDBOX
 175         imply HASH_VERIFY
 176         imply LZMA
 177         imply TEE
 178         imply AVB_VERIFY
 179         imply LIBAVB
 180         imply CMD_AVB
 181         imply PARTITION_TYPE_GUID
 182         imply SCP03
 183         imply CMD_SCP03
 184         imply UDP_FUNCTION_FASTBOOT
 185         imply VIRTIO_MMIO
 186         imply VIRTIO_PCI
 187         imply VIRTIO_SANDBOX
 188         imply VIRTIO_BLK
 189         imply VIRTIO_NET
 190         imply DM_SOUND
 191         imply PCI_SANDBOX_EP
 192         imply PCH
 193         imply PHYLIB
 194         imply DM_MDIO
 195         imply DM_MDIO_MUX
 196         imply ACPI_PMC
 197         imply ACPI_PMC_SANDBOX
 198         imply CMD_PMC
 199         imply CMD_CLONE
 200         imply SILENT_CONSOLE
 201         imply BOOTARGS_SUBST
 202         imply PHY_FIXED
 203         imply DM_DSA
 204         imply CMD_EXTENSION
 205         imply KEYBOARD
 206         imply PHYSMEM
 207         imply GENERATE_ACPI_TABLE
 208         imply BINMAN
 209
 210 config SH
 211         bool "SuperH architecture"
 212         select HAVE_PRIVATE_LIBGCC
 213         select SUPPORT_OF_CONTROL
 214
 215 config X86
 216         bool "x86 architecture"
 217         select SUPPORT_SPL
 218         select SUPPORT_TPL
 219         select CREATE_ARCH_SYMLINK
 220         select DM
 221         select HAVE_ARCH_IOMAP
 222         select HAVE_PRIVATE_LIBGCC
 223         select OF_CONTROL
 224         select PCI
 225         select SUPPORT_ACPI
 226         select SUPPORT_OF_CONTROL
 227         select SYS_CACHE_SHIFT_6
 228         select TIMER
 229         select USE_PRIVATE_LIBGCC
 230         select X86_TSC_TIMER
 231         select IRQ
 232         imply HAS_ROM if X86_RESET_VECTOR
 233         imply BLK
 234         imply CMD_DM
 235         imply CMD_FPGA_LOADMK
 236         imply CMD_GETTIME
 237         imply CMD_IO
 238         imply CMD_IRQ
 239         imply CMD_PCI
 240         imply CMD_SF
 241         imply CMD_SF_TEST
 242         imply CMD_ZBOOT
 243         imply DM_EVENT
 244         imply DM_GPIO
 245         imply DM_KEYBOARD
 246         imply DM_MMC
 247         imply DM_RTC
 248         imply DM_SCSI
 249         imply DM_SERIAL
 250         imply DM_SPI
 251         imply DM_SPI_FLASH
 252         imply DM_USB
 253         imply VIDEO
 254         imply SYSRESET
 255         imply SPL_SYSRESET
 256         imply SYSRESET_X86
 257         imply USB_ETHER_ASIX
 258         imply USB_ETHER_SMSC95XX
 259         imply USB_HOST_ETHER
 260         imply PCH
 261         imply PHYSMEM
 262         imply RTC_MC146818
 263         imply ACPIGEN if !QEMU && !EFI_APP
 264         imply SYSINFO if GENERATE_SMBIOS_TABLE
 265         imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
 266         imply TIMESTAMP
 267
 268         # Thing to enable for when SPL/TPL are enabled: SPL
 269         imply SPL_DM
 270         imply SPL_OF_LIBFDT
 271         imply SPL_DRIVERS_MISC
 272         imply SPL_GPIO
 273         imply SPL_PINCTRL
 274         imply SPL_LIBCOMMON_SUPPORT
 275         imply SPL_LIBGENERIC_SUPPORT
 276         imply SPL_SERIAL
 277         imply SPL_SPI_FLASH_SUPPORT
 278         imply SPL_SPI
 279         imply SPL_OF_CONTROL
 280         imply SPL_TIMER
 281         imply SPL_REGMAP
 282         imply SPL_SYSCON
 283         # TPL
 284         imply TPL_DM
 285         imply TPL_DRIVERS_MISC
 286         imply TPL_GPIO
 287         imply TPL_PINCTRL
 288         imply TPL_LIBCOMMON_SUPPORT
 289         imply TPL_LIBGENERIC_SUPPORT
 290         imply TPL_SERIAL
 291         imply TPL_OF_CONTROL
 292         imply TPL_TIMER
 293         imply TPL_REGMAP
 294         imply TPL_SYSCON
 295
 296 config XTENSA
 297         bool "Xtensa architecture"
 298         select CREATE_ARCH_SYMLINK
 299         select SUPPORT_OF_CONTROL
 300
 301 endchoice
 302
 303 config SYS_ARCH
 304         string
 305         help
 306           This option should contain the architecture name to build the
 307           appropriate arch/<CONFIG_SYS_ARCH> directory.
 308           All the architectures should specify this option correctly.
 309
 310 config SYS_CPU
 311         string
 312         help
 313           This option should contain the CPU name to build the correct
 314           arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
 315
 316           This is optional.  For those targets without the CPU directory,
 317           leave this option empty.
 318
 319 config SYS_SOC
 320         string
 321         help
 322           This option should contain the SoC name to build the directory
 323           arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
 324
 325           This is optional.  For those targets without the SoC directory,
 326           leave this option empty.
 327
 328 config SYS_VENDOR
 329         string
 330         help
 331           This option should contain the vendor name of the target board.
 332           If it is set and
 333           board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
 334           directory is compiled.
 335           If CONFIG_SYS_BOARD is also set, the sources under
 336           board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
 337
 338           This is optional.  For those targets without the vendor directory,
 339           leave this option empty.
 340
 341 config SYS_BOARD
 342         string
 343         help
 344           This option should contain the name of the target board.
 345           If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
 346           or board/<CONFIG_SYS_BOARD> directory is compiled depending on
 347           whether CONFIG_SYS_VENDOR is set or not.
 348
 349           This is optional.  For those targets without the board directory,
 350           leave this option empty.
 351
 352 config SYS_CONFIG_NAME
 353         string
 354         help
 355           This option should contain the base name of board header file.
 356           The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
 357           should be included from include/config.h.
 358
 359 config SYS_DISABLE_DCACHE_OPS
 360         bool
 361         help
 362          This option disables dcache flush and dcache invalidation
 363          operations. For example, on coherent systems where cache
 364          operatios are not required, enable this option to avoid them.
 365          Note that, its up to the individual architectures to implement
 366          this functionality.
 367
 368 config SYS_IMMR
 369         hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
 370         depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
 371         default 0xFF000000 if MPC8xx
 372         default 0xF0000000 if ARCH_MPC8313
 373         default 0xE0000000 if MPC83xx && !ARCH_MPC8313
 374         default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
 375         default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
 376                               ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
 377                               ARCH_P2020
 378         default SYS_CCSRBAR_DEFAULT
 379         help
 380           Address for the Internal Memory-Mapped Registers (IMMR) window used
 381           to configure the features of many Freescale / NXP SoCs.
 382
 383 config MONITOR_IS_IN_RAM
 384         bool "U-Boot is loaded in to RAM by a pre-loader"
 385         depends on M68K || NIOS2
 386
 387 config SKIP_LOWLEVEL_INIT
 388         bool "Skip the calls to certain low level initialization functions"
 389         depends on ARM || MIPS || RISCV
 390         help
 391           If enabled, then certain low level initializations (like setting up
 392           the memory controller) are omitted and/or U-Boot does not relocate
 393           itself into RAM.
 394           Normally this variable MUST NOT be defined. The only exception is
 395           when U-Boot is loaded (to RAM) by some other boot loader or by a
 396           debugger which performs these initializations itself.
 397
 398 config SPL_SKIP_LOWLEVEL_INIT
 399         bool "Skip the calls to certain low level initialization functions"
 400         depends on SPL && (ARM || MIPS || RISCV)
 401         help
 402           If enabled, then certain low level initializations (like setting up
 403           the memory controller) are omitted and/or U-Boot does not relocate
 404           itself into RAM.
 405           Normally this variable MUST NOT be defined. The only exception is
 406           when U-Boot is loaded (to RAM) by some other boot loader or by a
 407           debugger which performs these initializations itself.
 408
 409 config TPL_SKIP_LOWLEVEL_INIT
 410         bool "Skip the calls to certain low level initialization functions"
 411         depends on SPL && ARM
 412         help
 413           If enabled, then certain low level initializations (like setting up
 414           the memory controller) are omitted and/or U-Boot does not relocate
 415           itself into RAM.
 416           Normally this variable MUST NOT be defined. The only exception is
 417           when U-Boot is loaded (to RAM) by some other boot loader or by a
 418           debugger which performs these initializations itself.
 419
 420 config SKIP_LOWLEVEL_INIT_ONLY
 421         bool "Skip the call to lowlevel_init during early boot ONLY"
 422         depends on ARM
 423         help
 424           This allows just the call to lowlevel_init() to be skipped. The
 425           normal CP15 init (such as enabling the instruction cache) is still
 426           performed.
 427
 428 config SPL_SKIP_LOWLEVEL_INIT_ONLY
 429         bool "Skip the call to lowlevel_init during early boot ONLY"
 430         depends on SPL && ARM
 431         help
 432           This allows just the call to lowlevel_init() to be skipped. The
 433           normal CP15 init (such as enabling the instruction cache) is still
 434           performed.
 435
 436 config TPL_SKIP_LOWLEVEL_INIT_ONLY
 437         bool "Skip the call to lowlevel_init during early boot ONLY"
 438         depends on TPL && ARM
 439         help
 440           This allows just the call to lowlevel_init() to be skipped. The
 441           normal CP15 init (such as enabling the instruction cache) is still
 442           performed.
 443
 444 config SYS_HAS_NONCACHED_MEMORY
 445         bool "Enable reserving a non-cached memory area for drivers"
 446         depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
 447         help
 448           This is useful for drivers that would otherwise require a lot of
 449           explicit cache maintenance. For some drivers it's also impossible to
 450           properly maintain the cache. For example if the regions that need to
 451           be flushed are not a multiple of the cache-line size, *and* padding
 452           cannot be allocated between the regions to align them (i.e.  if the
 453           HW requires a contiguous array of regions, and the size of each
 454           region is not cache-aligned), then a flush of one region may result
 455           in overwriting data that hardware has written to another region in
 456           the same cache-line. This can happen for example in network drivers
 457           where descriptors for buffers are typically smaller than the CPU
 458           cache-line (e.g.  16 bytes vs. 32 or 64 bytes).
 459
 460 config SYS_NONCACHED_MEMORY
 461         hex "Size in bytes of the non-cached memory area"
 462         depends on SYS_HAS_NONCACHED_MEMORY
 463         default 0x100000
 464         help
 465           Size of non-cached memory area. This area of memory will be typically
 466           located right below the malloc() area and mapped uncached in the MMU.
 467
 468 source "arch/arc/Kconfig"
 469 source "arch/arm/Kconfig"
 470 source "arch/m68k/Kconfig"
 471 source "arch/microblaze/Kconfig"
 472 source "arch/mips/Kconfig"
 473 source "arch/nios2/Kconfig"
 474 source "arch/powerpc/Kconfig"
 475 source "arch/sandbox/Kconfig"
 476 source "arch/sh/Kconfig"
 477 source "arch/x86/Kconfig"
 478 source "arch/xtensa/Kconfig"
 479 source "arch/riscv/Kconfig"
 480
 481 if ARM || M68K || PPC
 482
 483 source "arch/Kconfig.nxp"
 484
 485 endif
 486
 487 source "board/keymile/Kconfig"
 488
 489 if MIPS || MICROBLAZE
 490
 491 choice
 492         prompt "Endianness selection"
 493         help
 494           Some MIPS boards can be configured for either little or big endian
 495           byte order. These modes require different U-Boot images. In general there
 496           is one preferred byteorder for a particular system but some systems are
 497           just as commonly used in the one or the other endianness.
 498
 499 config SYS_BIG_ENDIAN
 500         bool "Big endian"
 501         depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
 502
 503 config SYS_LITTLE_ENDIAN
 504         bool "Little endian"
 505         depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
 506
 507 endchoice
 508
 509 endif