2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arcregs.h>
10 /* Bit values in IC_CTRL */
11 #define IC_CTRL_CACHE_DISABLE (1 << 0)
13 /* Bit values in DC_CTRL */
14 #define DC_CTRL_CACHE_DISABLE (1 << 0)
15 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
16 #define DC_CTRL_FLUSH_STATUS (1 << 8)
17 #define CACHE_VER_NUM_MASK 0xF
19 int icache_status(void)
21 /* If no cache in CPU exit immediately */
22 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
25 return (read_aux_reg(ARC_AUX_IC_CTRL
) & IC_CTRL_CACHE_DISABLE
) !=
26 IC_CTRL_CACHE_DISABLE
;
29 void icache_enable(void)
31 /* If no cache in CPU exit immediately */
32 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
35 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) &
36 ~IC_CTRL_CACHE_DISABLE
);
39 void icache_disable(void)
41 /* If no cache in CPU exit immediately */
42 if (!(read_aux_reg(ARC_BCR_IC_BUILD
) & CACHE_VER_NUM_MASK
))
45 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) |
46 IC_CTRL_CACHE_DISABLE
);
49 void invalidate_icache_all(void)
51 #ifndef CONFIG_SYS_ICACHE_OFF
52 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
53 write_aux_reg(ARC_AUX_IC_IVIC
, 1);
54 #endif /* CONFIG_SYS_ICACHE_OFF */
57 int dcache_status(void)
59 /* If no cache in CPU exit immediately */
60 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
63 return (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_CACHE_DISABLE
) !=
64 DC_CTRL_CACHE_DISABLE
;
67 void dcache_enable(void)
69 /* If no cache in CPU exit immediately */
70 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
73 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) &
74 ~(DC_CTRL_INV_MODE_FLUSH
| DC_CTRL_CACHE_DISABLE
));
77 void dcache_disable(void)
79 /* If no cache in CPU exit immediately */
80 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
83 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) |
84 DC_CTRL_CACHE_DISABLE
);
87 void flush_dcache_all(void)
89 /* If no cache in CPU exit immediately */
90 if (!(read_aux_reg(ARC_BCR_DC_BUILD
) & CACHE_VER_NUM_MASK
))
93 /* Do flush of entire cache */
94 write_aux_reg(ARC_AUX_DC_FLSH
, 1);
97 while (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
101 #ifndef CONFIG_SYS_DCACHE_OFF
102 static void dcache_flush_line(unsigned addr
)
104 #if (CONFIG_ARC_MMU_VER == 3)
105 write_aux_reg(ARC_AUX_DC_PTAG
, addr
);
107 write_aux_reg(ARC_AUX_DC_FLDL
, addr
);
110 while (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
113 #ifndef CONFIG_SYS_ICACHE_OFF
115 * Invalidate I$ for addresses range just flushed from D$.
116 * If we try to execute data flushed above it will be valid/correct
118 #if (CONFIG_ARC_MMU_VER == 3)
119 write_aux_reg(ARC_AUX_IC_PTAG
, addr
);
121 write_aux_reg(ARC_AUX_IC_IVIL
, addr
);
122 #endif /* CONFIG_SYS_ICACHE_OFF */
124 #endif /* CONFIG_SYS_DCACHE_OFF */
126 void flush_dcache_range(unsigned long start
, unsigned long end
)
128 #ifndef CONFIG_SYS_DCACHE_OFF
131 start
= start
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
132 end
= end
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
134 for (addr
= start
; addr
<= end
; addr
+= CONFIG_SYS_CACHELINE_SIZE
)
135 dcache_flush_line(addr
);
136 #endif /* CONFIG_SYS_DCACHE_OFF */
139 void invalidate_dcache_range(unsigned long start
, unsigned long end
)
141 #ifndef CONFIG_SYS_DCACHE_OFF
144 start
= start
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
145 end
= end
& (~(CONFIG_SYS_CACHELINE_SIZE
- 1));
147 for (addr
= start
; addr
<= end
; addr
+= CONFIG_SYS_CACHELINE_SIZE
) {
148 #if (CONFIG_ARC_MMU_VER == 3)
149 write_aux_reg(ARC_AUX_DC_PTAG
, addr
);
151 write_aux_reg(ARC_AUX_DC_IVDL
, addr
);
153 #endif /* CONFIG_SYS_DCACHE_OFF */
156 void invalidate_dcache_all(void)
158 #ifndef CONFIG_SYS_DCACHE_OFF
159 /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
160 write_aux_reg(ARC_AUX_DC_IVDC
, 1);
161 #endif /* CONFIG_SYS_DCACHE_OFF */
164 void flush_cache(unsigned long start
, unsigned long size
)
166 flush_dcache_range(start
, start
+ size
);