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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arc/lib/cache.c
2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <asm/arcregs.h>
12 #include <asm/cache.h>
14 /* Bit values in IC_CTRL */
15 #define IC_CTRL_CACHE_DISABLE (1 << 0)
17 /* Bit values in DC_CTRL */
18 #define DC_CTRL_CACHE_DISABLE (1 << 0)
19 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
20 #define DC_CTRL_FLUSH_STATUS (1 << 8)
21 #define CACHE_VER_NUM_MASK 0xF
22 #define SLC_CTRL_SB (1 << 2)
29 * By default that variable will fall into .bss section.
30 * But .bss section is not relocated and so it will be initilized before
31 * relocation but will be used after being zeroed.
33 int l1_line_sz
__section(".data");
34 int dcache_exists
__section(".data");
35 int icache_exists
__section(".data");
37 #define CACHE_LINE_MASK (~(l1_line_sz - 1))
39 #ifdef CONFIG_ISA_ARCV2
40 int slc_line_sz
__section(".data");
41 int slc_exists
__section(".data");
42 int ioc_exists
__section(".data");
44 static unsigned int __before_slc_op(const int op
)
46 unsigned int reg
= reg
;
50 * IM is set by default and implies Flush-n-inv
51 * Clear it here for vanilla inv
53 reg
= read_aux_reg(ARC_AUX_SLC_CTRL
);
54 write_aux_reg(ARC_AUX_SLC_CTRL
, reg
& ~DC_CTRL_INV_MODE_FLUSH
);
60 static void __after_slc_op(const int op
, unsigned int reg
)
62 if (op
& OP_FLUSH
) /* flush / flush-n-inv both wait */
63 while (read_aux_reg(ARC_AUX_SLC_CTRL
) &
67 /* Switch back to default Invalidate mode */
69 write_aux_reg(ARC_AUX_SLC_CTRL
, reg
| DC_CTRL_INV_MODE_FLUSH
);
72 static inline void __slc_line_loop(unsigned long paddr
, unsigned long sz
,
78 #define SLC_LINE_MASK (~(slc_line_sz - 1))
80 aux_cmd
= op
& OP_INV
? ARC_AUX_SLC_IVDL
: ARC_AUX_SLC_FLDL
;
82 sz
+= paddr
& ~SLC_LINE_MASK
;
83 paddr
&= SLC_LINE_MASK
;
85 num_lines
= DIV_ROUND_UP(sz
, slc_line_sz
);
87 while (num_lines
-- > 0) {
88 write_aux_reg(aux_cmd
, paddr
);
93 static inline void __slc_entire_op(const int cacheop
)
96 unsigned int ctrl_reg
= __before_slc_op(cacheop
);
98 if (cacheop
& OP_INV
) /* Inv or flush-n-inv use same cmd reg */
99 aux
= ARC_AUX_SLC_INVALIDATE
;
101 aux
= ARC_AUX_SLC_FLUSH
;
103 write_aux_reg(aux
, 0x1);
105 __after_slc_op(cacheop
, ctrl_reg
);
108 static inline void __slc_line_op(unsigned long paddr
, unsigned long sz
,
111 unsigned int ctrl_reg
= __before_slc_op(cacheop
);
112 __slc_line_loop(paddr
, sz
, cacheop
);
113 __after_slc_op(cacheop
, ctrl_reg
);
116 #define __slc_entire_op(cacheop)
117 #define __slc_line_op(paddr, sz, cacheop)
120 #ifdef CONFIG_ISA_ARCV2
121 static void read_decode_cache_bcr_arcv2(void)
125 #ifdef CONFIG_CPU_BIG_ENDIAN
126 unsigned int pad
:24, way
:2, lsz
:2, sz
:4;
128 unsigned int sz
:4, lsz
:2, way
:2, pad
:24;
136 #ifdef CONFIG_CPU_BIG_ENDIAN
137 unsigned int pad
:24, ver
:8;
139 unsigned int ver
:8, pad
:24;
145 sbcr
.word
= read_aux_reg(ARC_BCR_SLC
);
146 if (sbcr
.fields
.ver
) {
147 slc_cfg
.word
= read_aux_reg(ARC_AUX_SLC_CONFIG
);
149 slc_line_sz
= (slc_cfg
.fields
.lsz
== 0) ? 128 : 64;
153 struct bcr_clust_cfg
{
154 #ifdef CONFIG_CPU_BIG_ENDIAN
155 unsigned int pad
:7, c
:1, num_entries
:8, num_cores
:8, ver
:8;
157 unsigned int ver
:8, num_cores
:8, num_entries
:8, c
:1, pad
:7;
163 cbcr
.word
= read_aux_reg(ARC_BCR_CLUSTER
);
169 void read_decode_cache_bcr(void)
171 int dc_line_sz
= 0, ic_line_sz
= 0;
175 #ifdef CONFIG_CPU_BIG_ENDIAN
176 unsigned int pad
:12, line_len
:4, sz
:4, config
:4, ver
:8;
178 unsigned int ver
:8, config
:4, sz
:4, line_len
:4, pad
:12;
184 ibcr
.word
= read_aux_reg(ARC_BCR_IC_BUILD
);
185 if (ibcr
.fields
.ver
) {
187 l1_line_sz
= ic_line_sz
= 8 << ibcr
.fields
.line_len
;
189 panic("Instruction exists but line length is 0\n");
192 dbcr
.word
= read_aux_reg(ARC_BCR_DC_BUILD
);
193 if (dbcr
.fields
.ver
){
195 l1_line_sz
= dc_line_sz
= 16 << dbcr
.fields
.line_len
;
197 panic("Data cache exists but line length is 0\n");
200 if (ic_line_sz
&& dc_line_sz
&& (ic_line_sz
!= dc_line_sz
))
201 panic("Instruction and data cache line lengths differ\n");
204 void cache_init(void)
206 read_decode_cache_bcr();
208 #ifdef CONFIG_ISA_ARCV2
209 read_decode_cache_bcr_arcv2();
213 invalidate_dcache_all();
215 /* IO coherency base - 0x8z */
216 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE
, 0x80000);
217 /* IO coherency aperture size - 512Mb: 0x8z-0xAz */
218 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE
, 0x11);
219 /* Enable partial writes */
220 write_aux_reg(ARC_AUX_IO_COH_PARTIAL
, 1);
221 /* Enable IO coherency */
222 write_aux_reg(ARC_AUX_IO_COH_ENABLE
, 1);
227 int icache_status(void)
232 if (read_aux_reg(ARC_AUX_IC_CTRL
) & IC_CTRL_CACHE_DISABLE
)
238 void icache_enable(void)
241 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) &
242 ~IC_CTRL_CACHE_DISABLE
);
245 void icache_disable(void)
248 write_aux_reg(ARC_AUX_IC_CTRL
, read_aux_reg(ARC_AUX_IC_CTRL
) |
249 IC_CTRL_CACHE_DISABLE
);
252 #ifndef CONFIG_SYS_DCACHE_OFF
253 void invalidate_icache_all(void)
255 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
256 if (icache_status()) {
257 write_aux_reg(ARC_AUX_IC_IVIC
, 1);
258 read_aux_reg(ARC_AUX_IC_CTRL
); /* blocks */
262 void invalidate_icache_all(void)
267 int dcache_status(void)
272 if (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_CACHE_DISABLE
)
278 void dcache_enable(void)
283 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) &
284 ~(DC_CTRL_INV_MODE_FLUSH
| DC_CTRL_CACHE_DISABLE
));
287 void dcache_disable(void)
292 write_aux_reg(ARC_AUX_DC_CTRL
, read_aux_reg(ARC_AUX_DC_CTRL
) |
293 DC_CTRL_CACHE_DISABLE
);
296 #ifndef CONFIG_SYS_DCACHE_OFF
298 * Common Helper for Line Operations on {I,D}-Cache
300 static inline void __cache_line_loop(unsigned long paddr
, unsigned long sz
,
303 unsigned int aux_cmd
;
304 #if (CONFIG_ARC_MMU_VER == 3)
305 unsigned int aux_tag
;
309 if (cacheop
== OP_INV_IC
) {
310 aux_cmd
= ARC_AUX_IC_IVIL
;
311 #if (CONFIG_ARC_MMU_VER == 3)
312 aux_tag
= ARC_AUX_IC_PTAG
;
315 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
316 aux_cmd
= cacheop
& OP_INV
? ARC_AUX_DC_IVDL
: ARC_AUX_DC_FLDL
;
317 #if (CONFIG_ARC_MMU_VER == 3)
318 aux_tag
= ARC_AUX_DC_PTAG
;
322 sz
+= paddr
& ~CACHE_LINE_MASK
;
323 paddr
&= CACHE_LINE_MASK
;
325 num_lines
= DIV_ROUND_UP(sz
, l1_line_sz
);
327 while (num_lines
-- > 0) {
328 #if (CONFIG_ARC_MMU_VER == 3)
329 write_aux_reg(aux_tag
, paddr
);
331 write_aux_reg(aux_cmd
, paddr
);
336 static unsigned int __before_dc_op(const int op
)
342 * IM is set by default and implies Flush-n-inv
343 * Clear it here for vanilla inv
345 reg
= read_aux_reg(ARC_AUX_DC_CTRL
);
346 write_aux_reg(ARC_AUX_DC_CTRL
, reg
& ~DC_CTRL_INV_MODE_FLUSH
);
352 static void __after_dc_op(const int op
, unsigned int reg
)
354 if (op
& OP_FLUSH
) /* flush / flush-n-inv both wait */
355 while (read_aux_reg(ARC_AUX_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
358 /* Switch back to default Invalidate mode */
360 write_aux_reg(ARC_AUX_DC_CTRL
, reg
| DC_CTRL_INV_MODE_FLUSH
);
363 static inline void __dc_entire_op(const int cacheop
)
366 unsigned int ctrl_reg
= __before_dc_op(cacheop
);
368 if (cacheop
& OP_INV
) /* Inv or flush-n-inv use same cmd reg */
369 aux
= ARC_AUX_DC_IVDC
;
371 aux
= ARC_AUX_DC_FLSH
;
373 write_aux_reg(aux
, 0x1);
375 __after_dc_op(cacheop
, ctrl_reg
);
378 static inline void __dc_line_op(unsigned long paddr
, unsigned long sz
,
381 unsigned int ctrl_reg
= __before_dc_op(cacheop
);
382 __cache_line_loop(paddr
, sz
, cacheop
);
383 __after_dc_op(cacheop
, ctrl_reg
);
386 #define __dc_entire_op(cacheop)
387 #define __dc_line_op(paddr, sz, cacheop)
388 #endif /* !CONFIG_SYS_DCACHE_OFF */
390 void invalidate_dcache_range(unsigned long start
, unsigned long end
)
392 #ifdef CONFIG_ISA_ARCV2
395 __dc_line_op(start
, end
- start
, OP_INV
);
397 #ifdef CONFIG_ISA_ARCV2
398 if (slc_exists
&& !ioc_exists
)
399 __slc_line_op(start
, end
- start
, OP_INV
);
403 void flush_dcache_range(unsigned long start
, unsigned long end
)
405 #ifdef CONFIG_ISA_ARCV2
408 __dc_line_op(start
, end
- start
, OP_FLUSH
);
410 #ifdef CONFIG_ISA_ARCV2
411 if (slc_exists
&& !ioc_exists
)
412 __slc_line_op(start
, end
- start
, OP_FLUSH
);
416 void flush_cache(unsigned long start
, unsigned long size
)
418 flush_dcache_range(start
, start
+ size
);
421 void invalidate_dcache_all(void)
423 __dc_entire_op(OP_INV
);
425 #ifdef CONFIG_ISA_ARCV2
427 __slc_entire_op(OP_INV
);
431 void flush_dcache_all(void)
433 __dc_entire_op(OP_FLUSH
);
435 #ifdef CONFIG_ISA_ARCV2
437 __slc_entire_op(OP_FLUSH
);