1 menu "ARM architecture"
11 select SYS_CACHE_SHIFT_6
12 imply SPL_SEPARATE_BSS
15 bool "Enable support for CRC32 instruction"
16 depends on ARM64 && CC_IS_GCC
19 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
20 This is faster than software crc32 calculation. This instruction may
21 not be present on all ARMv8.0, but is always present on ARMv8.1 and
24 config COUNTER_FREQUENCY
25 int "Timer clock frequency"
26 depends on ARM64 || CPU_V7A
27 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
28 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
29 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
30 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
31 default 100000000 if ARCH_ZYNQMP
32 default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
35 For platforms with ARMv8-A and ARMv7-A which features a system
36 counter, those platforms needs software to program the counter
37 frequency. Setup time clock frequency for certain platform.
38 0 means no need to configure the system counter frequency.
39 For platforms needs the frequency set in U-Boot with a
40 pre-defined value, should have the macro defined as a non-zero value.
42 config POSITION_INDEPENDENT
43 bool "Generate position-independent pre-relocation code"
44 depends on ARM64 || CPU_V7A
46 U-Boot expects to be linked to a specific hard-coded address, and to
47 be loaded to and run from that address. This option lifts that
48 restriction, thus allowing the code to be loaded to and executed from
49 almost any 4K aligned address. This logic relies on the relocation
50 information that is embedded in the binary to support U-Boot
51 relocating itself to the top-of-RAM later during execution.
53 config INIT_SP_RELATIVE
54 bool "Specify the early stack pointer relative to the .bss section"
56 default n if ARCH_QEMU
57 default y if POSITION_INDEPENDENT
59 U-Boot typically uses a hard-coded value for the stack pointer
60 before relocation. Enable this option to instead calculate the
61 initial SP at run-time. This is useful to avoid hard-coding addresses
62 into U-Boot, so that it can be loaded and executed at arbitrary
63 addresses and thus avoid using arbitrary addresses at runtime.
65 If this option is enabled, the early stack pointer is set to
66 &_bss_start with a offset value added. The offset is specified by
67 SYS_INIT_SP_BSS_OFFSET.
69 config SYS_INIT_SP_BSS_OFFSET
70 int "Early stack offset from the .bss base address"
72 depends on INIT_SP_RELATIVE
75 This option's value is the offset added to &_bss_start in order to
76 calculate the stack pointer. This offset should be large enough so
77 that the early malloc region, global data (gd), and early stack usage
78 do not overlap any appended DTB.
80 config SPL_SYS_NO_VECTOR_TABLE
84 config SPL_USE_SEPARATE_FAULT_HANDLERS
85 bool "Use separate fault handlers instead of a single common one"
86 depends on !SPL_SYS_NO_VECTOR_TABLE && !ARM64 && !CPU_V7M
88 Instead of a common fault handler, generate a separate one for
89 undefined_instruction, software_interrupt, prefetch_abort etc.
90 This is for debugging purposes, when you want to set breakpoints
93 config LINUX_KERNEL_IMAGE_HEADER
97 Place a Linux kernel image header at the start of the U-Boot binary.
98 The format of the header is described in the Linux kernel source at
99 Documentation/arm64/booting.txt. This feature is useful since the
100 image header reports the amount of memory (BSS and similar) that
101 U-Boot needs to use, but which isn't part of the binary.
103 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
104 depends on LINUX_KERNEL_IMAGE_HEADER
107 The value subtracted from CONFIG_TEXT_BASE to calculate the
108 TEXT_OFFSET value written to the Linux kernel image header.
120 ARM GICV3 Interrupt translation service (ITS).
121 Basic support for programming locality specific peripheral
122 interrupts (LPI) configuration tables and enable LPI tables.
123 LPI configuration table can be used by u-boot or Linux.
124 ARM GICV3 has limitation, once the LPI table is enabled, LPI
125 configuration table can not be re-programmed, unless GICV3 reset.
127 config GICV3_SUPPORT_GIC600
128 bool "ARM GICV3 GIC600 SUPPORT"
130 ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
131 implements a power control register in the Redistributor frame.This
132 register must be programmed to mark the frame as powered on, before
133 accessing other registers in the frame. Rest of initialization sequence
140 config DMA_ADDR_T_64BIT
150 config GPIO_EXTRA_HEADER
153 # Used for compatibility with asm files copied from the kernel
154 config ARM_ASM_UNIFIED
158 # Used for compatibility with asm files copied from the kernel
162 config SYS_ICACHE_OFF
163 bool "Do not enable icache"
165 Do not enable instruction cache in U-Boot.
167 config SPL_SYS_ICACHE_OFF
168 bool "Do not enable icache in SPL"
170 default SYS_ICACHE_OFF
172 Do not enable instruction cache in SPL.
174 config SYS_DCACHE_OFF
175 bool "Do not enable dcache"
177 Do not enable data cache in U-Boot.
179 config SPL_SYS_DCACHE_OFF
180 bool "Do not enable dcache in SPL"
182 default SYS_DCACHE_OFF
184 Do not enable data cache in SPL.
186 config SYS_ARM_CACHE_CP15
187 bool "CP15 based cache enabling support"
189 Select this if your processor suports enabling caches by using
193 bool "MMU-based Paged Memory Management Support"
194 select SYS_ARM_CACHE_CP15
196 Select if you want MMU-based virtualised addressing space
197 support via paged memory management.
200 bool 'Use the ARM v7 PMSA Compliant MPU'
202 Some ARM systems without an MMU have instead a Memory Protection
203 Unit (MPU) that defines the type and permissions for regions of
205 If your CPU has an MPU then you should choose 'y' here unless you
206 know that you do not want to use the MPU.
208 # If set, the workarounds for these ARM errata are applied early during U-Boot
209 # startup. Note that in general these options force the workarounds to be
210 # applied; no CPU-type/version detection exists, unlike the similar options in
211 # the Linux kernel. Do not set these options unless they apply! Also note that
212 # the following can be machine-specific errata. These do have ability to
213 # provide rudimentary version and machine-specific checks, but expect no
215 # CONFIG_ARM_ERRATA_430973
216 # CONFIG_ARM_ERRATA_454179
217 # CONFIG_ARM_ERRATA_621766
218 # CONFIG_ARM_ERRATA_798870
219 # CONFIG_ARM_ERRATA_801819
220 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
221 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
223 config ARM_ERRATA_430973
226 config ARM_ERRATA_454179
229 config ARM_ERRATA_621766
232 config ARM_ERRATA_716044
235 config ARM_ERRATA_725233
238 config ARM_ERRATA_742230
241 config ARM_ERRATA_743622
244 config ARM_ERRATA_751472
247 config ARM_ERRATA_761320
250 config ARM_ERRATA_773022
253 config ARM_ERRATA_774769
256 config ARM_ERRATA_794072
259 config ARM_ERRATA_798870
262 config ARM_ERRATA_801819
265 config ARM_ERRATA_826974
268 config ARM_ERRATA_828024
271 config ARM_ERRATA_829520
274 config ARM_ERRATA_833069
277 config ARM_ERRATA_833471
280 config ARM_ERRATA_845369
283 config ARM_ERRATA_852421
286 config ARM_ERRATA_852423
289 config ARM_ERRATA_855873
292 config ARM_CORTEX_A8_CVE_2017_5715
295 config ARM_CORTEX_A15_CVE_2017_5715
300 select SYS_CACHE_SHIFT_5
305 select SYS_CACHE_SHIFT_5
310 select SYS_CACHE_SHIFT_5
312 imply SPL_SEPARATE_BSS
316 select SYS_CACHE_SHIFT_5
321 select SYS_CACHE_SHIFT_5
323 imply SPL_SEPARATE_BSS
328 select SYS_CACHE_SHIFT_5
335 select SYS_CACHE_SHIFT_6
342 select SYS_CACHE_SHIFT_5
343 select SYS_THUMB_BUILD
349 select SYS_ARM_CACHE_CP15
351 select SYS_CACHE_SHIFT_6
354 default "arm720t" if CPU_ARM720T
355 default "arm920t" if CPU_ARM920T
356 default "arm926ejs" if CPU_ARM926EJS
357 default "arm946es" if CPU_ARM946ES
358 default "arm1136" if CPU_ARM1136
359 default "arm1176" if CPU_ARM1176
360 default "armv7" if CPU_V7A
361 default "armv7" if CPU_V7R
362 default "armv7m" if CPU_V7M
363 default "armv8" if ARM64
367 default 4 if CPU_ARM720T
368 default 4 if CPU_ARM920T
369 default 5 if CPU_ARM926EJS
370 default 5 if CPU_ARM946ES
371 default 6 if CPU_ARM1136
372 default 6 if CPU_ARM1176
379 prompt "Select the ARM data write cache policy"
380 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMNS || RZA1
381 default SYS_ARM_CACHE_WRITEBACK
383 config SYS_ARM_CACHE_WRITEBACK
384 bool "Write-back (WB)"
386 A write updates the cache only and marks the cache line as dirty.
387 External memory is updated only when the line is evicted or explicitly
390 config SYS_ARM_CACHE_WRITETHROUGH
391 bool "Write-through (WT)"
393 A write updates both the cache and the external memory system.
394 This does not mark the cache line as dirty.
396 config SYS_ARM_CACHE_WRITEALLOC
397 bool "Write allocation (WA)"
399 A cache line is allocated on a write miss. This means that executing a
400 store instruction on the processor might cause a burst read to occur.
401 There is a linefill to obtain the data for the cache line, before the
405 config ARCH_VERY_EARLY_INIT
408 config SPL_ARCH_VERY_EARLY_INIT
412 bool "Enable ARCH_CPU_INIT"
414 Some architectures require a call to arch_cpu_init().
415 Say Y here to enable it
417 config SYS_ARCH_TIMER
418 bool "ARM Generic Timer support"
419 depends on CPU_V7A || ARM64
422 The ARM Generic Timer (aka arch-timer) provides an architected
423 interface to a timer source on an SoC.
424 It is mandatory for ARMv8 implementation and widely available
428 bool "Support for ARM SMC Calling Convention (SMCCC)"
429 depends on CPU_V7A || ARM64
432 Say Y here if you want to enable ARM SMC Calling Convention.
433 This should be enabled if U-Boot needs to communicate with system
434 firmware (for example, PSCI) according to SMCCC.
436 config SYS_THUMB_BUILD
437 bool "Build U-Boot using the Thumb instruction set"
440 Use this flag to build U-Boot using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
445 config SPL_SYS_THUMB_BUILD
446 bool "Build SPL using the Thumb instruction set"
447 default y if SYS_THUMB_BUILD
448 depends on !ARM64 && SPL
450 Use this flag to build SPL using the Thumb instruction set for
451 ARM architectures. Thumb instruction set provides better code
452 density. For ARM architectures that support Thumb2 this flag will
453 result in Thumb2 code generated by GCC.
455 config TPL_SYS_THUMB_BUILD
456 bool "Build TPL using the Thumb instruction set"
457 default y if SYS_THUMB_BUILD
458 depends on TPL && !ARM64
460 Use this flag to build TPL using the Thumb instruction set for
461 ARM architectures. Thumb instruction set provides better code
462 density. For ARM architectures that support Thumb2 this flag will
463 result in Thumb2 code generated by GCC.
466 bool "ARM PL310 L2 cache controller"
468 Enable support for ARM PL310 L2 cache controller in U-Boot
470 config SPL_SYS_L2_PL310
471 bool "ARM PL310 L2 cache controller in SPL"
473 Enable support for ARM PL310 L2 cache controller in SPL
475 config SYS_L2CACHE_OFF
478 If SoC does not support L2CACHE or one does not want to enable
479 L2CACHE, choose this option.
481 config ENABLE_ARM_SOC_BOOT0_HOOK
482 bool "prepare BOOT0 header"
484 If the SoC's BOOT0 requires a header area filled with (magic)
485 values, then choose this option, and create a file included as
486 <asm/arch/boot0.h> which contains the required assembler code.
488 config USE_ARCH_MEMCPY
489 bool "Use an assembly optimized implementation of memcpy"
491 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
493 Enable the generation of an optimized version of memcpy.
494 Such an implementation may be faster under some conditions
495 but may increase the binary size.
497 config SPL_USE_ARCH_MEMCPY
498 bool "Use an assembly optimized implementation of memcpy for SPL"
499 default y if USE_ARCH_MEMCPY
502 Enable the generation of an optimized version of memcpy.
503 Such an implementation may be faster under some conditions
504 but may increase the binary size.
506 config TPL_USE_ARCH_MEMCPY
507 bool "Use an assembly optimized implementation of memcpy for TPL"
508 default y if USE_ARCH_MEMCPY
511 Enable the generation of an optimized version of memcpy.
512 Such an implementation may be faster under some conditions
513 but may increase the binary size.
515 config USE_ARCH_MEMMOVE
516 bool "Use an assembly optimized implementation of memmove" if !ARM64
517 default USE_ARCH_MEMCPY if ARM64
520 Enable the generation of an optimized version of memmove.
521 Such an implementation may be faster under some conditions
522 but may increase the binary size.
524 config SPL_USE_ARCH_MEMMOVE
525 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
526 default SPL_USE_ARCH_MEMCPY if ARM64
527 depends on SPL && ARM64
529 Enable the generation of an optimized version of memmove.
530 Such an implementation may be faster under some conditions
531 but may increase the binary size.
533 config TPL_USE_ARCH_MEMMOVE
534 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
535 default TPL_USE_ARCH_MEMCPY if ARM64
536 depends on TPL && ARM64
538 Enable the generation of an optimized version of memmove.
539 Such an implementation may be faster under some conditions
540 but may increase the binary size.
542 config USE_ARCH_MEMSET
543 bool "Use an assembly optimized implementation of memset"
545 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
547 Enable the generation of an optimized version of memset.
548 Such an implementation may be faster under some conditions
549 but may increase the binary size.
551 config SPL_USE_ARCH_MEMSET
552 bool "Use an assembly optimized implementation of memset for SPL"
553 default y if USE_ARCH_MEMSET
556 Enable the generation of an optimized version of memset.
557 Such an implementation may be faster under some conditions
558 but may increase the binary size.
560 config TPL_USE_ARCH_MEMSET
561 bool "Use an assembly optimized implementation of memset for TPL"
562 default y if USE_ARCH_MEMSET
565 Enable the generation of an optimized version of memset.
566 Such an implementation may be faster under some conditions
567 but may increase the binary size.
569 config ARM64_SUPPORT_AARCH32
570 bool "ARM64 system support AArch32 execution state"
572 default y if !TARGET_THUNDERX_88XX
574 This ARM64 system supports AArch32 execution state.
580 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
583 prompt "Target select"
588 select GPIO_EXTRA_HEADER
589 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
590 select SPL_SEPARATE_BSS if SPL
591 imply SYS_THUMB_BUILD
596 select GPIO_EXTRA_HEADER
597 select SPL_DM_SPI if SPL
600 Support for TI's DaVinci platform.
603 bool "Hisilicon HiSTB SoCs"
610 Support for HiSTB SoCs.
613 bool "Marvell Kirkwood"
614 select ARCH_MISC_INIT
615 select BOARD_EARLY_INIT_F
617 select GPIO_EXTRA_HEADER
621 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
622 select ARCH_EARLY_INIT_R if ARM64
627 select GPIO_EXTRA_HEADER
629 select SPL_DM_SPI if SPL
630 select SPL_DM_SPI_FLASH if SPL
631 select SPL_TIMER if SPL
632 select TIMER if !ARM64
641 select GPIO_EXTRA_HEADER
642 select SPL_SEPARATE_BSS if SPL
646 bool "Broadcom BCM283X family"
650 select GPIO_EXTRA_HEADER
653 select SERIAL_SEARCH_ALL
658 bool "Broadcom BCM7XXX family"
661 select GPIO_EXTRA_HEADER
664 imply OF_HAS_PRIOR_STAGE
666 This enables support for Broadcom ARM-based set-top box
667 chipsets, including the 7445 family of chips.
670 bool "Broadcom broadband chip family"
675 config TARGET_VEXPRESS_CA9X4
676 bool "Support vexpress_ca9x4"
681 bool "Support Broadcom Northstar"
689 select ARM_GLOBAL_TIMER
690 imply SYS_THUMB_BUILD
693 imply NAND_BRCMNAND_IPROC
695 Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
696 ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
700 bool "Support Broadcom NS3"
702 select BOARD_LATE_INIT
704 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
705 ARMv8 Cortex-A72 processors targeting a broad range of networking
709 bool "Samsung EXYNOS"
719 select GPIO_EXTRA_HEADER
720 imply SYS_THUMB_BUILD
725 bool "Samsung S5PC1XX"
731 select GPIO_EXTRA_HEADER
735 bool "Calxeda Highbank"
747 imply OF_HAS_PRIOR_STAGE
749 config ARCH_INTEGRATOR
750 bool "ARM Ltd. Integrator family"
753 select GPIO_EXTRA_HEADER
758 bool "Qualcomm IPQ40xx SoCs"
764 select GPIO_EXTRA_HEADER
770 select CLK_QCOM_IPQ4019
771 select PINCTRL_QCOM_IPQ4019
780 select SPL_BOARD_INIT if SPL
782 select SYS_ARCH_TIMER
783 select SYS_THUMB_BUILD
790 imply TI_KEYSTONE_SERDES
793 bool "Texas Instruments' K3 Architecture"
798 select FIT_SIGNATURE if ARM64
799 imply TI_SECURE_DEVICE
801 config ARCH_OMAP2PLUS
804 select GPIO_EXTRA_HEADER
805 select SPL_BOARD_INIT if SPL
806 select SPL_STACK_R if SPL
808 imply TI_SYSC if DM && OF_CONTROL
810 imply SPL_SEPARATE_BSS
814 select GPIO_EXTRA_HEADER
815 imply DISTRO_DEFAULTS
818 Support for the Meson SoC family developed by Amlogic Inc.,
819 targeted at media players and tablet computers. We currently
820 support the S905 (GXBaby) 64-bit SoC.
825 select GPIO_EXTRA_HEADER
828 select SPL_LIBCOMMON_SUPPORT if SPL
829 select SPL_LIBGENERIC_SUPPORT if SPL
830 select SPL_OF_CONTROL if SPL
833 Support for the MediaTek SoCs family developed by MediaTek Inc.
834 Please refer to doc/README.mediatek for more information.
837 bool "NXP LPC32xx platform"
842 select GPIO_EXTRA_HEADER
848 bool "NXP i.MX8 platform"
850 select SYS_FSL_HAS_SEC
851 select SYS_FSL_SEC_COMPAT_4
852 select SYS_FSL_SEC_LE
855 select GPIO_EXTRA_HEADER
858 select ENABLE_ARM_SOC_BOOT0_HOOK
861 bool "NXP i.MX8M platform"
863 select GPIO_EXTRA_HEADER
865 select SYS_FSL_HAS_SEC
866 select SYS_FSL_SEC_COMPAT_4
867 select SYS_FSL_SEC_LE
870 select DM_EVENT if CLK
875 bool "NXP i.MX8ULP platform"
882 select GPIO_EXTRA_HEADER
888 bool "NXP i.MX9 platform"
894 select GPIO_EXTRA_HEADER
900 bool "NXP i.MXRT platform"
904 select GPIO_EXTRA_HEADER
910 bool "NXP i.MX23 family"
912 select GPIO_EXTRA_HEADER
917 bool "NXP i.MX28 family"
919 select GPIO_EXTRA_HEADER
924 bool "NXP i.MX31 family"
926 select GPIO_EXTRA_HEADER
931 select BOARD_POSTCLK_INIT
933 select GPIO_EXTRA_HEADER
935 select SYS_FSL_HAS_SEC
936 select SYS_FSL_SEC_COMPAT_4
937 select SYS_FSL_SEC_LE
938 select ROM_UNIFIED_SECTIONS
940 imply SYS_THUMB_BUILD
944 select ARCH_MISC_INIT
946 select GPIO_EXTRA_HEADER
949 select SYS_FSL_HAS_SEC
950 select SYS_FSL_SEC_COMPAT_4
951 select SYS_FSL_SEC_LE
952 imply BOARD_EARLY_INIT_F
954 imply SYS_THUMB_BUILD
958 select BOARD_POSTCLK_INIT
960 select GPIO_EXTRA_HEADER
963 select SYS_FSL_HAS_SEC
964 select SYS_FSL_SEC_COMPAT_4
965 select SYS_FSL_SEC_LE
966 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
968 imply SYS_THUMB_BUILD
969 imply SPL_SEPARATE_BSS
973 select BOARD_EARLY_INIT_F
975 select GPIO_EXTRA_HEADER
980 bool "Nexell S5P4418/S5P6818 SoC"
981 select ENABLE_ARM_SOC_BOOT0_HOOK
983 select GPIO_EXTRA_HEADER
986 bool "Support Nuvoton SoCs"
1007 select LINUX_KERNEL_IMAGE_HEADER
1009 select OF_BOARD_SETUP
1014 select POSITION_INDEPENDENT
1020 select SYSRESET_WATCHDOG
1021 select SYSRESET_WATCHDOG_AUTO
1025 imply DISTRO_DEFAULTS
1026 imply OF_HAS_PRIOR_STAGE
1029 bool "Actions Semi OWL SoCs"
1032 select GPIO_EXTRA_HEADER
1037 select SYS_RELOC_GD_ENV_ADDR
1041 bool "QEMU Virtual Platform"
1050 imply OF_HAS_PRIOR_STAGE
1053 imply SYS_WHITE_ON_BLACK
1054 imply SYS_CONSOLE_IS_IN_ENV
1055 imply PRE_CONSOLE_BUFFER
1063 bool "Renesas ARM SoCs"
1066 select GPIO_EXTRA_HEADER
1068 imply BOARD_EARLY_INIT_F
1071 imply SYS_THUMB_BUILD
1072 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1074 config ARCH_SNAPDRAGON
1075 bool "Qualcomm Snapdragon SoCs"
1082 select GPIO_EXTRA_HEADER
1088 select BOARD_LATE_INIT
1090 select SAVE_PREV_BL_FDT_ADDR
1091 select LINUX_KERNEL_IMAGE_HEADER
1095 bool "Altera SOCFPGA family"
1096 select ARCH_EARLY_INIT_R
1097 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1098 select ARM64 if TARGET_SOCFPGA_SOC64
1099 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1103 select GPIO_EXTRA_HEADER
1104 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1106 select SPL_DM_RESET if DM_RESET
1107 select SPL_DM_SERIAL
1108 select SPL_LIBCOMMON_SUPPORT
1109 select SPL_LIBGENERIC_SUPPORT
1110 select SPL_OF_CONTROL
1111 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1112 select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
1113 select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
1119 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1121 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1122 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
1123 TARGET_SOCFPGA_SOC64
1134 imply SPL_DM_SPI_FLASH
1135 imply SPL_LIBDISK_SUPPORT
1137 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1138 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1139 imply SPL_SPI_FLASH_SUPPORT
1144 bool "Support sunxi (Allwinner) SoCs"
1147 select CMD_MMC if MMC
1148 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1152 select DM_I2C if I2C
1153 select DM_SPI if SPI
1154 select DM_SPI_FLASH if SPI && MTD
1156 select DM_MMC if MMC
1158 select OF_BOARD_SETUP
1162 select SPECIFY_CONSOLE_INDEX
1163 select SPL_SEPARATE_BSS if SPL
1164 select SPL_STACK_R if SPL
1165 select SPL_SYS_MALLOC_SIMPLE if SPL
1166 select SPL_SYS_THUMB_BUILD if SPL && !ARM64
1169 select SYS_THUMB_BUILD if !ARM64
1170 select USB if DISTRO_DEFAULTS
1171 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1172 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1173 select SPL_USE_TINY_PRINTF if SPL
1175 select SYS_RELOC_GD_ENV_ADDR
1176 imply BOARD_LATE_INIT
1179 imply CMD_UBI if MTD_RAW_NAND
1180 imply DISTRO_DEFAULTS
1182 imply DM_REGULATOR_FIXED
1185 imply OF_LIBFDT_OVERLAY
1186 imply PRE_CONSOLE_BUFFER
1188 imply SPL_LIBCOMMON_SUPPORT
1189 imply SPL_LIBGENERIC_SUPPORT
1190 imply SPL_MMC if MMC
1194 imply SYSRESET_WATCHDOG
1195 imply SYSRESET_WATCHDOG_AUTO
1200 bool "ST-Ericsson U8500 Series"
1204 select DM_MMC if MMC
1206 select DM_USB_GADGET if DM_USB
1210 imply AB8500_USB_PHY
1211 imply ARM_PL180_MMCI
1216 imply NOMADIK_MTU_TIMER
1221 imply SYS_THUMB_BUILD
1222 imply SYSRESET_SYSCON
1225 bool "Support Xilinx Versal Platform"
1229 select DM_MMC if MMC
1234 imply BOARD_LATE_INIT
1235 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1237 config ARCH_VERSAL_NET
1238 bool "Support Xilinx Versal NET Platform"
1242 select DM_MMC if MMC
1245 imply BOARD_LATE_INIT
1246 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1249 bool "Freescale Vybrid"
1251 select GPIO_EXTRA_HEADER
1252 select IOMUX_SHARE_CONF_REG
1254 select SYS_FSL_ERRATUM_ESDHC111
1259 bool "Xilinx Zynq based platform"
1260 select ARM_TWD_TIMER
1261 select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
1265 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1267 select DM_MMC if MMC
1274 select SPL_BOARD_INIT if SPL
1275 select SPL_CLK if SPL
1276 select SPL_DM if SPL
1277 select SPL_DM_SPI if SPL
1278 select SPL_DM_SPI_FLASH if SPL
1279 select SPL_OF_CONTROL if SPL
1280 select SPL_SEPARATE_BSS if SPL
1281 select SPL_TIMER if SPL
1284 imply BOARD_LATE_INIT
1288 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1291 config ARCH_ZYNQMP_R5
1292 bool "Xilinx ZynqMP R5 based platform"
1296 select DM_MMC if MMC
1303 bool "Xilinx ZynqMP based platform"
1307 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1309 select DM_MMC if MMC
1312 select DM_SPI if SPI
1313 select DM_SPI_FLASH if DM_SPI
1317 select SPL_BOARD_INIT if SPL
1318 select SPL_CLK if SPL
1319 select SPL_DM if SPL
1320 select SPL_DM_SPI if SPI && SPL_DM
1321 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1322 select SPL_DM_MAILBOX if SPL
1323 imply SPL_FIRMWARE if SPL
1324 select SPL_SEPARATE_BSS if SPL
1326 imply ZYNQMP_IPI if DM_MAILBOX
1328 imply BOARD_LATE_INIT
1330 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1334 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1338 select GPIO_EXTRA_HEADER
1339 imply DISTRO_DEFAULTS
1341 imply SPL_TIMER if SPL
1343 config ARCH_VEXPRESS64
1344 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1352 select MTD_NOR_FLASH if MTD
1353 select FLASH_CFI_DRIVER if MTD
1354 select ENV_IS_IN_FLASH if MTD
1355 imply DISTRO_DEFAULTS
1357 config TARGET_CORSTONE1000
1358 bool "Support Corstone1000 Platform"
1363 config TARGET_TOTAL_COMPUTE
1364 bool "Support Total Compute Platform"
1372 config TARGET_LS2080A_EMU
1373 bool "Support ls2080a_emu"
1376 select ARMV8_MULTIENTRY
1377 select FSL_DDR_SYNC_REFRESH
1378 select GPIO_EXTRA_HEADER
1380 Support for Freescale LS2080A_EMU platform.
1381 The LS2080A Development System (EMULATOR) is a pre-silicon
1382 development platform that supports the QorIQ LS2080A
1383 Layerscape Architecture processor.
1385 config TARGET_LS1088AQDS
1386 bool "Support ls1088aqds"
1389 select ARMV8_MULTIENTRY
1390 select ARCH_SUPPORT_TFABOOT
1391 select BOARD_LATE_INIT
1392 select GPIO_EXTRA_HEADER
1394 select FSL_DDR_INTERACTIVE if !SD_BOOT
1396 Support for NXP LS1088AQDS platform.
1397 The LS1088A Development System (QDS) is a high-performance
1398 development platform that supports the QorIQ LS1088A
1399 Layerscape Architecture processor.
1401 config TARGET_LS2080AQDS
1402 bool "Support ls2080aqds"
1405 select ARMV8_MULTIENTRY
1406 select ARCH_SUPPORT_TFABOOT
1407 select BOARD_LATE_INIT
1408 select GPIO_EXTRA_HEADER
1413 select FSL_DDR_INTERACTIVE if !SPL
1415 Support for Freescale LS2080AQDS platform.
1416 The LS2080A Development System (QDS) is a high-performance
1417 development platform that supports the QorIQ LS2080A
1418 Layerscape Architecture processor.
1420 config TARGET_LS2080ARDB
1421 bool "Support ls2080ardb"
1424 select ARMV8_MULTIENTRY
1425 select ARCH_SUPPORT_TFABOOT
1426 select BOARD_LATE_INIT
1429 select FSL_DDR_INTERACTIVE if !SPL
1430 select GPIO_EXTRA_HEADER
1434 Support for Freescale LS2080ARDB platform.
1435 The LS2080A Reference design board (RDB) is a high-performance
1436 development platform that supports the QorIQ LS2080A
1437 Layerscape Architecture processor.
1439 config TARGET_LS2081ARDB
1440 bool "Support ls2081ardb"
1443 select ARMV8_MULTIENTRY
1444 select BOARD_LATE_INIT
1445 select GPIO_EXTRA_HEADER
1448 Support for Freescale LS2081ARDB platform.
1449 The LS2081A Reference design board (RDB) is a high-performance
1450 development platform that supports the QorIQ LS2081A/LS2041A
1451 Layerscape Architecture processor.
1453 config TARGET_LX2160ARDB
1454 bool "Support lx2160ardb"
1457 select ARMV8_MULTIENTRY
1458 select ARCH_SUPPORT_TFABOOT
1459 select BOARD_LATE_INIT
1460 select GPIO_EXTRA_HEADER
1462 Support for NXP LX2160ARDB platform.
1463 The lx2160ardb (LX2160A Reference design board (RDB)
1464 is a high-performance development platform that supports the
1465 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1467 config TARGET_LX2160AQDS
1468 bool "Support lx2160aqds"
1471 select ARMV8_MULTIENTRY
1472 select ARCH_SUPPORT_TFABOOT
1473 select BOARD_LATE_INIT
1474 select GPIO_EXTRA_HEADER
1476 Support for NXP LX2160AQDS platform.
1477 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1478 is a high-performance development platform that supports the
1479 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1481 config TARGET_LX2162AQDS
1482 bool "Support lx2162aqds"
1484 select ARCH_MISC_INIT
1486 select ARMV8_MULTIENTRY
1487 select ARCH_SUPPORT_TFABOOT
1488 select BOARD_LATE_INIT
1489 select GPIO_EXTRA_HEADER
1491 Support for NXP LX2162AQDS platform.
1492 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1495 bool "Support HiKey 96boards Consumer Edition Platform"
1500 select GPIO_EXTRA_HEADER
1503 select SPECIFY_CONSOLE_INDEX
1506 Support for HiKey 96boards platform. It features a HI6220
1507 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1509 config TARGET_HIKEY960
1510 bool "Support HiKey960 96boards Consumer Edition Platform"
1514 select GPIO_EXTRA_HEADER
1519 Support for HiKey960 96boards platform. It features a HI3660
1520 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1522 config TARGET_POPLAR
1523 bool "Support Poplar 96boards Enterprise Edition Platform"
1527 select GPIO_EXTRA_HEADER
1532 Support for Poplar 96boards EE platform. It features a HI3798cv200
1533 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1534 making it capable of running any commercial set-top solution based on
1537 config TARGET_LS1012AQDS
1538 bool "Support ls1012aqds"
1541 select ARCH_SUPPORT_TFABOOT
1542 select BOARD_LATE_INIT
1543 select GPIO_EXTRA_HEADER
1545 Support for Freescale LS1012AQDS platform.
1546 The LS1012A Development System (QDS) is a high-performance
1547 development platform that supports the QorIQ LS1012A
1548 Layerscape Architecture processor.
1550 config TARGET_LS1012ARDB
1551 bool "Support ls1012ardb"
1554 select ARCH_SUPPORT_TFABOOT
1555 select BOARD_LATE_INIT
1556 select GPIO_EXTRA_HEADER
1560 Support for Freescale LS1012ARDB platform.
1561 The LS1012A Reference design board (RDB) is a high-performance
1562 development platform that supports the QorIQ LS1012A
1563 Layerscape Architecture processor.
1565 config TARGET_LS1012A2G5RDB
1566 bool "Support ls1012a2g5rdb"
1569 select ARCH_SUPPORT_TFABOOT
1570 select BOARD_LATE_INIT
1571 select GPIO_EXTRA_HEADER
1574 Support for Freescale LS1012A2G5RDB platform.
1575 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1576 development platform that supports the QorIQ LS1012A
1577 Layerscape Architecture processor.
1579 config TARGET_LS1012AFRWY
1580 bool "Support ls1012afrwy"
1583 select ARCH_SUPPORT_TFABOOT
1584 select BOARD_LATE_INIT
1585 select GPIO_EXTRA_HEADER
1589 Support for Freescale LS1012AFRWY platform.
1590 The LS1012A FRWY board (FRWY) is a high-performance
1591 development platform that supports the QorIQ LS1012A
1592 Layerscape Architecture processor.
1594 config TARGET_LS1012AFRDM
1595 bool "Support ls1012afrdm"
1598 select ARCH_SUPPORT_TFABOOT
1599 select GPIO_EXTRA_HEADER
1601 Support for Freescale LS1012AFRDM platform.
1602 The LS1012A Freedom board (FRDM) is a high-performance
1603 development platform that supports the QorIQ LS1012A
1604 Layerscape Architecture processor.
1606 config TARGET_LS1028AQDS
1607 bool "Support ls1028aqds"
1610 select ARMV8_MULTIENTRY
1611 select ARCH_SUPPORT_TFABOOT
1612 select BOARD_LATE_INIT
1613 select GPIO_EXTRA_HEADER
1615 Support for Freescale LS1028AQDS platform
1616 The LS1028A Development System (QDS) is a high-performance
1617 development platform that supports the QorIQ LS1028A
1618 Layerscape Architecture processor.
1620 config TARGET_LS1028ARDB
1621 bool "Support ls1028ardb"
1624 select ARMV8_MULTIENTRY
1625 select ARCH_SUPPORT_TFABOOT
1626 select BOARD_LATE_INIT
1627 select GPIO_EXTRA_HEADER
1629 Support for Freescale LS1028ARDB platform
1630 The LS1028A Development System (RDB) is a high-performance
1631 development platform that supports the QorIQ LS1028A
1632 Layerscape Architecture processor.
1634 config TARGET_LS1088ARDB
1635 bool "Support ls1088ardb"
1638 select ARMV8_MULTIENTRY
1639 select ARCH_SUPPORT_TFABOOT
1640 select BOARD_LATE_INIT
1642 select FSL_DDR_INTERACTIVE if !SD_BOOT
1643 select GPIO_EXTRA_HEADER
1645 Support for NXP LS1088ARDB platform.
1646 The LS1088A Reference design board (RDB) is a high-performance
1647 development platform that supports the QorIQ LS1088A
1648 Layerscape Architecture processor.
1650 config TARGET_LS1021AQDS
1651 bool "Support ls1021aqds"
1653 select ARCH_SUPPORT_PSCI
1654 select BOARD_EARLY_INIT_F
1655 select BOARD_LATE_INIT
1657 select CPU_V7_HAS_NONSEC
1658 select CPU_V7_HAS_VIRT
1659 select LS1_DEEP_SLEEP
1660 select PEN_ADDR_BIG_ENDIAN
1663 select FSL_DDR_INTERACTIVE
1664 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1665 select GPIO_EXTRA_HEADER
1666 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1669 config TARGET_LS1021ATWR
1670 bool "Support ls1021atwr"
1672 select ARCH_SUPPORT_PSCI
1673 select BOARD_EARLY_INIT_F
1674 select BOARD_LATE_INIT
1676 select CPU_V7_HAS_NONSEC
1677 select CPU_V7_HAS_VIRT
1678 select LS1_DEEP_SLEEP
1679 select PEN_ADDR_BIG_ENDIAN
1681 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1682 select GPIO_EXTRA_HEADER
1685 config TARGET_PG_WCOM_SELI8
1686 bool "Support Hitachi-Powergrids SELI8 service unit card"
1688 select ARCH_SUPPORT_PSCI
1689 select BOARD_EARLY_INIT_F
1690 select BOARD_LATE_INIT
1692 select CPU_V7_HAS_NONSEC
1693 select CPU_V7_HAS_VIRT
1695 select FSL_DDR_INTERACTIVE
1696 select GPIO_EXTRA_HEADER
1700 Support for Hitachi-Powergrids SELI8 service unit card.
1701 SELI8 is a QorIQ LS1021a based service unit card used
1702 in XMC20 and FOX615 product families.
1704 config TARGET_PG_WCOM_EXPU1
1705 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1707 select ARCH_SUPPORT_PSCI
1708 select BOARD_EARLY_INIT_F
1709 select BOARD_LATE_INIT
1711 select CPU_V7_HAS_NONSEC
1712 select CPU_V7_HAS_VIRT
1714 select FSL_DDR_INTERACTIVE
1718 Support for Hitachi-Powergrids EXPU1 service unit card.
1719 EXPU1 is a QorIQ LS1021a based service unit card used
1720 in XMC20 and FOX615 product families.
1722 config TARGET_LS1021ATSN
1723 bool "Support ls1021atsn"
1725 select ARCH_SUPPORT_PSCI
1726 select BOARD_EARLY_INIT_F
1727 select BOARD_LATE_INIT
1729 select CPU_V7_HAS_NONSEC
1730 select CPU_V7_HAS_VIRT
1731 select LS1_DEEP_SLEEP
1733 select GPIO_EXTRA_HEADER
1736 config TARGET_LS1021AIOT
1737 bool "Support ls1021aiot"
1739 select ARCH_SUPPORT_PSCI
1740 select BOARD_LATE_INIT
1742 select CPU_V7_HAS_NONSEC
1743 select CPU_V7_HAS_VIRT
1744 select PEN_ADDR_BIG_ENDIAN
1746 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1747 select GPIO_EXTRA_HEADER
1750 Support for Freescale LS1021AIOT platform.
1751 The LS1021A Freescale board (IOT) is a high-performance
1752 development platform that supports the QorIQ LS1021A
1753 Layerscape Architecture processor.
1755 config TARGET_LS1043AQDS
1756 bool "Support ls1043aqds"
1759 select ARMV8_MULTIENTRY
1760 select ARCH_SUPPORT_TFABOOT
1761 select BOARD_EARLY_INIT_F
1762 select BOARD_LATE_INIT
1764 select FSL_DDR_INTERACTIVE if !SPL
1765 select FSL_DSPI if !SPL_NO_DSPI
1766 select DM_SPI_FLASH if FSL_DSPI
1767 select GPIO_EXTRA_HEADER
1771 Support for Freescale LS1043AQDS platform.
1773 config TARGET_LS1043ARDB
1774 bool "Support ls1043ardb"
1777 select ARMV8_MULTIENTRY
1778 select ARCH_SUPPORT_TFABOOT
1779 select BOARD_EARLY_INIT_F
1780 select BOARD_LATE_INIT
1782 select FSL_DSPI if !SPL_NO_DSPI
1783 select DM_SPI_FLASH if FSL_DSPI
1784 select GPIO_EXTRA_HEADER
1786 Support for Freescale LS1043ARDB platform.
1788 config TARGET_LS1046AQDS
1789 bool "Support ls1046aqds"
1792 select ARMV8_MULTIENTRY
1793 select ARCH_SUPPORT_TFABOOT
1794 select BOARD_EARLY_INIT_F
1795 select BOARD_LATE_INIT
1796 select DM_SPI_FLASH if DM_SPI
1798 select FSL_DDR_BIST if !SPL
1799 select FSL_DDR_INTERACTIVE if !SPL
1800 select FSL_DDR_INTERACTIVE if !SPL
1801 select GPIO_EXTRA_HEADER
1804 Support for Freescale LS1046AQDS platform.
1805 The LS1046A Development System (QDS) is a high-performance
1806 development platform that supports the QorIQ LS1046A
1807 Layerscape Architecture processor.
1809 config TARGET_LS1046ARDB
1810 bool "Support ls1046ardb"
1813 select ARMV8_MULTIENTRY
1814 select ARCH_SUPPORT_TFABOOT
1815 select BOARD_EARLY_INIT_F
1816 select BOARD_LATE_INIT
1817 select DM_SPI_FLASH if DM_SPI
1818 select POWER_MC34VR500
1821 select FSL_DDR_INTERACTIVE if !SPL
1822 select GPIO_EXTRA_HEADER
1825 Support for Freescale LS1046ARDB platform.
1826 The LS1046A Reference Design Board (RDB) is a high-performance
1827 development platform that supports the QorIQ LS1046A
1828 Layerscape Architecture processor.
1830 config TARGET_LS1046AFRWY
1831 bool "Support ls1046afrwy"
1834 select ARMV8_MULTIENTRY
1835 select ARCH_SUPPORT_TFABOOT
1836 select BOARD_EARLY_INIT_F
1837 select BOARD_LATE_INIT
1838 select DM_SPI_FLASH if DM_SPI
1839 select GPIO_EXTRA_HEADER
1842 Support for Freescale LS1046AFRWY platform.
1843 The LS1046A Freeway Board (FRWY) is a high-performance
1844 development platform that supports the QorIQ LS1046A
1845 Layerscape Architecture processor.
1851 select ARMV8_MULTIENTRY
1867 select GPIO_EXTRA_HEADER
1868 select SPL_DM if SPL
1869 select SPL_DM_SPI if SPL
1870 select SPL_DM_SPI_FLASH if SPL
1871 select SPL_DM_I2C if SPL
1872 select SPL_DM_MMC if SPL
1873 select SPL_DM_SERIAL if SPL
1875 Support for Kontron SMARC-sAL28 board.
1878 bool "Support ten64"
1880 select ARCH_MISC_INIT
1882 select ARMV8_MULTIENTRY
1883 select ARCH_SUPPORT_TFABOOT
1884 select BOARD_LATE_INIT
1886 select FSL_DDR_INTERACTIVE if !SD_BOOT
1887 select GPIO_EXTRA_HEADER
1889 Support for Traverse Technologies Ten64 board, based
1892 config ARCH_UNIPHIER
1893 bool "Socionext UniPhier SoCs"
1894 select BOARD_LATE_INIT
1902 select OF_BOARD_SETUP
1906 select SPL_BOARD_INIT if SPL
1907 select SPL_DM if SPL
1908 select SPL_LIBCOMMON_SUPPORT if SPL
1909 select SPL_LIBGENERIC_SUPPORT if SPL
1910 select SPL_OF_CONTROL if SPL
1911 select SPL_PINCTRL if SPL
1914 imply DISTRO_DEFAULTS
1917 Support for UniPhier SoC family developed by Socionext Inc.
1918 (formerly, System LSI Business Division of Panasonic Corporation)
1920 config ARCH_SYNQUACER
1921 bool "Socionext SynQuacer SoCs"
1927 select SYSRESET_PSCI
1930 Support for SynQuacer SoC family developed by Socionext Inc.
1931 This SoC is used on 96boards EE DeveloperBox.
1934 bool "Support STMicroelectronics STM32 MCU with cortex M"
1941 bool "Support STMicroelectronics SoCs"
1950 Support for STMicroelectronics STiH407/10 SoC family.
1951 This SoC is used on Linaro 96Board STiH410-B2260
1954 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1955 select ARCH_MISC_INIT
1956 select ARCH_SUPPORT_TFABOOT
1957 select BOARD_LATE_INIT
1966 select OF_SYSTEM_SETUP
1971 select SYS_THUMB_BUILD if !ARM64
1975 imply OF_LIBFDT_OVERLAY
1976 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1980 Support for STM32MP SoC family developed by STMicroelectronics,
1981 MPUs based on ARM cortex A core
1982 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1983 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1985 SPL is the unsecure FSBL for the basic boot chain.
1987 config ARCH_ROCKCHIP
1988 bool "Support Rockchip SoCs"
1990 select BINMAN if SPL_OPTEE || SPL
2000 select DM_USB_GADGET if USB_DWC3_GADGET
2001 select ENABLE_ARM_SOC_BOOT0_HOOK
2005 select SPL_DM if SPL
2006 select SPL_DM_SPI if SPL
2007 select SPL_DM_SPI_FLASH if SPL
2009 select SYS_THUMB_BUILD if !ARM64
2012 imply DEBUG_UART_BOARD_INIT
2013 imply BOOTSTD_DEFAULTS
2015 imply SARADC_ROCKCHIP
2017 imply SPL_SYS_MALLOC_SIMPLE
2020 imply USB_FUNCTION_FASTBOOT
2022 config ARCH_OCTEONTX
2023 bool "Support OcteonTX SoCs"
2026 select GPIO_EXTRA_HEADER
2030 select BOARD_LATE_INIT
2031 select SYS_CACHE_SHIFT_7
2032 select SYS_PCI_64BIT if PCI
2033 imply OF_HAS_PRIOR_STAGE
2035 config ARCH_OCTEONTX2
2036 bool "Support OcteonTX2 SoCs"
2039 select GPIO_EXTRA_HEADER
2043 select BOARD_LATE_INIT
2044 select SYS_CACHE_SHIFT_7
2045 select SYS_PCI_64BIT if PCI
2046 imply OF_HAS_PRIOR_STAGE
2048 config TARGET_THUNDERX_88XX
2049 bool "Support ThunderX 88xx"
2051 select GPIO_EXTRA_HEADER
2054 select SYS_CACHE_SHIFT_7
2057 bool "Support Aspeed SoCs"
2062 config TARGET_DURIAN
2063 bool "Support Phytium Durian Platform"
2065 select GPIO_EXTRA_HEADER
2067 Support for durian platform.
2068 It has 2GB Sdram, uart and pcie.
2070 config TARGET_POMELO
2071 bool "Support Phytium Pomelo Platform"
2084 Support for pomelo platform.
2085 It has 8GB Sdram, uart and pcie.
2087 config TARGET_PE2201
2088 bool "Support Phytium PE2201 Platform"
2091 Support for pe2201 platform.It has 2GB Sdram, uart and pcie.
2093 config TARGET_PRESIDIO_ASIC
2094 bool "Support Cortina Presidio ASIC Platform"
2098 config TARGET_XENGUEST_ARM64
2099 bool "Xen guest ARM64"
2103 select LINUX_KERNEL_IMAGE_HEADER
2105 imply OF_HAS_PRIOR_STAGE
2108 bool "Support HPE GXP SoCs"
2115 config SUPPORT_PASSING_ATAGS
2116 bool "Support pre-devicetree ATAG-based booting"
2118 imply SETUP_MEMORY_TAGS
2120 Support for booting older Linux kernels, using ATAGs rather than
2121 passing a devicetree. This is option is rarely used, and the
2122 semantics are defined at
2123 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2125 config SETUP_MEMORY_TAGS
2126 bool "Pass memory size information via ATAG"
2127 depends on SUPPORT_PASSING_ATAGS
2130 bool "Pass Linux kernel cmdline via ATAG"
2131 depends on SUPPORT_PASSING_ATAGS
2134 bool "Pass initrd starting point and size via ATAG"
2135 depends on SUPPORT_PASSING_ATAGS
2138 bool "Pass system revision via ATAG"
2139 depends on SUPPORT_PASSING_ATAGS
2142 bool "Pass system serial number via ATAG"
2143 depends on SUPPORT_PASSING_ATAGS
2145 config STATIC_MACH_TYPE
2146 bool "Statically define the Machine ID number"
2147 default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2149 When booting via ATAGs, enable this option if we know the correct
2150 machine ID number to use at compile time. Some systems will be
2151 passed the number dynamically by whatever loads U-Boot.
2154 int "Machine ID number"
2155 depends on STATIC_MACH_TYPE
2156 default 527 if TARGET_DS109
2157 default 3036 if TARGET_DS414
2158 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2160 When booting via ATAGs, the machine type must be passed as a number.
2161 For the full list see https://www.arm.linux.org.uk/developer/machines
2163 config ARCH_SUPPORT_TFABOOT
2167 bool "Support for booting from TF-A"
2168 depends on ARCH_SUPPORT_TFABOOT
2170 Some platforms support the setup of secure registers (for instance
2171 for CPU errata handling) or provide secure services like PSCI.
2172 Those services could also be provided by other firmware parts
2173 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2174 does not need to (and cannot) execute this code.
2175 Enabling this option will make a U-Boot binary that is relying
2176 on other firmware layers to provide secure functionality.
2178 config TI_SECURE_DEVICE
2179 bool "HS Device Type Support"
2180 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2182 If a high secure (HS) device type is being used, this config
2183 must be set. This option impacts various aspects of the
2184 build system (to create signed boot images that can be
2185 authenticated) and the code. See the doc/README.ti-secure
2186 file for further details.
2188 config SYS_KWD_CONFIG
2189 string "kwbimage config file path"
2190 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2191 default "arch/arm/mach-mvebu/kwbimage.cfg"
2193 Path within the source directory to the kwbimage.cfg file to use
2194 when packaging the U-Boot image for use.
2196 source "arch/arm/mach-apple/Kconfig"
2198 source "arch/arm/mach-aspeed/Kconfig"
2200 source "arch/arm/mach-at91/Kconfig"
2202 source "arch/arm/mach-bcm283x/Kconfig"
2204 source "arch/arm/mach-bcmbca/Kconfig"
2206 source "arch/arm/mach-bcmstb/Kconfig"
2208 source "arch/arm/mach-davinci/Kconfig"
2210 source "arch/arm/mach-exynos/Kconfig"
2212 source "arch/arm/mach-hpe/gxp/Kconfig"
2214 source "arch/arm/mach-highbank/Kconfig"
2216 source "arch/arm/mach-histb/Kconfig"
2218 source "arch/arm/mach-integrator/Kconfig"
2220 source "arch/arm/mach-ipq40xx/Kconfig"
2222 source "arch/arm/mach-k3/Kconfig"
2224 source "arch/arm/mach-keystone/Kconfig"
2226 source "arch/arm/mach-kirkwood/Kconfig"
2228 source "arch/arm/mach-lpc32xx/Kconfig"
2230 source "arch/arm/mach-mvebu/Kconfig"
2232 source "arch/arm/mach-octeontx/Kconfig"
2234 source "arch/arm/mach-octeontx2/Kconfig"
2236 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2238 source "arch/arm/mach-imx/mx3/Kconfig"
2240 source "arch/arm/mach-imx/mx5/Kconfig"
2242 source "arch/arm/mach-imx/mx6/Kconfig"
2244 source "arch/arm/mach-imx/mx7/Kconfig"
2246 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2248 source "arch/arm/mach-imx/imx8/Kconfig"
2250 source "arch/arm/mach-imx/imx8m/Kconfig"
2252 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2254 source "arch/arm/mach-imx/imx9/Kconfig"
2256 source "arch/arm/mach-imx/imxrt/Kconfig"
2258 source "arch/arm/mach-imx/mxs/Kconfig"
2260 source "arch/arm/mach-omap2/Kconfig"
2262 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2264 source "arch/arm/mach-orion5x/Kconfig"
2266 source "arch/arm/mach-owl/Kconfig"
2268 source "arch/arm/mach-renesas/Kconfig"
2270 source "arch/arm/mach-meson/Kconfig"
2272 source "arch/arm/mach-mediatek/Kconfig"
2274 source "arch/arm/mach-qemu/Kconfig"
2276 source "arch/arm/mach-rockchip/Kconfig"
2278 source "arch/arm/mach-s5pc1xx/Kconfig"
2280 source "arch/arm/mach-snapdragon/Kconfig"
2282 source "arch/arm/mach-socfpga/Kconfig"
2284 source "arch/arm/mach-sti/Kconfig"
2286 source "arch/arm/mach-stm32/Kconfig"
2288 source "arch/arm/mach-stm32mp/Kconfig"
2290 source "arch/arm/mach-sunxi/Kconfig"
2292 source "arch/arm/mach-tegra/Kconfig"
2294 source "arch/arm/mach-u8500/Kconfig"
2296 source "arch/arm/mach-uniphier/Kconfig"
2298 source "arch/arm/cpu/armv7/vf610/Kconfig"
2300 source "arch/arm/mach-zynq/Kconfig"
2302 source "arch/arm/mach-zynqmp/Kconfig"
2304 source "arch/arm/mach-versal/Kconfig"
2306 source "arch/arm/mach-versal-net/Kconfig"
2308 source "arch/arm/mach-zynqmp-r5/Kconfig"
2310 source "arch/arm/cpu/armv7/Kconfig"
2312 source "arch/arm/cpu/armv8/Kconfig"
2314 source "arch/arm/mach-imx/Kconfig"
2316 source "arch/arm/mach-nexell/Kconfig"
2318 source "arch/arm/mach-npcm/Kconfig"
2320 source "board/armltd/total_compute/Kconfig"
2321 source "board/armltd/corstone1000/Kconfig"
2322 source "board/bosch/shc/Kconfig"
2323 source "board/bosch/guardian/Kconfig"
2324 source "board/Marvell/octeontx/Kconfig"
2325 source "board/Marvell/octeontx2/Kconfig"
2326 source "board/armltd/vexpress/Kconfig"
2327 source "board/armltd/vexpress64/Kconfig"
2328 source "board/cortina/presidio-asic/Kconfig"
2329 source "board/broadcom/bcmns/Kconfig"
2330 source "board/broadcom/bcmns3/Kconfig"
2331 source "board/cavium/thunderx/Kconfig"
2332 source "board/eets/pdu001/Kconfig"
2333 source "board/emulation/qemu-arm/Kconfig"
2334 source "board/freescale/ls2080aqds/Kconfig"
2335 source "board/freescale/ls2080ardb/Kconfig"
2336 source "board/freescale/ls1088a/Kconfig"
2337 source "board/freescale/ls1028a/Kconfig"
2338 source "board/freescale/ls1021aqds/Kconfig"
2339 source "board/freescale/ls1043aqds/Kconfig"
2340 source "board/freescale/ls1021atwr/Kconfig"
2341 source "board/freescale/ls1021atsn/Kconfig"
2342 source "board/freescale/ls1021aiot/Kconfig"
2343 source "board/freescale/ls1046aqds/Kconfig"
2344 source "board/freescale/ls1043ardb/Kconfig"
2345 source "board/freescale/ls1046ardb/Kconfig"
2346 source "board/freescale/ls1046afrwy/Kconfig"
2347 source "board/freescale/ls1012aqds/Kconfig"
2348 source "board/freescale/ls1012ardb/Kconfig"
2349 source "board/freescale/ls1012afrdm/Kconfig"
2350 source "board/freescale/lx2160a/Kconfig"
2351 source "board/grinn/chiliboard/Kconfig"
2352 source "board/hisilicon/hikey/Kconfig"
2353 source "board/hisilicon/hikey960/Kconfig"
2354 source "board/hisilicon/poplar/Kconfig"
2355 source "board/isee/igep003x/Kconfig"
2356 source "board/kontron/sl28/Kconfig"
2357 source "board/myir/mys_6ulx/Kconfig"
2358 source "board/samsung/common/Kconfig"
2359 source "board/siemens/common/Kconfig"
2360 source "board/seeed/npi_imx6ull/Kconfig"
2361 source "board/socionext/developerbox/Kconfig"
2362 source "board/tcl/sl50/Kconfig"
2363 source "board/traverse/ten64/Kconfig"
2364 source "board/variscite/dart_6ul/Kconfig"
2365 source "board/vscom/baltos/Kconfig"
2366 source "board/phytium/durian/Kconfig"
2367 source "board/phytium/pomelo/Kconfig"
2368 source "board/phytium/pe2201/Kconfig"
2369 source "board/xen/xenguest_arm64/Kconfig"
2371 source "arch/arm/Kconfig.debug"