arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_32BIT_OFF_T
   6         select ARCH_HAS_BINFMT_FLAT
   7         select ARCH_HAS_DEBUG_VIRTUAL if MMU
   8         select ARCH_HAS_DEVMEM_IS_ALLOWED
   9         select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
  10         select ARCH_HAS_ELF_RANDOMIZE
  11         select ARCH_HAS_FORTIFY_SOURCE
  12         select ARCH_HAS_KEEPINITRD
  13         select ARCH_HAS_KCOV
  14         select ARCH_HAS_MEMBARRIER_SYNC_CORE
  15         select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
  16         select ARCH_HAS_PHYS_TO_DMA
  17         select ARCH_HAS_SETUP_DMA_OPS
  18         select ARCH_HAS_SET_MEMORY
  19         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  20         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  21         select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
  22         select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
  23         select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
  24         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  25         select ARCH_HAVE_CUSTOM_GPIO_H
  26         select ARCH_HAS_GCOV_PROFILE_ALL
  27         select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
  28         select ARCH_MIGHT_HAVE_PC_PARPORT
  29         select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
  30         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  31         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  32         select ARCH_SUPPORTS_ATOMIC_RMW
  33         select ARCH_USE_BUILTIN_BSWAP
  34         select ARCH_USE_CMPXCHG_LOCKREF
  35         select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
  36         select ARCH_WANT_IPC_PARSE_VERSION
  37         select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
  38         select BUILDTIME_TABLE_SORT if MMU
  39         select CLONE_BACKWARDS
  40         select CPU_PM if SUSPEND || CPU_IDLE
  41         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  42         select DMA_DECLARE_COHERENT
  43         select DMA_REMAP if MMU
  44         select EDAC_SUPPORT
  45         select EDAC_ATOMIC_SCRUB
  46         select GENERIC_ALLOCATOR
  47         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  48         select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
  49         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  50         select GENERIC_CPU_AUTOPROBE
  51         select GENERIC_EARLY_IOREMAP
  52         select GENERIC_IDLE_POLL_SETUP
  53         select GENERIC_IRQ_PROBE
  54         select GENERIC_IRQ_SHOW
  55         select GENERIC_IRQ_SHOW_LEVEL
  56         select GENERIC_PCI_IOMAP
  57         select GENERIC_SCHED_CLOCK
  58         select GENERIC_SMP_IDLE_THREAD
  59         select GENERIC_STRNCPY_FROM_USER
  60         select GENERIC_STRNLEN_USER
  61         select HANDLE_DOMAIN_IRQ
  62         select HARDIRQS_SW_RESEND
  63         select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
  64         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  65         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  66         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  67         select HAVE_ARCH_MMAP_RND_BITS if MMU
  68         select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
  69         select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  70         select HAVE_ARCH_TRACEHOOK
  71         select HAVE_ARM_SMCCC if CPU_V7
  72         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  73         select HAVE_CONTEXT_TRACKING
  74         select HAVE_COPY_THREAD_TLS
  75         select HAVE_C_RECORDMCOUNT
  76         select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
  77         select HAVE_DMA_CONTIGUOUS if MMU
  78         select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  79         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  80         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  81         select HAVE_EXIT_THREAD
  82         select HAVE_FAST_GUP if ARM_LPAE
  83         select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
  84         select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
  85         select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
  86         select HAVE_GCC_PLUGINS
  87         select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
  88         select HAVE_IDE if PCI || ISA || PCMCIA
  89         select HAVE_IRQ_TIME_ACCOUNTING
  90         select HAVE_KERNEL_GZIP
  91         select HAVE_KERNEL_LZ4
  92         select HAVE_KERNEL_LZMA
  93         select HAVE_KERNEL_LZO
  94         select HAVE_KERNEL_XZ
  95         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  96         select HAVE_KRETPROBES if HAVE_KPROBES
  97         select HAVE_MOD_ARCH_SPECIFIC
  98         select HAVE_NMI
  99         select HAVE_OPROFILE if HAVE_PERF_EVENTS
 100         select HAVE_OPTPROBES if !THUMB2_KERNEL
 101         select HAVE_PERF_EVENTS
 102         select HAVE_PERF_REGS
 103         select HAVE_PERF_USER_STACK_DUMP
 104         select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
 105         select HAVE_REGS_AND_STACK_ACCESS_API
 106         select HAVE_RSEQ
 107         select HAVE_STACKPROTECTOR
 108         select HAVE_SYSCALL_TRACEPOINTS
 109         select HAVE_UID16
 110         select HAVE_VIRT_CPU_ACCOUNTING_GEN
 111         select IRQ_FORCED_THREADING
 112         select MODULES_USE_ELF_REL
 113         select NEED_DMA_MAP_STATE
 114         select OF_EARLY_FLATTREE if OF
 115         select OLD_SIGACTION
 116         select OLD_SIGSUSPEND3
 117         select PCI_SYSCALL if PCI
 118         select PERF_USE_VMALLOC
 119         select RTC_LIB
 120         select SYS_SUPPORTS_APM_EMULATION
 121         # Above selects are sorted alphabetically; please add new ones
 122         # according to that.  Thanks.
 123         help
 124           The ARM series is a line of low-power-consumption RISC chip designs
 125           licensed by ARM Ltd and targeted at embedded applications and
 126           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 127           manufactured, but legacy ARM-based PC hardware remains popular in
 128           Europe.  There is an ARM Linux project with a web page at
 129           <http://www.arm.linux.org.uk/>.
 130
 131 config ARM_HAS_SG_CHAIN
 132         bool
 133
 134 config ARM_DMA_USE_IOMMU
 135         bool
 136         select ARM_HAS_SG_CHAIN
 137         select NEED_SG_DMA_LENGTH
 138
 139 if ARM_DMA_USE_IOMMU
 140
 141 config ARM_DMA_IOMMU_ALIGNMENT
 142         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 143         range 4 9
 144         default 8
 145         help
 146           DMA mapping framework by default aligns all buffers to the smallest
 147           PAGE_SIZE order which is greater than or equal to the requested buffer
 148           size. This works well for buffers up to a few hundreds kilobytes, but
 149           for larger buffers it just a waste of address space. Drivers which has
 150           relatively small addressing window (like 64Mib) might run out of
 151           virtual space with just a few allocations.
 152
 153           With this parameter you can specify the maximum PAGE_SIZE order for
 154           DMA IOMMU buffers. Larger buffers will be aligned only to this
 155           specified order. The order is expressed as a power of two multiplied
 156           by the PAGE_SIZE.
 157
 158 endif
 159
 160 config SYS_SUPPORTS_APM_EMULATION
 161         bool
 162
 163 config HAVE_TCM
 164         bool
 165         select GENERIC_ALLOCATOR
 166
 167 config HAVE_PROC_CPU
 168         bool
 169
 170 config NO_IOPORT_MAP
 171         bool
 172
 173 config SBUS
 174         bool
 175
 176 config STACKTRACE_SUPPORT
 177         bool
 178         default y
 179
 180 config LOCKDEP_SUPPORT
 181         bool
 182         default y
 183
 184 config TRACE_IRQFLAGS_SUPPORT
 185         bool
 186         default !CPU_V7M
 187
 188 config ARCH_HAS_ILOG2_U32
 189         bool
 190
 191 config ARCH_HAS_ILOG2_U64
 192         bool
 193
 194 config ARCH_HAS_BANDGAP
 195         bool
 196
 197 config FIX_EARLYCON_MEM
 198         def_bool y if MMU
 199
 200 config GENERIC_HWEIGHT
 201         bool
 202         default y
 203
 204 config GENERIC_CALIBRATE_DELAY
 205         bool
 206         default y
 207
 208 config ARCH_MAY_HAVE_PC_FDC
 209         bool
 210
 211 config ZONE_DMA
 212         bool
 213
 214 config ARCH_SUPPORTS_UPROBES
 215         def_bool y
 216
 217 config ARCH_HAS_DMA_SET_COHERENT_MASK
 218         bool
 219
 220 config GENERIC_ISA_DMA
 221         bool
 222
 223 config FIQ
 224         bool
 225
 226 config NEED_RET_TO_USER
 227         bool
 228
 229 config ARCH_MTD_XIP
 230         bool
 231
 232 config ARM_PATCH_PHYS_VIRT
 233         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 234         default y
 235         depends on !XIP_KERNEL && MMU
 236         help
 237           Patch phys-to-virt and virt-to-phys translation functions at
 238           boot and module load time according to the position of the
 239           kernel in system memory.
 240
 241           This can only be used with non-XIP MMU kernels where the base
 242           of physical memory is at a 16MB boundary.
 243
 244           Only disable this option if you know that you do not require
 245           this feature (eg, building a kernel for a single machine) and
 246           you need to shrink the kernel to the minimal size.
 247
 248 config NEED_MACH_IO_H
 249         bool
 250         help
 251           Select this when mach/io.h is required to provide special
 252           definitions for this platform.  The need for mach/io.h should
 253           be avoided when possible.
 254
 255 config NEED_MACH_MEMORY_H
 256         bool
 257         help
 258           Select this when mach/memory.h is required to provide special
 259           definitions for this platform.  The need for mach/memory.h should
 260           be avoided when possible.
 261
 262 config PHYS_OFFSET
 263         hex "Physical address of main memory" if MMU
 264         depends on !ARM_PATCH_PHYS_VIRT
 265         default DRAM_BASE if !MMU
 266         default 0x00000000 if ARCH_EBSA110 || \
 267                         ARCH_FOOTBRIDGE || \
 268                         ARCH_INTEGRATOR || \
 269                         ARCH_REALVIEW
 270         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 271         default 0x20000000 if ARCH_S5PV210
 272         default 0xc0000000 if ARCH_SA1100
 273         help
 274           Please provide the physical address corresponding to the
 275           location of main memory in your system.
 276
 277 config GENERIC_BUG
 278         def_bool y
 279         depends on BUG
 280
 281 config PGTABLE_LEVELS
 282         int
 283         default 3 if ARM_LPAE
 284         default 2
 285
 286 menu "System Type"
 287
 288 config MMU
 289         bool "MMU-based Paged Memory Management Support"
 290         default y
 291         help
 292           Select if you want MMU-based virtualised addressing space
 293           support by paged memory management. If unsure, say 'Y'.
 294
 295 config ARCH_MMAP_RND_BITS_MIN
 296         default 8
 297
 298 config ARCH_MMAP_RND_BITS_MAX
 299         default 14 if PAGE_OFFSET=0x40000000
 300         default 15 if PAGE_OFFSET=0x80000000
 301         default 16
 302
 303 #
 304 # The "ARM system type" choice list is ordered alphabetically by option
 305 # text.  Please add new entries in the option alphabetic order.
 306 #
 307 choice
 308         prompt "ARM system type"
 309         default ARM_SINGLE_ARMV7M if !MMU
 310         default ARCH_MULTIPLATFORM if MMU
 311
 312 config ARCH_MULTIPLATFORM
 313         bool "Allow multiple platforms to be selected"
 314         depends on MMU
 315         select ARM_HAS_SG_CHAIN
 316         select ARM_PATCH_PHYS_VIRT
 317         select AUTO_ZRELADDR
 318         select TIMER_OF
 319         select COMMON_CLK
 320         select GENERIC_CLOCKEVENTS
 321         select GENERIC_IRQ_MULTI_HANDLER
 322         select HAVE_PCI
 323         select PCI_DOMAINS_GENERIC if PCI
 324         select SPARSE_IRQ
 325         select USE_OF
 326
 327 config ARM_SINGLE_ARMV7M
 328         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 329         depends on !MMU
 330         select ARM_NVIC
 331         select AUTO_ZRELADDR
 332         select TIMER_OF
 333         select COMMON_CLK
 334         select CPU_V7M
 335         select GENERIC_CLOCKEVENTS
 336         select NO_IOPORT_MAP
 337         select SPARSE_IRQ
 338         select USE_OF
 339
 340 config ARCH_EBSA110
 341         bool "EBSA-110"
 342         select ARCH_USES_GETTIMEOFFSET
 343         select CPU_SA110
 344         select ISA
 345         select NEED_MACH_IO_H
 346         select NEED_MACH_MEMORY_H
 347         select NO_IOPORT_MAP
 348         help
 349           This is an evaluation board for the StrongARM processor available
 350           from Digital. It has limited hardware on-board, including an
 351           Ethernet interface, two PCMCIA sockets, two serial ports and a
 352           parallel port.
 353
 354 config ARCH_EP93XX
 355         bool "EP93xx-based"
 356         select ARCH_SPARSEMEM_ENABLE
 357         select ARM_AMBA
 358         imply ARM_PATCH_PHYS_VIRT
 359         select ARM_VIC
 360         select AUTO_ZRELADDR
 361         select CLKDEV_LOOKUP
 362         select CLKSRC_MMIO
 363         select CPU_ARM920T
 364         select GENERIC_CLOCKEVENTS
 365         select GPIOLIB
 366         help
 367           This enables support for the Cirrus EP93xx series of CPUs.
 368
 369 config ARCH_FOOTBRIDGE
 370         bool "FootBridge"
 371         select CPU_SA110
 372         select FOOTBRIDGE
 373         select GENERIC_CLOCKEVENTS
 374         select HAVE_IDE
 375         select NEED_MACH_IO_H if !MMU
 376         select NEED_MACH_MEMORY_H
 377         help
 378           Support for systems based on the DC21285 companion chip
 379           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 380
 381 config ARCH_IOP32X
 382         bool "IOP32x-based"
 383         depends on MMU
 384         select CPU_XSCALE
 385         select GPIO_IOP
 386         select GPIOLIB
 387         select NEED_RET_TO_USER
 388         select FORCE_PCI
 389         select PLAT_IOP
 390         help
 391           Support for Intel's 80219 and IOP32X (XScale) family of
 392           processors.
 393
 394 config ARCH_IXP4XX
 395         bool "IXP4xx-based"
 396         depends on MMU
 397         select ARCH_HAS_DMA_SET_COHERENT_MASK
 398         select ARCH_SUPPORTS_BIG_ENDIAN
 399         select CPU_XSCALE
 400         select DMABOUNCE if PCI
 401         select GENERIC_CLOCKEVENTS
 402         select GENERIC_IRQ_MULTI_HANDLER
 403         select GPIO_IXP4XX
 404         select GPIOLIB
 405         select HAVE_PCI
 406         select IXP4XX_IRQ
 407         select IXP4XX_TIMER
 408         select NEED_MACH_IO_H
 409         select USB_EHCI_BIG_ENDIAN_DESC
 410         select USB_EHCI_BIG_ENDIAN_MMIO
 411         help
 412           Support for Intel's IXP4XX (XScale) family of processors.
 413
 414 config ARCH_DOVE
 415         bool "Marvell Dove"
 416         select CPU_PJ4
 417         select GENERIC_CLOCKEVENTS
 418         select GENERIC_IRQ_MULTI_HANDLER
 419         select GPIOLIB
 420         select HAVE_PCI
 421         select MVEBU_MBUS
 422         select PINCTRL
 423         select PINCTRL_DOVE
 424         select PLAT_ORION_LEGACY
 425         select SPARSE_IRQ
 426         select PM_GENERIC_DOMAINS if PM
 427         help
 428           Support for the Marvell Dove SoC 88AP510
 429
 430 config ARCH_PXA
 431         bool "PXA2xx/PXA3xx-based"
 432         depends on MMU
 433         select ARCH_MTD_XIP
 434         select ARM_CPU_SUSPEND if PM
 435         select AUTO_ZRELADDR
 436         select COMMON_CLK
 437         select CLKDEV_LOOKUP
 438         select CLKSRC_PXA
 439         select CLKSRC_MMIO
 440         select TIMER_OF
 441         select CPU_XSCALE if !CPU_XSC3
 442         select GENERIC_CLOCKEVENTS
 443         select GENERIC_IRQ_MULTI_HANDLER
 444         select GPIO_PXA
 445         select GPIOLIB
 446         select HAVE_IDE
 447         select IRQ_DOMAIN
 448         select PLAT_PXA
 449         select SPARSE_IRQ
 450         help
 451           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 452
 453 config ARCH_RPC
 454         bool "RiscPC"
 455         depends on MMU
 456         select ARCH_ACORN
 457         select ARCH_MAY_HAVE_PC_FDC
 458         select ARCH_SPARSEMEM_ENABLE
 459         select ARM_HAS_SG_CHAIN
 460         select CPU_SA110
 461         select FIQ
 462         select HAVE_IDE
 463         select HAVE_PATA_PLATFORM
 464         select ISA_DMA_API
 465         select NEED_MACH_IO_H
 466         select NEED_MACH_MEMORY_H
 467         select NO_IOPORT_MAP
 468         help
 469           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 470           CD-ROM interface, serial and parallel port, and the floppy drive.
 471
 472 config ARCH_SA1100
 473         bool "SA1100-based"
 474         select ARCH_MTD_XIP
 475         select ARCH_SPARSEMEM_ENABLE
 476         select CLKDEV_LOOKUP
 477         select CLKSRC_MMIO
 478         select CLKSRC_PXA
 479         select TIMER_OF if OF
 480         select COMMON_CLK
 481         select CPU_FREQ
 482         select CPU_SA1100
 483         select GENERIC_CLOCKEVENTS
 484         select GENERIC_IRQ_MULTI_HANDLER
 485         select GPIOLIB
 486         select HAVE_IDE
 487         select IRQ_DOMAIN
 488         select ISA
 489         select NEED_MACH_MEMORY_H
 490         select SPARSE_IRQ
 491         help
 492           Support for StrongARM 11x0 based boards.
 493
 494 config ARCH_S3C24XX
 495         bool "Samsung S3C24XX SoCs"
 496         select ATAGS
 497         select CLKDEV_LOOKUP
 498         select CLKSRC_SAMSUNG_PWM
 499         select GENERIC_CLOCKEVENTS
 500         select GPIO_SAMSUNG
 501         select GPIOLIB
 502         select GENERIC_IRQ_MULTI_HANDLER
 503         select HAVE_S3C2410_I2C if I2C
 504         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 505         select HAVE_S3C_RTC if RTC_CLASS
 506         select NEED_MACH_IO_H
 507         select SAMSUNG_ATAGS
 508         select USE_OF
 509         help
 510           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 511           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 512           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 513           Samsung SMDK2410 development board (and derivatives).
 514
 515 config ARCH_OMAP1
 516         bool "TI OMAP1"
 517         depends on MMU
 518         select ARCH_HAS_HOLES_MEMORYMODEL
 519         select ARCH_OMAP
 520         select CLKDEV_LOOKUP
 521         select CLKSRC_MMIO
 522         select GENERIC_CLOCKEVENTS
 523         select GENERIC_IRQ_CHIP
 524         select GENERIC_IRQ_MULTI_HANDLER
 525         select GPIOLIB
 526         select HAVE_IDE
 527         select IRQ_DOMAIN
 528         select NEED_MACH_IO_H if PCCARD
 529         select NEED_MACH_MEMORY_H
 530         select SPARSE_IRQ
 531         help
 532           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 533
 534 endchoice
 535
 536 menu "Multiple platform selection"
 537         depends on ARCH_MULTIPLATFORM
 538
 539 comment "CPU Core family selection"
 540
 541 config ARCH_MULTI_V4
 542         bool "ARMv4 based platforms (FA526)"
 543         depends on !ARCH_MULTI_V6_V7
 544         select ARCH_MULTI_V4_V5
 545         select CPU_FA526
 546
 547 config ARCH_MULTI_V4T
 548         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 549         depends on !ARCH_MULTI_V6_V7
 550         select ARCH_MULTI_V4_V5
 551         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 552                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 553                 CPU_ARM925T || CPU_ARM940T)
 554
 555 config ARCH_MULTI_V5
 556         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 557         depends on !ARCH_MULTI_V6_V7
 558         select ARCH_MULTI_V4_V5
 559         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 560                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 561                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 562
 563 config ARCH_MULTI_V4_V5
 564         bool
 565
 566 config ARCH_MULTI_V6
 567         bool "ARMv6 based platforms (ARM11)"
 568         select ARCH_MULTI_V6_V7
 569         select CPU_V6K
 570
 571 config ARCH_MULTI_V7
 572         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 573         default y
 574         select ARCH_MULTI_V6_V7
 575         select CPU_V7
 576         select HAVE_SMP
 577
 578 config ARCH_MULTI_V6_V7
 579         bool
 580         select MIGHT_HAVE_CACHE_L2X0
 581
 582 config ARCH_MULTI_CPU_AUTO
 583         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 584         select ARCH_MULTI_V5
 585
 586 endmenu
 587
 588 config ARCH_VIRT
 589         bool "Dummy Virtual Machine"
 590         depends on ARCH_MULTI_V7
 591         select ARM_AMBA
 592         select ARM_GIC
 593         select ARM_GIC_V2M if PCI
 594         select ARM_GIC_V3
 595         select ARM_GIC_V3_ITS if PCI
 596         select ARM_PSCI
 597         select HAVE_ARM_ARCH_TIMER
 598         select ARCH_SUPPORTS_BIG_ENDIAN
 599
 600 #
 601 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 602 # Kconfigs may be included either alphabetically (according to the
 603 # plat- suffix) or along side the corresponding mach-* source.
 604 #
 605 source "arch/arm/mach-actions/Kconfig"
 606
 607 source "arch/arm/mach-alpine/Kconfig"
 608
 609 source "arch/arm/mach-artpec/Kconfig"
 610
 611 source "arch/arm/mach-asm9260/Kconfig"
 612
 613 source "arch/arm/mach-aspeed/Kconfig"
 614
 615 source "arch/arm/mach-at91/Kconfig"
 616
 617 source "arch/arm/mach-axxia/Kconfig"
 618
 619 source "arch/arm/mach-bcm/Kconfig"
 620
 621 source "arch/arm/mach-berlin/Kconfig"
 622
 623 source "arch/arm/mach-clps711x/Kconfig"
 624
 625 source "arch/arm/mach-cns3xxx/Kconfig"
 626
 627 source "arch/arm/mach-davinci/Kconfig"
 628
 629 source "arch/arm/mach-digicolor/Kconfig"
 630
 631 source "arch/arm/mach-dove/Kconfig"
 632
 633 source "arch/arm/mach-ep93xx/Kconfig"
 634
 635 source "arch/arm/mach-exynos/Kconfig"
 636 source "arch/arm/plat-samsung/Kconfig"
 637
 638 source "arch/arm/mach-footbridge/Kconfig"
 639
 640 source "arch/arm/mach-gemini/Kconfig"
 641
 642 source "arch/arm/mach-highbank/Kconfig"
 643
 644 source "arch/arm/mach-hisi/Kconfig"
 645
 646 source "arch/arm/mach-imx/Kconfig"
 647
 648 source "arch/arm/mach-integrator/Kconfig"
 649
 650 source "arch/arm/mach-iop32x/Kconfig"
 651
 652 source "arch/arm/mach-ixp4xx/Kconfig"
 653
 654 source "arch/arm/mach-keystone/Kconfig"
 655
 656 source "arch/arm/mach-lpc32xx/Kconfig"
 657
 658 source "arch/arm/mach-mediatek/Kconfig"
 659
 660 source "arch/arm/mach-meson/Kconfig"
 661
 662 source "arch/arm/mach-milbeaut/Kconfig"
 663
 664 source "arch/arm/mach-mmp/Kconfig"
 665
 666 source "arch/arm/mach-moxart/Kconfig"
 667
 668 source "arch/arm/mach-mv78xx0/Kconfig"
 669
 670 source "arch/arm/mach-mvebu/Kconfig"
 671
 672 source "arch/arm/mach-mxs/Kconfig"
 673
 674 source "arch/arm/mach-nomadik/Kconfig"
 675
 676 source "arch/arm/mach-npcm/Kconfig"
 677
 678 source "arch/arm/mach-nspire/Kconfig"
 679
 680 source "arch/arm/plat-omap/Kconfig"
 681
 682 source "arch/arm/mach-omap1/Kconfig"
 683
 684 source "arch/arm/mach-omap2/Kconfig"
 685
 686 source "arch/arm/mach-orion5x/Kconfig"
 687
 688 source "arch/arm/mach-oxnas/Kconfig"
 689
 690 source "arch/arm/mach-picoxcell/Kconfig"
 691
 692 source "arch/arm/mach-prima2/Kconfig"
 693
 694 source "arch/arm/mach-pxa/Kconfig"
 695 source "arch/arm/plat-pxa/Kconfig"
 696
 697 source "arch/arm/mach-qcom/Kconfig"
 698
 699 source "arch/arm/mach-rda/Kconfig"
 700
 701 source "arch/arm/mach-realview/Kconfig"
 702
 703 source "arch/arm/mach-rockchip/Kconfig"
 704
 705 source "arch/arm/mach-s3c24xx/Kconfig"
 706
 707 source "arch/arm/mach-s3c64xx/Kconfig"
 708
 709 source "arch/arm/mach-s5pv210/Kconfig"
 710
 711 source "arch/arm/mach-sa1100/Kconfig"
 712
 713 source "arch/arm/mach-shmobile/Kconfig"
 714
 715 source "arch/arm/mach-socfpga/Kconfig"
 716
 717 source "arch/arm/mach-spear/Kconfig"
 718
 719 source "arch/arm/mach-sti/Kconfig"
 720
 721 source "arch/arm/mach-stm32/Kconfig"
 722
 723 source "arch/arm/mach-sunxi/Kconfig"
 724
 725 source "arch/arm/mach-tango/Kconfig"
 726
 727 source "arch/arm/mach-tegra/Kconfig"
 728
 729 source "arch/arm/mach-u300/Kconfig"
 730
 731 source "arch/arm/mach-uniphier/Kconfig"
 732
 733 source "arch/arm/mach-ux500/Kconfig"
 734
 735 source "arch/arm/mach-versatile/Kconfig"
 736
 737 source "arch/arm/mach-vexpress/Kconfig"
 738 source "arch/arm/plat-versatile/Kconfig"
 739
 740 source "arch/arm/mach-vt8500/Kconfig"
 741
 742 source "arch/arm/mach-zx/Kconfig"
 743
 744 source "arch/arm/mach-zynq/Kconfig"
 745
 746 # ARMv7-M architecture
 747 config ARCH_EFM32
 748         bool "Energy Micro efm32"
 749         depends on ARM_SINGLE_ARMV7M
 750         select GPIOLIB
 751         help
 752           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 753           processors.
 754
 755 config ARCH_LPC18XX
 756         bool "NXP LPC18xx/LPC43xx"
 757         depends on ARM_SINGLE_ARMV7M
 758         select ARCH_HAS_RESET_CONTROLLER
 759         select ARM_AMBA
 760         select CLKSRC_LPC32XX
 761         select PINCTRL
 762         help
 763           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 764           high performance microcontrollers.
 765
 766 config ARCH_MPS2
 767         bool "ARM MPS2 platform"
 768         depends on ARM_SINGLE_ARMV7M
 769         select ARM_AMBA
 770         select CLKSRC_MPS2
 771         help
 772           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 773           with a range of available cores like Cortex-M3/M4/M7.
 774
 775           Please, note that depends which Application Note is used memory map
 776           for the platform may vary, so adjustment of RAM base might be needed.
 777
 778 # Definitions to make life easier
 779 config ARCH_ACORN
 780         bool
 781
 782 config PLAT_IOP
 783         bool
 784         select GENERIC_CLOCKEVENTS
 785
 786 config PLAT_ORION
 787         bool
 788         select CLKSRC_MMIO
 789         select COMMON_CLK
 790         select GENERIC_IRQ_CHIP
 791         select IRQ_DOMAIN
 792
 793 config PLAT_ORION_LEGACY
 794         bool
 795         select PLAT_ORION
 796
 797 config PLAT_PXA
 798         bool
 799
 800 config PLAT_VERSATILE
 801         bool
 802
 803 source "arch/arm/mm/Kconfig"
 804
 805 config IWMMXT
 806         bool "Enable iWMMXt support"
 807         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 808         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 809         help
 810           Enable support for iWMMXt context switching at run time if
 811           running on a CPU that supports it.
 812
 813 if !MMU
 814 source "arch/arm/Kconfig-nommu"
 815 endif
 816
 817 config PJ4B_ERRATA_4742
 818         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 819         depends on CPU_PJ4B && MACH_ARMADA_370
 820         default y
 821         help
 822           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 823           Event (WFE) IDLE states, a specific timing sensitivity exists between
 824           the retiring WFI/WFE instructions and the newly issued subsequent
 825           instructions.  This sensitivity can result in a CPU hang scenario.
 826           Workaround:
 827           The software must insert either a Data Synchronization Barrier (DSB)
 828           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 829           instruction
 830
 831 config ARM_ERRATA_326103
 832         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 833         depends on CPU_V6
 834         help
 835           Executing a SWP instruction to read-only memory does not set bit 11
 836           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 837           treat the access as a read, preventing a COW from occurring and
 838           causing the faulting task to livelock.
 839
 840 config ARM_ERRATA_411920
 841         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 842         depends on CPU_V6 || CPU_V6K
 843         help
 844           Invalidation of the Instruction Cache operation can
 845           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 846           It does not affect the MPCore. This option enables the ARM Ltd.
 847           recommended workaround.
 848
 849 config ARM_ERRATA_430973
 850         bool "ARM errata: Stale prediction on replaced interworking branch"
 851         depends on CPU_V7
 852         help
 853           This option enables the workaround for the 430973 Cortex-A8
 854           r1p* erratum. If a code sequence containing an ARM/Thumb
 855           interworking branch is replaced with another code sequence at the
 856           same virtual address, whether due to self-modifying code or virtual
 857           to physical address re-mapping, Cortex-A8 does not recover from the
 858           stale interworking branch prediction. This results in Cortex-A8
 859           executing the new code sequence in the incorrect ARM or Thumb state.
 860           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 861           and also flushes the branch target cache at every context switch.
 862           Note that setting specific bits in the ACTLR register may not be
 863           available in non-secure mode.
 864
 865 config ARM_ERRATA_458693
 866         bool "ARM errata: Processor deadlock when a false hazard is created"
 867         depends on CPU_V7
 868         depends on !ARCH_MULTIPLATFORM
 869         help
 870           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 871           erratum. For very specific sequences of memory operations, it is
 872           possible for a hazard condition intended for a cache line to instead
 873           be incorrectly associated with a different cache line. This false
 874           hazard might then cause a processor deadlock. The workaround enables
 875           the L1 caching of the NEON accesses and disables the PLD instruction
 876           in the ACTLR register. Note that setting specific bits in the ACTLR
 877           register may not be available in non-secure mode.
 878
 879 config ARM_ERRATA_460075
 880         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 881         depends on CPU_V7
 882         depends on !ARCH_MULTIPLATFORM
 883         help
 884           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
 885           erratum. Any asynchronous access to the L2 cache may encounter a
 886           situation in which recent store transactions to the L2 cache are lost
 887           and overwritten with stale memory contents from external memory. The
 888           workaround disables the write-allocate mode for the L2 cache via the
 889           ACTLR register. Note that setting specific bits in the ACTLR register
 890           may not be available in non-secure mode.
 891
 892 config ARM_ERRATA_742230
 893         bool "ARM errata: DMB operation may be faulty"
 894         depends on CPU_V7 && SMP
 895         depends on !ARCH_MULTIPLATFORM
 896         help
 897           This option enables the workaround for the 742230 Cortex-A9
 898           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
 899           between two write operations may not ensure the correct visibility
 900           ordering of the two writes. This workaround sets a specific bit in
 901           the diagnostic register of the Cortex-A9 which causes the DMB
 902           instruction to behave as a DSB, ensuring the correct behaviour of
 903           the two writes.
 904
 905 config ARM_ERRATA_742231
 906         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
 907         depends on CPU_V7 && SMP
 908         depends on !ARCH_MULTIPLATFORM
 909         help
 910           This option enables the workaround for the 742231 Cortex-A9
 911           (r2p0..r2p2) erratum. Under certain conditions, specific to the
 912           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
 913           accessing some data located in the same cache line, may get corrupted
 914           data due to bad handling of the address hazard when the line gets
 915           replaced from one of the CPUs at the same time as another CPU is
 916           accessing it. This workaround sets specific bits in the diagnostic
 917           register of the Cortex-A9 which reduces the linefill issuing
 918           capabilities of the processor.
 919
 920 config ARM_ERRATA_643719
 921         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
 922         depends on CPU_V7 && SMP
 923         default y
 924         help
 925           This option enables the workaround for the 643719 Cortex-A9 (prior to
 926           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
 927           register returns zero when it should return one. The workaround
 928           corrects this value, ensuring cache maintenance operations which use
 929           it behave as intended and avoiding data corruption.
 930
 931 config ARM_ERRATA_720789
 932         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
 933         depends on CPU_V7
 934         help
 935           This option enables the workaround for the 720789 Cortex-A9 (prior to
 936           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
 937           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
 938           As a consequence of this erratum, some TLB entries which should be
 939           invalidated are not, resulting in an incoherency in the system page
 940           tables. The workaround changes the TLB flushing routines to invalidate
 941           entries regardless of the ASID.
 942
 943 config ARM_ERRATA_743622
 944         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
 945         depends on CPU_V7
 946         depends on !ARCH_MULTIPLATFORM
 947         help
 948           This option enables the workaround for the 743622 Cortex-A9
 949           (r2p*) erratum. Under very rare conditions, a faulty
 950           optimisation in the Cortex-A9 Store Buffer may lead to data
 951           corruption. This workaround sets a specific bit in the diagnostic
 952           register of the Cortex-A9 which disables the Store Buffer
 953           optimisation, preventing the defect from occurring. This has no
 954           visible impact on the overall performance or power consumption of the
 955           processor.
 956
 957 config ARM_ERRATA_751472
 958         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
 959         depends on CPU_V7
 960         depends on !ARCH_MULTIPLATFORM
 961         help
 962           This option enables the workaround for the 751472 Cortex-A9 (prior
 963           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
 964           completion of a following broadcasted operation if the second
 965           operation is received by a CPU before the ICIALLUIS has completed,
 966           potentially leading to corrupted entries in the cache or TLB.
 967
 968 config ARM_ERRATA_754322
 969         bool "ARM errata: possible faulty MMU translations following an ASID switch"
 970         depends on CPU_V7
 971         help
 972           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
 973           r3p*) erratum. A speculative memory access may cause a page table walk
 974           which starts prior to an ASID switch but completes afterwards. This
 975           can populate the micro-TLB with a stale entry which may be hit with
 976           the new ASID. This workaround places two dsb instructions in the mm
 977           switching code so that no page table walks can cross the ASID switch.
 978
 979 config ARM_ERRATA_754327
 980         bool "ARM errata: no automatic Store Buffer drain"
 981         depends on CPU_V7 && SMP
 982         help
 983           This option enables the workaround for the 754327 Cortex-A9 (prior to
 984           r2p0) erratum. The Store Buffer does not have any automatic draining
 985           mechanism and therefore a livelock may occur if an external agent
 986           continuously polls a memory location waiting to observe an update.
 987           This workaround defines cpu_relax() as smp_mb(), preventing correctly
 988           written polling loops from denying visibility of updates to memory.
 989
 990 config ARM_ERRATA_364296
 991         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
 992         depends on CPU_V6
 993         help
 994           This options enables the workaround for the 364296 ARM1136
 995           r0p2 erratum (possible cache data corruption with
 996           hit-under-miss enabled). It sets the undocumented bit 31 in
 997           the auxiliary control register and the FI bit in the control
 998           register, thus disabling hit-under-miss without putting the
 999           processor into full low interrupt latency mode. ARM11MPCore
1000           is not affected.
1001
1002 config ARM_ERRATA_764369
1003         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1004         depends on CPU_V7 && SMP
1005         help
1006           This option enables the workaround for erratum 764369
1007           affecting Cortex-A9 MPCore with two or more processors (all
1008           current revisions). Under certain timing circumstances, a data
1009           cache line maintenance operation by MVA targeting an Inner
1010           Shareable memory region may fail to proceed up to either the
1011           Point of Coherency or to the Point of Unification of the
1012           system. This workaround adds a DSB instruction before the
1013           relevant cache maintenance functions and sets a specific bit
1014           in the diagnostic control register of the SCU.
1015
1016 config ARM_ERRATA_775420
1017        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1018        depends on CPU_V7
1019        help
1020          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1021          r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1022          operation aborts with MMU exception, it might cause the processor
1023          to deadlock. This workaround puts DSB before executing ISB if
1024          an abort may occur on cache maintenance.
1025
1026 config ARM_ERRATA_798181
1027         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1028         depends on CPU_V7 && SMP
1029         help
1030           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1031           adequately shooting down all use of the old entries. This
1032           option enables the Linux kernel workaround for this erratum
1033           which sends an IPI to the CPUs that are running the same ASID
1034           as the one being invalidated.
1035
1036 config ARM_ERRATA_773022
1037         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1038         depends on CPU_V7
1039         help
1040           This option enables the workaround for the 773022 Cortex-A15
1041           (up to r0p4) erratum. In certain rare sequences of code, the
1042           loop buffer may deliver incorrect instructions. This
1043           workaround disables the loop buffer to avoid the erratum.
1044
1045 config ARM_ERRATA_818325_852422
1046         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1047         depends on CPU_V7
1048         help
1049           This option enables the workaround for:
1050           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1051             instruction might deadlock.  Fixed in r0p1.
1052           - Cortex-A12 852422: Execution of a sequence of instructions might
1053             lead to either a data corruption or a CPU deadlock.  Not fixed in
1054             any Cortex-A12 cores yet.
1055           This workaround for all both errata involves setting bit[12] of the
1056           Feature Register. This bit disables an optimisation applied to a
1057           sequence of 2 instructions that use opposing condition codes.
1058
1059 config ARM_ERRATA_821420
1060         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1061         depends on CPU_V7
1062         help
1063           This option enables the workaround for the 821420 Cortex-A12
1064           (all revs) erratum. In very rare timing conditions, a sequence
1065           of VMOV to Core registers instructions, for which the second
1066           one is in the shadow of a branch or abort, can lead to a
1067           deadlock when the VMOV instructions are issued out-of-order.
1068
1069 config ARM_ERRATA_825619
1070         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1071         depends on CPU_V7
1072         help
1073           This option enables the workaround for the 825619 Cortex-A12
1074           (all revs) erratum. Within rare timing constraints, executing a
1075           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1076           and Device/Strongly-Ordered loads and stores might cause deadlock
1077
1078 config ARM_ERRATA_857271
1079         bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1080         depends on CPU_V7
1081         help
1082           This option enables the workaround for the 857271 Cortex-A12
1083           (all revs) erratum. Under very rare timing conditions, the CPU might
1084           hang. The workaround is expected to have a < 1% performance impact.
1085
1086 config ARM_ERRATA_852421
1087         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1088         depends on CPU_V7
1089         help
1090           This option enables the workaround for the 852421 Cortex-A17
1091           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1092           execution of a DMB ST instruction might fail to properly order
1093           stores from GroupA and stores from GroupB.
1094
1095 config ARM_ERRATA_852423
1096         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1097         depends on CPU_V7
1098         help
1099           This option enables the workaround for:
1100           - Cortex-A17 852423: Execution of a sequence of instructions might
1101             lead to either a data corruption or a CPU deadlock.  Not fixed in
1102             any Cortex-A17 cores yet.
1103           This is identical to Cortex-A12 erratum 852422.  It is a separate
1104           config option from the A12 erratum due to the way errata are checked
1105           for and handled.
1106
1107 config ARM_ERRATA_857272
1108         bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1109         depends on CPU_V7
1110         help
1111           This option enables the workaround for the 857272 Cortex-A17 erratum.
1112           This erratum is not known to be fixed in any A17 revision.
1113           This is identical to Cortex-A12 erratum 857271.  It is a separate
1114           config option from the A12 erratum due to the way errata are checked
1115           for and handled.
1116
1117 endmenu
1118
1119 source "arch/arm/common/Kconfig"
1120
1121 menu "Bus support"
1122
1123 config ISA
1124         bool
1125         help
1126           Find out whether you have ISA slots on your motherboard.  ISA is the
1127           name of a bus system, i.e. the way the CPU talks to the other stuff
1128           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1129           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1130           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1131
1132 # Select ISA DMA controller support
1133 config ISA_DMA
1134         bool
1135         select ISA_DMA_API
1136
1137 # Select ISA DMA interface
1138 config ISA_DMA_API
1139         bool
1140
1141 config PCI_NANOENGINE
1142         bool "BSE nanoEngine PCI support"
1143         depends on SA1100_NANOENGINE
1144         help
1145           Enable PCI on the BSE nanoEngine board.
1146
1147 config PCI_HOST_ITE8152
1148         bool
1149         depends on PCI && MACH_ARMCORE
1150         default y
1151         select DMABOUNCE
1152
1153 config ARM_ERRATA_814220
1154         bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1155         depends on CPU_V7
1156         help
1157           The v7 ARM states that all cache and branch predictor maintenance
1158           operations that do not specify an address execute, relative to
1159           each other, in program order.
1160           However, because of this erratum, an L2 set/way cache maintenance
1161           operation can overtake an L1 set/way cache maintenance operation.
1162           This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1163           r0p4, r0p5.
1164
1165 endmenu
1166
1167 menu "Kernel Features"
1168
1169 config HAVE_SMP
1170         bool
1171         help
1172           This option should be selected by machines which have an SMP-
1173           capable CPU.
1174
1175           The only effect of this option is to make the SMP-related
1176           options available to the user for configuration.
1177
1178 config SMP
1179         bool "Symmetric Multi-Processing"
1180         depends on CPU_V6K || CPU_V7
1181         depends on GENERIC_CLOCKEVENTS
1182         depends on HAVE_SMP
1183         depends on MMU || ARM_MPU
1184         select IRQ_WORK
1185         help
1186           This enables support for systems with more than one CPU. If you have
1187           a system with only one CPU, say N. If you have a system with more
1188           than one CPU, say Y.
1189
1190           If you say N here, the kernel will run on uni- and multiprocessor
1191           machines, but will use only one CPU of a multiprocessor machine. If
1192           you say Y here, the kernel will run on many, but not all,
1193           uniprocessor machines. On a uniprocessor machine, the kernel
1194           will run faster if you say N here.
1195
1196           See also <file:Documentation/x86/i386/IO-APIC.rst>,
1197           <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1198           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1199
1200           If you don't know what to do here, say N.
1201
1202 config SMP_ON_UP
1203         bool "Allow booting SMP kernel on uniprocessor systems"
1204         depends on SMP && !XIP_KERNEL && MMU
1205         default y
1206         help
1207           SMP kernels contain instructions which fail on non-SMP processors.
1208           Enabling this option allows the kernel to modify itself to make
1209           these instructions safe.  Disabling it allows about 1K of space
1210           savings.
1211
1212           If you don't know what to do here, say Y.
1213
1214 config ARM_CPU_TOPOLOGY
1215         bool "Support cpu topology definition"
1216         depends on SMP && CPU_V7
1217         default y
1218         help
1219           Support ARM cpu topology definition. The MPIDR register defines
1220           affinity between processors which is then used to describe the cpu
1221           topology of an ARM System.
1222
1223 config SCHED_MC
1224         bool "Multi-core scheduler support"
1225         depends on ARM_CPU_TOPOLOGY
1226         help
1227           Multi-core scheduler support improves the CPU scheduler's decision
1228           making when dealing with multi-core CPU chips at a cost of slightly
1229           increased overhead in some places. If unsure say N here.
1230
1231 config SCHED_SMT
1232         bool "SMT scheduler support"
1233         depends on ARM_CPU_TOPOLOGY
1234         help
1235           Improves the CPU scheduler's decision making when dealing with
1236           MultiThreading at a cost of slightly increased overhead in some
1237           places. If unsure say N here.
1238
1239 config HAVE_ARM_SCU
1240         bool
1241         help
1242           This option enables support for the ARM snoop control unit
1243
1244 config HAVE_ARM_ARCH_TIMER
1245         bool "Architected timer support"
1246         depends on CPU_V7
1247         select ARM_ARCH_TIMER
1248         select GENERIC_CLOCKEVENTS
1249         help
1250           This option enables support for the ARM architected timer
1251
1252 config HAVE_ARM_TWD
1253         bool
1254         help
1255           This options enables support for the ARM timer and watchdog unit
1256
1257 config MCPM
1258         bool "Multi-Cluster Power Management"
1259         depends on CPU_V7 && SMP
1260         help
1261           This option provides the common power management infrastructure
1262           for (multi-)cluster based systems, such as big.LITTLE based
1263           systems.
1264
1265 config MCPM_QUAD_CLUSTER
1266         bool
1267         depends on MCPM
1268         help
1269           To avoid wasting resources unnecessarily, MCPM only supports up
1270           to 2 clusters by default.
1271           Platforms with 3 or 4 clusters that use MCPM must select this
1272           option to allow the additional clusters to be managed.
1273
1274 config BIG_LITTLE
1275         bool "big.LITTLE support (Experimental)"
1276         depends on CPU_V7 && SMP
1277         select MCPM
1278         help
1279           This option enables support selections for the big.LITTLE
1280           system architecture.
1281
1282 config BL_SWITCHER
1283         bool "big.LITTLE switcher support"
1284         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1285         select CPU_PM
1286         help
1287           The big.LITTLE "switcher" provides the core functionality to
1288           transparently handle transition between a cluster of A15's
1289           and a cluster of A7's in a big.LITTLE system.
1290
1291 config BL_SWITCHER_DUMMY_IF
1292         tristate "Simple big.LITTLE switcher user interface"
1293         depends on BL_SWITCHER && DEBUG_KERNEL
1294         help
1295           This is a simple and dummy char dev interface to control
1296           the big.LITTLE switcher core code.  It is meant for
1297           debugging purposes only.
1298
1299 choice
1300         prompt "Memory split"
1301         depends on MMU
1302         default VMSPLIT_3G
1303         help
1304           Select the desired split between kernel and user memory.
1305
1306           If you are not absolutely sure what you are doing, leave this
1307           option alone!
1308
1309         config VMSPLIT_3G
1310                 bool "3G/1G user/kernel split"
1311         config VMSPLIT_3G_OPT
1312                 depends on !ARM_LPAE
1313                 bool "3G/1G user/kernel split (for full 1G low memory)"
1314         config VMSPLIT_2G
1315                 bool "2G/2G user/kernel split"
1316         config VMSPLIT_1G
1317                 bool "1G/3G user/kernel split"
1318 endchoice
1319
1320 config PAGE_OFFSET
1321         hex
1322         default PHYS_OFFSET if !MMU
1323         default 0x40000000 if VMSPLIT_1G
1324         default 0x80000000 if VMSPLIT_2G
1325         default 0xB0000000 if VMSPLIT_3G_OPT
1326         default 0xC0000000
1327
1328 config NR_CPUS
1329         int "Maximum number of CPUs (2-32)"
1330         range 2 32
1331         depends on SMP
1332         default "4"
1333
1334 config HOTPLUG_CPU
1335         bool "Support for hot-pluggable CPUs"
1336         depends on SMP
1337         select GENERIC_IRQ_MIGRATION
1338         help
1339           Say Y here to experiment with turning CPUs off and on.  CPUs
1340           can be controlled through /sys/devices/system/cpu.
1341
1342 config ARM_PSCI
1343         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1344         depends on HAVE_ARM_SMCCC
1345         select ARM_PSCI_FW
1346         help
1347           Say Y here if you want Linux to communicate with system firmware
1348           implementing the PSCI specification for CPU-centric power
1349           management operations described in ARM document number ARM DEN
1350           0022A ("Power State Coordination Interface System Software on
1351           ARM processors").
1352
1353 # The GPIO number here must be sorted by descending number. In case of
1354 # a multiplatform kernel, we just want the highest value required by the
1355 # selected platforms.
1356 config ARCH_NR_GPIO
1357         int
1358         default 2048 if ARCH_SOCFPGA
1359         default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1360                 ARCH_ZYNQ || ARCH_ASPEED
1361         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1362                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1363         default 416 if ARCH_SUNXI
1364         default 392 if ARCH_U8500
1365         default 352 if ARCH_VT8500
1366         default 288 if ARCH_ROCKCHIP
1367         default 264 if MACH_H4700
1368         default 0
1369         help
1370           Maximum number of GPIOs in the system.
1371
1372           If unsure, leave the default value.
1373
1374 config HZ_FIXED
1375         int
1376         default 200 if ARCH_EBSA110
1377         default 128 if SOC_AT91RM9200
1378         default 0
1379
1380 choice
1381         depends on HZ_FIXED = 0
1382         prompt "Timer frequency"
1383
1384 config HZ_100
1385         bool "100 Hz"
1386
1387 config HZ_200
1388         bool "200 Hz"
1389
1390 config HZ_250
1391         bool "250 Hz"
1392
1393 config HZ_300
1394         bool "300 Hz"
1395
1396 config HZ_500
1397         bool "500 Hz"
1398
1399 config HZ_1000
1400         bool "1000 Hz"
1401
1402 endchoice
1403
1404 config HZ
1405         int
1406         default HZ_FIXED if HZ_FIXED != 0
1407         default 100 if HZ_100
1408         default 200 if HZ_200
1409         default 250 if HZ_250
1410         default 300 if HZ_300
1411         default 500 if HZ_500
1412         default 1000
1413
1414 config SCHED_HRTICK
1415         def_bool HIGH_RES_TIMERS
1416
1417 config THUMB2_KERNEL
1418         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1419         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1420         default y if CPU_THUMBONLY
1421         select ARM_UNWIND
1422         help
1423           By enabling this option, the kernel will be compiled in
1424           Thumb-2 mode.
1425
1426           If unsure, say N.
1427
1428 config THUMB2_AVOID_R_ARM_THM_JUMP11
1429         bool "Work around buggy Thumb-2 short branch relocations in gas"
1430         depends on THUMB2_KERNEL && MODULES
1431         default y
1432         help
1433           Various binutils versions can resolve Thumb-2 branches to
1434           locally-defined, preemptible global symbols as short-range "b.n"
1435           branch instructions.
1436
1437           This is a problem, because there's no guarantee the final
1438           destination of the symbol, or any candidate locations for a
1439           trampoline, are within range of the branch.  For this reason, the
1440           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1441           relocation in modules at all, and it makes little sense to add
1442           support.
1443
1444           The symptom is that the kernel fails with an "unsupported
1445           relocation" error when loading some modules.
1446
1447           Until fixed tools are available, passing
1448           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1449           code which hits this problem, at the cost of a bit of extra runtime
1450           stack usage in some cases.
1451
1452           The problem is described in more detail at:
1453               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1454
1455           Only Thumb-2 kernels are affected.
1456
1457           Unless you are sure your tools don't have this problem, say Y.
1458
1459 config ARM_PATCH_IDIV
1460         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1461         depends on CPU_32v7 && !XIP_KERNEL
1462         default y
1463         help
1464           The ARM compiler inserts calls to __aeabi_idiv() and
1465           __aeabi_uidiv() when it needs to perform division on signed
1466           and unsigned integers. Some v7 CPUs have support for the sdiv
1467           and udiv instructions that can be used to implement those
1468           functions.
1469
1470           Enabling this option allows the kernel to modify itself to
1471           replace the first two instructions of these library functions
1472           with the sdiv or udiv plus "bx lr" instructions when the CPU
1473           it is running on supports them. Typically this will be faster
1474           and less power intensive than running the original library
1475           code to do integer division.
1476
1477 config AEABI
1478         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1479                 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1480         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1481         help
1482           This option allows for the kernel to be compiled using the latest
1483           ARM ABI (aka EABI).  This is only useful if you are using a user
1484           space environment that is also compiled with EABI.
1485
1486           Since there are major incompatibilities between the legacy ABI and
1487           EABI, especially with regard to structure member alignment, this
1488           option also changes the kernel syscall calling convention to
1489           disambiguate both ABIs and allow for backward compatibility support
1490           (selected with CONFIG_OABI_COMPAT).
1491
1492           To use this you need GCC version 4.0.0 or later.
1493
1494 config OABI_COMPAT
1495         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1496         depends on AEABI && !THUMB2_KERNEL
1497         help
1498           This option preserves the old syscall interface along with the
1499           new (ARM EABI) one. It also provides a compatibility layer to
1500           intercept syscalls that have structure arguments which layout
1501           in memory differs between the legacy ABI and the new ARM EABI
1502           (only for non "thumb" binaries). This option adds a tiny
1503           overhead to all syscalls and produces a slightly larger kernel.
1504
1505           The seccomp filter system will not be available when this is
1506           selected, since there is no way yet to sensibly distinguish
1507           between calling conventions during filtering.
1508
1509           If you know you'll be using only pure EABI user space then you
1510           can say N here. If this option is not selected and you attempt
1511           to execute a legacy ABI binary then the result will be
1512           UNPREDICTABLE (in fact it can be predicted that it won't work
1513           at all). If in doubt say N.
1514
1515 config ARCH_HAS_HOLES_MEMORYMODEL
1516         bool
1517
1518 config ARCH_SPARSEMEM_ENABLE
1519         bool
1520
1521 config ARCH_SPARSEMEM_DEFAULT
1522         def_bool ARCH_SPARSEMEM_ENABLE
1523
1524 config HAVE_ARCH_PFN_VALID
1525         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1526
1527 config HIGHMEM
1528         bool "High Memory Support"
1529         depends on MMU
1530         help
1531           The address space of ARM processors is only 4 Gigabytes large
1532           and it has to accommodate user address space, kernel address
1533           space as well as some memory mapped IO. That means that, if you
1534           have a large amount of physical memory and/or IO, not all of the
1535           memory can be "permanently mapped" by the kernel. The physical
1536           memory that is not permanently mapped is called "high memory".
1537
1538           Depending on the selected kernel/user memory split, minimum
1539           vmalloc space and actual amount of RAM, you may not need this
1540           option which should result in a slightly faster kernel.
1541
1542           If unsure, say n.
1543
1544 config HIGHPTE
1545         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1546         depends on HIGHMEM
1547         default y
1548         help
1549           The VM uses one page of physical memory for each page table.
1550           For systems with a lot of processes, this can use a lot of
1551           precious low memory, eventually leading to low memory being
1552           consumed by page tables.  Setting this option will allow
1553           user-space 2nd level page tables to reside in high memory.
1554
1555 config CPU_SW_DOMAIN_PAN
1556         bool "Enable use of CPU domains to implement privileged no-access"
1557         depends on MMU && !ARM_LPAE
1558         default y
1559         help
1560           Increase kernel security by ensuring that normal kernel accesses
1561           are unable to access userspace addresses.  This can help prevent
1562           use-after-free bugs becoming an exploitable privilege escalation
1563           by ensuring that magic values (such as LIST_POISON) will always
1564           fault when dereferenced.
1565
1566           CPUs with low-vector mappings use a best-efforts implementation.
1567           Their lower 1MB needs to remain accessible for the vectors, but
1568           the remainder of userspace will become appropriately inaccessible.
1569
1570 config HW_PERF_EVENTS
1571         def_bool y
1572         depends on ARM_PMU
1573
1574 config SYS_SUPPORTS_HUGETLBFS
1575        def_bool y
1576        depends on ARM_LPAE
1577
1578 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1579        def_bool y
1580        depends on ARM_LPAE
1581
1582 config ARCH_WANT_GENERAL_HUGETLB
1583         def_bool y
1584
1585 config ARM_MODULE_PLTS
1586         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1587         depends on MODULES
1588         default y
1589         help
1590           Allocate PLTs when loading modules so that jumps and calls whose
1591           targets are too far away for their relative offsets to be encoded
1592           in the instructions themselves can be bounced via veneers in the
1593           module's PLT. This allows modules to be allocated in the generic
1594           vmalloc area after the dedicated module memory area has been
1595           exhausted. The modules will use slightly more memory, but after
1596           rounding up to page size, the actual memory footprint is usually
1597           the same.
1598
1599           Disabling this is usually safe for small single-platform
1600           configurations. If unsure, say y.
1601
1602 config FORCE_MAX_ZONEORDER
1603         int "Maximum zone order"
1604         default "12" if SOC_AM33XX
1605         default "9" if SA1111 || ARCH_EFM32
1606         default "11"
1607         help
1608           The kernel memory allocator divides physically contiguous memory
1609           blocks into "zones", where each zone is a power of two number of
1610           pages.  This option selects the largest power of two that the kernel
1611           keeps in the memory allocator.  If you need to allocate very large
1612           blocks of physically contiguous memory, then you may need to
1613           increase this value.
1614
1615           This config option is actually maximum order plus one. For example,
1616           a value of 11 means that the largest free memory block is 2^10 pages.
1617
1618 config ALIGNMENT_TRAP
1619         bool
1620         depends on CPU_CP15_MMU
1621         default y if !ARCH_EBSA110
1622         select HAVE_PROC_CPU if PROC_FS
1623         help
1624           ARM processors cannot fetch/store information which is not
1625           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1626           address divisible by 4. On 32-bit ARM processors, these non-aligned
1627           fetch/store instructions will be emulated in software if you say
1628           here, which has a severe performance impact. This is necessary for
1629           correct operation of some network protocols. With an IP-only
1630           configuration it is safe to say N, otherwise say Y.
1631
1632 config UACCESS_WITH_MEMCPY
1633         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1634         depends on MMU
1635         default y if CPU_FEROCEON
1636         help
1637           Implement faster copy_to_user and clear_user methods for CPU
1638           cores where a 8-word STM instruction give significantly higher
1639           memory write throughput than a sequence of individual 32bit stores.
1640
1641           A possible side effect is a slight increase in scheduling latency
1642           between threads sharing the same address space if they invoke
1643           such copy operations with large buffers.
1644
1645           However, if the CPU data cache is using a write-allocate mode,
1646           this option is unlikely to provide any performance gain.
1647
1648 config SECCOMP
1649         bool
1650         prompt "Enable seccomp to safely compute untrusted bytecode"
1651         ---help---
1652           This kernel feature is useful for number crunching applications
1653           that may need to compute untrusted bytecode during their
1654           execution. By using pipes or other transports made available to
1655           the process as file descriptors supporting the read/write
1656           syscalls, it's possible to isolate those applications in
1657           their own address space using seccomp. Once seccomp is
1658           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1659           and the task is only allowed to execute a few safe syscalls
1660           defined by each seccomp mode.
1661
1662 config PARAVIRT
1663         bool "Enable paravirtualization code"
1664         help
1665           This changes the kernel so it can modify itself when it is run
1666           under a hypervisor, potentially improving performance significantly
1667           over full virtualization.
1668
1669 config PARAVIRT_TIME_ACCOUNTING
1670         bool "Paravirtual steal time accounting"
1671         select PARAVIRT
1672         help
1673           Select this option to enable fine granularity task steal time
1674           accounting. Time spent executing other tasks in parallel with
1675           the current vCPU is discounted from the vCPU power. To account for
1676           that, there can be a small performance impact.
1677
1678           If in doubt, say N here.
1679
1680 config XEN_DOM0
1681         def_bool y
1682         depends on XEN
1683
1684 config XEN
1685         bool "Xen guest support on ARM"
1686         depends on ARM && AEABI && OF
1687         depends on CPU_V7 && !CPU_V6
1688         depends on !GENERIC_ATOMIC64
1689         depends on MMU
1690         select ARCH_DMA_ADDR_T_64BIT
1691         select ARM_PSCI
1692         select SWIOTLB
1693         select SWIOTLB_XEN
1694         select PARAVIRT
1695         help
1696           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1697
1698 config STACKPROTECTOR_PER_TASK
1699         bool "Use a unique stack canary value for each task"
1700         depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1701         select GCC_PLUGIN_ARM_SSP_PER_TASK
1702         default y
1703         help
1704           Due to the fact that GCC uses an ordinary symbol reference from
1705           which to load the value of the stack canary, this value can only
1706           change at reboot time on SMP systems, and all tasks running in the
1707           kernel's address space are forced to use the same canary value for
1708           the entire duration that the system is up.
1709
1710           Enable this option to switch to a different method that uses a
1711           different canary value for each task.
1712
1713 endmenu
1714
1715 menu "Boot options"
1716
1717 config USE_OF
1718         bool "Flattened Device Tree support"
1719         select IRQ_DOMAIN
1720         select OF
1721         help
1722           Include support for flattened device tree machine descriptions.
1723
1724 config ATAGS
1725         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1726         default y
1727         help
1728           This is the traditional way of passing data to the kernel at boot
1729           time. If you are solely relying on the flattened device tree (or
1730           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1731           to remove ATAGS support from your kernel binary.  If unsure,
1732           leave this to y.
1733
1734 config DEPRECATED_PARAM_STRUCT
1735         bool "Provide old way to pass kernel parameters"
1736         depends on ATAGS
1737         help
1738           This was deprecated in 2001 and announced to live on for 5 years.
1739           Some old boot loaders still use this way.
1740
1741 # Compressed boot loader in ROM.  Yes, we really want to ask about
1742 # TEXT and BSS so we preserve their values in the config files.
1743 config ZBOOT_ROM_TEXT
1744         hex "Compressed ROM boot loader base address"
1745         default "0"
1746         help
1747           The physical address at which the ROM-able zImage is to be
1748           placed in the target.  Platforms which normally make use of
1749           ROM-able zImage formats normally set this to a suitable
1750           value in their defconfig file.
1751
1752           If ZBOOT_ROM is not enabled, this has no effect.
1753
1754 config ZBOOT_ROM_BSS
1755         hex "Compressed ROM boot loader BSS address"
1756         default "0"
1757         help
1758           The base address of an area of read/write memory in the target
1759           for the ROM-able zImage which must be available while the
1760           decompressor is running. It must be large enough to hold the
1761           entire decompressed kernel plus an additional 128 KiB.
1762           Platforms which normally make use of ROM-able zImage formats
1763           normally set this to a suitable value in their defconfig file.
1764
1765           If ZBOOT_ROM is not enabled, this has no effect.
1766
1767 config ZBOOT_ROM
1768         bool "Compressed boot loader in ROM/flash"
1769         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1770         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1771         help
1772           Say Y here if you intend to execute your compressed kernel image
1773           (zImage) directly from ROM or flash.  If unsure, say N.
1774
1775 config ARM_APPENDED_DTB
1776         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1777         depends on OF
1778         help
1779           With this option, the boot code will look for a device tree binary
1780           (DTB) appended to zImage
1781           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1782
1783           This is meant as a backward compatibility convenience for those
1784           systems with a bootloader that can't be upgraded to accommodate
1785           the documented boot protocol using a device tree.
1786
1787           Beware that there is very little in terms of protection against
1788           this option being confused by leftover garbage in memory that might
1789           look like a DTB header after a reboot if no actual DTB is appended
1790           to zImage.  Do not leave this option active in a production kernel
1791           if you don't intend to always append a DTB.  Proper passing of the
1792           location into r2 of a bootloader provided DTB is always preferable
1793           to this option.
1794
1795 config ARM_ATAG_DTB_COMPAT
1796         bool "Supplement the appended DTB with traditional ATAG information"
1797         depends on ARM_APPENDED_DTB
1798         help
1799           Some old bootloaders can't be updated to a DTB capable one, yet
1800           they provide ATAGs with memory configuration, the ramdisk address,
1801           the kernel cmdline string, etc.  Such information is dynamically
1802           provided by the bootloader and can't always be stored in a static
1803           DTB.  To allow a device tree enabled kernel to be used with such
1804           bootloaders, this option allows zImage to extract the information
1805           from the ATAG list and store it at run time into the appended DTB.
1806
1807 choice
1808         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1809         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1810
1811 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1812         bool "Use bootloader kernel arguments if available"
1813         help
1814           Uses the command-line options passed by the boot loader instead of
1815           the device tree bootargs property. If the boot loader doesn't provide
1816           any, the device tree bootargs property will be used.
1817
1818 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1819         bool "Extend with bootloader kernel arguments"
1820         help
1821           The command-line arguments provided by the boot loader will be
1822           appended to the the device tree bootargs property.
1823
1824 endchoice
1825
1826 config CMDLINE
1827         string "Default kernel command string"
1828         default ""
1829         help
1830           On some architectures (EBSA110 and CATS), there is currently no way
1831           for the boot loader to pass arguments to the kernel. For these
1832           architectures, you should supply some command-line options at build
1833           time by entering them here. As a minimum, you should specify the
1834           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1835
1836 choice
1837         prompt "Kernel command line type" if CMDLINE != ""
1838         default CMDLINE_FROM_BOOTLOADER
1839         depends on ATAGS
1840
1841 config CMDLINE_FROM_BOOTLOADER
1842         bool "Use bootloader kernel arguments if available"
1843         help
1844           Uses the command-line options passed by the boot loader. If
1845           the boot loader doesn't provide any, the default kernel command
1846           string provided in CMDLINE will be used.
1847
1848 config CMDLINE_EXTEND
1849         bool "Extend bootloader kernel arguments"
1850         help
1851           The command-line arguments provided by the boot loader will be
1852           appended to the default kernel command string.
1853
1854 config CMDLINE_FORCE
1855         bool "Always use the default kernel command string"
1856         help
1857           Always use the default kernel command string, even if the boot
1858           loader passes other arguments to the kernel.
1859           This is useful if you cannot or don't want to change the
1860           command-line options your boot loader passes to the kernel.
1861 endchoice
1862
1863 config XIP_KERNEL
1864         bool "Kernel Execute-In-Place from ROM"
1865         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1866         help
1867           Execute-In-Place allows the kernel to run from non-volatile storage
1868           directly addressable by the CPU, such as NOR flash. This saves RAM
1869           space since the text section of the kernel is not loaded from flash
1870           to RAM.  Read-write sections, such as the data section and stack,
1871           are still copied to RAM.  The XIP kernel is not compressed since
1872           it has to run directly from flash, so it will take more space to
1873           store it.  The flash address used to link the kernel object files,
1874           and for storing it, is configuration dependent. Therefore, if you
1875           say Y here, you must know the proper physical address where to
1876           store the kernel image depending on your own flash memory usage.
1877
1878           Also note that the make target becomes "make xipImage" rather than
1879           "make zImage" or "make Image".  The final kernel binary to put in
1880           ROM memory will be arch/arm/boot/xipImage.
1881
1882           If unsure, say N.
1883
1884 config XIP_PHYS_ADDR
1885         hex "XIP Kernel Physical Location"
1886         depends on XIP_KERNEL
1887         default "0x00080000"
1888         help
1889           This is the physical address in your flash memory the kernel will
1890           be linked for and stored to.  This address is dependent on your
1891           own flash usage.
1892
1893 config XIP_DEFLATED_DATA
1894         bool "Store kernel .data section compressed in ROM"
1895         depends on XIP_KERNEL
1896         select ZLIB_INFLATE
1897         help
1898           Before the kernel is actually executed, its .data section has to be
1899           copied to RAM from ROM. This option allows for storing that data
1900           in compressed form and decompressed to RAM rather than merely being
1901           copied, saving some precious ROM space. A possible drawback is a
1902           slightly longer boot delay.
1903
1904 config KEXEC
1905         bool "Kexec system call (EXPERIMENTAL)"
1906         depends on (!SMP || PM_SLEEP_SMP)
1907         depends on MMU
1908         select KEXEC_CORE
1909         help
1910           kexec is a system call that implements the ability to shutdown your
1911           current kernel, and to start another kernel.  It is like a reboot
1912           but it is independent of the system firmware.   And like a reboot
1913           you can start any kernel with it, not just Linux.
1914
1915           It is an ongoing process to be certain the hardware in a machine
1916           is properly shutdown, so do not be surprised if this code does not
1917           initially work for you.
1918
1919 config ATAGS_PROC
1920         bool "Export atags in procfs"
1921         depends on ATAGS && KEXEC
1922         default y
1923         help
1924           Should the atags used to boot the kernel be exported in an "atags"
1925           file in procfs. Useful with kexec.
1926
1927 config CRASH_DUMP
1928         bool "Build kdump crash kernel (EXPERIMENTAL)"
1929         help
1930           Generate crash dump after being started by kexec. This should
1931           be normally only set in special crash dump kernels which are
1932           loaded in the main kernel with kexec-tools into a specially
1933           reserved region and then later executed after a crash by
1934           kdump/kexec. The crash dump kernel must be compiled to a
1935           memory address not used by the main kernel
1936
1937           For more details see Documentation/admin-guide/kdump/kdump.rst
1938
1939 config AUTO_ZRELADDR
1940         bool "Auto calculation of the decompressed kernel image address"
1941         help
1942           ZRELADDR is the physical address where the decompressed kernel
1943           image will be placed. If AUTO_ZRELADDR is selected, the address
1944           will be determined at run-time by masking the current IP with
1945           0xf8000000. This assumes the zImage being placed in the first 128MB
1946           from start of memory.
1947
1948 config EFI_STUB
1949         bool
1950
1951 config EFI
1952         bool "UEFI runtime support"
1953         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1954         select UCS2_STRING
1955         select EFI_PARAMS_FROM_FDT
1956         select EFI_STUB
1957         select EFI_ARMSTUB
1958         select EFI_RUNTIME_WRAPPERS
1959         ---help---
1960           This option provides support for runtime services provided
1961           by UEFI firmware (such as non-volatile variables, realtime
1962           clock, and platform reset). A UEFI stub is also provided to
1963           allow the kernel to be booted as an EFI application. This
1964           is only useful for kernels that may run on systems that have
1965           UEFI firmware.
1966
1967 config DMI
1968         bool "Enable support for SMBIOS (DMI) tables"
1969         depends on EFI
1970         default y
1971         help
1972           This enables SMBIOS/DMI feature for systems.
1973
1974           This option is only useful on systems that have UEFI firmware.
1975           However, even with this option, the resultant kernel should
1976           continue to boot on existing non-UEFI platforms.
1977
1978           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1979           i.e., the the practice of identifying the platform via DMI to
1980           decide whether certain workarounds for buggy hardware and/or
1981           firmware need to be enabled. This would require the DMI subsystem
1982           to be enabled much earlier than we do on ARM, which is non-trivial.
1983
1984 endmenu
1985
1986 menu "CPU Power Management"
1987
1988 source "drivers/cpufreq/Kconfig"
1989
1990 source "drivers/cpuidle/Kconfig"
1991
1992 endmenu
1993
1994 menu "Floating point emulation"
1995
1996 comment "At least one emulation must be selected"
1997
1998 config FPE_NWFPE
1999         bool "NWFPE math emulation"
2000         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2001         ---help---
2002           Say Y to include the NWFPE floating point emulator in the kernel.
2003           This is necessary to run most binaries. Linux does not currently
2004           support floating point hardware so you need to say Y here even if
2005           your machine has an FPA or floating point co-processor podule.
2006
2007           You may say N here if you are going to load the Acorn FPEmulator
2008           early in the bootup.
2009
2010 config FPE_NWFPE_XP
2011         bool "Support extended precision"
2012         depends on FPE_NWFPE
2013         help
2014           Say Y to include 80-bit support in the kernel floating-point
2015           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2016           Note that gcc does not generate 80-bit operations by default,
2017           so in most cases this option only enlarges the size of the
2018           floating point emulator without any good reason.
2019
2020           You almost surely want to say N here.
2021
2022 config FPE_FASTFPE
2023         bool "FastFPE math emulation (EXPERIMENTAL)"
2024         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2025         ---help---
2026           Say Y here to include the FAST floating point emulator in the kernel.
2027           This is an experimental much faster emulator which now also has full
2028           precision for the mantissa.  It does not support any exceptions.
2029           It is very simple, and approximately 3-6 times faster than NWFPE.
2030
2031           It should be sufficient for most programs.  It may be not suitable
2032           for scientific calculations, but you have to check this for yourself.
2033           If you do not feel you need a faster FP emulation you should better
2034           choose NWFPE.
2035
2036 config VFP
2037         bool "VFP-format floating point maths"
2038         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2039         help
2040           Say Y to include VFP support code in the kernel. This is needed
2041           if your hardware includes a VFP unit.
2042
2043           Please see <file:Documentation/arm/vfp/release-notes.rst> for
2044           release notes and additional status information.
2045
2046           Say N if your target does not have VFP hardware.
2047
2048 config VFPv3
2049         bool
2050         depends on VFP
2051         default y if CPU_V7
2052
2053 config NEON
2054         bool "Advanced SIMD (NEON) Extension support"
2055         depends on VFPv3 && CPU_V7
2056         help
2057           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2058           Extension.
2059
2060 config KERNEL_MODE_NEON
2061         bool "Support for NEON in kernel mode"
2062         depends on NEON && AEABI
2063         help
2064           Say Y to include support for NEON in kernel mode.
2065
2066 endmenu
2067
2068 menu "Power management options"
2069
2070 source "kernel/power/Kconfig"
2071
2072 config ARCH_SUSPEND_POSSIBLE
2073         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2074                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2075         def_bool y
2076
2077 config ARM_CPU_SUSPEND
2078         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2079         depends on ARCH_SUSPEND_POSSIBLE
2080
2081 config ARCH_HIBERNATION_POSSIBLE
2082         bool
2083         depends on MMU
2084         default y if ARCH_SUSPEND_POSSIBLE
2085
2086 endmenu
2087
2088 source "drivers/firmware/Kconfig"
2089
2090 if CRYPTO
2091 source "arch/arm/crypto/Kconfig"
2092 endif