1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
15 depends on ARM64 && CC_IS_GCC
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMNS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
416 config SYS_THUMB_BUILD
417 bool "Build U-Boot using the Thumb instruction set"
420 Use this flag to build U-Boot using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config SPL_SYS_THUMB_BUILD
426 bool "Build SPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on !ARM64 && SPL
430 Use this flag to build SPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
435 config TPL_SYS_THUMB_BUILD
436 bool "Build TPL using the Thumb instruction set"
437 default y if SYS_THUMB_BUILD
438 depends on TPL && !ARM64
440 Use this flag to build TPL using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
446 bool "ARM PL310 L2 cache controller"
448 Enable support for ARM PL310 L2 cache controller in U-Boot
450 config SPL_SYS_L2_PL310
451 bool "ARM PL310 L2 cache controller in SPL"
453 Enable support for ARM PL310 L2 cache controller in SPL
455 config SYS_L2CACHE_OFF
458 If SoC does not support L2CACHE or one does not want to enable
459 L2CACHE, choose this option.
461 config ENABLE_ARM_SOC_BOOT0_HOOK
462 bool "prepare BOOT0 header"
464 If the SoC's BOOT0 requires a header area filled with (magic)
465 values, then choose this option, and create a file included as
466 <asm/arch/boot0.h> which contains the required assembler code.
468 config USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy"
471 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config SPL_USE_ARCH_MEMCPY
478 bool "Use an assembly optimized implementation of memcpy for SPL"
479 default y if USE_ARCH_MEMCPY
482 Enable the generation of an optimized version of memcpy.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config TPL_USE_ARCH_MEMCPY
487 bool "Use an assembly optimized implementation of memcpy for TPL"
488 default y if USE_ARCH_MEMCPY
491 Enable the generation of an optimized version of memcpy.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config USE_ARCH_MEMMOVE
496 bool "Use an assembly optimized implementation of memmove" if !ARM64
497 default USE_ARCH_MEMCPY if ARM64
500 Enable the generation of an optimized version of memmove.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SPL_USE_ARCH_MEMMOVE
505 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
506 default SPL_USE_ARCH_MEMCPY if ARM64
507 depends on SPL && ARM64
509 Enable the generation of an optimized version of memmove.
510 Such an implementation may be faster under some conditions
511 but may increase the binary size.
513 config TPL_USE_ARCH_MEMMOVE
514 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
515 default TPL_USE_ARCH_MEMCPY if ARM64
516 depends on TPL && ARM64
518 Enable the generation of an optimized version of memmove.
519 Such an implementation may be faster under some conditions
520 but may increase the binary size.
522 config USE_ARCH_MEMSET
523 bool "Use an assembly optimized implementation of memset"
525 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
527 Enable the generation of an optimized version of memset.
528 Such an implementation may be faster under some conditions
529 but may increase the binary size.
531 config SPL_USE_ARCH_MEMSET
532 bool "Use an assembly optimized implementation of memset for SPL"
533 default y if USE_ARCH_MEMSET
536 Enable the generation of an optimized version of memset.
537 Such an implementation may be faster under some conditions
538 but may increase the binary size.
540 config TPL_USE_ARCH_MEMSET
541 bool "Use an assembly optimized implementation of memset for TPL"
542 default y if USE_ARCH_MEMSET
545 Enable the generation of an optimized version of memset.
546 Such an implementation may be faster under some conditions
547 but may increase the binary size.
549 config ARM64_SUPPORT_AARCH32
550 bool "ARM64 system support AArch32 execution state"
552 default y if !TARGET_THUNDERX_88XX
554 This ARM64 system supports AArch32 execution state.
560 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
563 prompt "Target select"
568 select GPIO_EXTRA_HEADER
569 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
570 select SPL_SEPARATE_BSS if SPL
575 select GPIO_EXTRA_HEADER
576 select SPL_DM_SPI if SPL
579 Support for TI's DaVinci platform.
582 bool "Hisilicon HiSTB SoCs"
589 Support for HiSTB SoCs.
592 bool "Marvell Kirkwood"
593 select ARCH_MISC_INIT
594 select BOARD_EARLY_INIT_F
596 select GPIO_EXTRA_HEADER
600 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
601 select ARCH_EARLY_INIT_R if ARM64
606 select GPIO_EXTRA_HEADER
607 select SPL_DM_SPI if SPL
608 select SPL_DM_SPI_FLASH if SPL
609 select SPL_TIMER if SPL
610 select TIMER if !ARM64
619 select GPIO_EXTRA_HEADER
620 select SPL_SEPARATE_BSS if SPL
623 config TARGET_STV0991
624 bool "Support stv0991"
630 select GPIO_EXTRA_HEADER
637 bool "Broadcom BCM283X family"
641 select GPIO_EXTRA_HEADER
644 select SERIAL_SEARCH_ALL
649 bool "Broadcom BCM7XXX family"
652 select GPIO_EXTRA_HEADER
655 imply OF_HAS_PRIOR_STAGE
657 This enables support for Broadcom ARM-based set-top box
658 chipsets, including the 7445 family of chips.
661 bool "Broadcom broadband chip family"
666 config TARGET_VEXPRESS_CA9X4
667 bool "Support vexpress_ca9x4"
672 bool "Support Broadcom Northstar"
680 select ARM_GLOBAL_TIMER
681 imply SYS_THUMB_BUILD
684 imply NAND_BRCMNAND_IPROC
686 Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
687 ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
691 bool "Support Broadcom Northstar2"
693 select GPIO_EXTRA_HEADER
695 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
696 ARMv8 Cortex-A57 processors targeting a broad range of networking
700 bool "Support Broadcom NS3"
702 select BOARD_LATE_INIT
704 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
705 ARMv8 Cortex-A72 processors targeting a broad range of networking
709 bool "Samsung EXYNOS"
718 select GPIO_EXTRA_HEADER
719 imply SYS_THUMB_BUILD
724 bool "Samsung S5PC1XX"
730 select GPIO_EXTRA_HEADER
734 bool "Calxeda Highbank"
746 imply OF_HAS_PRIOR_STAGE
748 config ARCH_INTEGRATOR
749 bool "ARM Ltd. Integrator family"
752 select GPIO_EXTRA_HEADER
757 bool "Qualcomm IPQ40xx SoCs"
763 select GPIO_EXTRA_HEADER
777 select SYS_ARCH_TIMER
778 select SYS_THUMB_BUILD
784 bool "Texas Instruments' K3 Architecture"
789 select FIT_SIGNATURE if ARM64
790 imply TI_SECURE_DEVICE
792 config ARCH_OMAP2PLUS
795 select GPIO_EXTRA_HEADER
796 select SPL_BOARD_INIT if SPL
797 select SPL_STACK_R if SPL
799 imply TI_SYSC if DM && OF_CONTROL
801 imply SPL_SEPARATE_BSS
805 select GPIO_EXTRA_HEADER
806 imply DISTRO_DEFAULTS
809 Support for the Meson SoC family developed by Amlogic Inc.,
810 targeted at media players and tablet computers. We currently
811 support the S905 (GXBaby) 64-bit SoC.
816 select GPIO_EXTRA_HEADER
819 select SPL_LIBCOMMON_SUPPORT if SPL
820 select SPL_LIBGENERIC_SUPPORT if SPL
821 select SPL_OF_CONTROL if SPL
824 Support for the MediaTek SoCs family developed by MediaTek Inc.
825 Please refer to doc/README.mediatek for more information.
828 bool "NXP LPC32xx platform"
833 select GPIO_EXTRA_HEADER
839 bool "NXP i.MX8 platform"
841 select SYS_FSL_HAS_SEC
842 select SYS_FSL_SEC_COMPAT_4
843 select SYS_FSL_SEC_LE
846 select GPIO_EXTRA_HEADER
849 select ENABLE_ARM_SOC_BOOT0_HOOK
852 bool "NXP i.MX8M platform"
854 select GPIO_EXTRA_HEADER
856 select SYS_FSL_HAS_SEC
857 select SYS_FSL_SEC_COMPAT_4
858 select SYS_FSL_SEC_LE
861 select DM_EVENT if CLK
866 bool "NXP i.MX8ULP platform"
873 select GPIO_EXTRA_HEADER
879 bool "NXP i.MX9 platform"
885 select GPIO_EXTRA_HEADER
891 bool "NXP i.MXRT platform"
895 select GPIO_EXTRA_HEADER
901 bool "NXP i.MX23 family"
903 select GPIO_EXTRA_HEADER
908 bool "NXP i.MX28 family"
910 select GPIO_EXTRA_HEADER
915 bool "NXP i.MX31 family"
917 select GPIO_EXTRA_HEADER
922 select BOARD_POSTCLK_INIT
924 select GPIO_EXTRA_HEADER
926 select SYS_FSL_HAS_SEC
927 select SYS_FSL_SEC_COMPAT_4
928 select SYS_FSL_SEC_LE
929 select ROM_UNIFIED_SECTIONS
931 imply SYS_THUMB_BUILD
935 select ARCH_MISC_INIT
937 select GPIO_EXTRA_HEADER
940 select SYS_FSL_HAS_SEC
941 select SYS_FSL_SEC_COMPAT_4
942 select SYS_FSL_SEC_LE
943 imply BOARD_EARLY_INIT_F
945 imply SYS_THUMB_BUILD
949 select BOARD_POSTCLK_INIT
951 select GPIO_EXTRA_HEADER
954 select SYS_FSL_HAS_SEC
955 select SYS_FSL_SEC_COMPAT_4
956 select SYS_FSL_SEC_LE
957 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
959 imply SYS_THUMB_BUILD
960 imply SPL_SEPARATE_BSS
964 select BOARD_EARLY_INIT_F
966 select GPIO_EXTRA_HEADER
971 bool "Nexell S5P4418/S5P6818 SoC"
972 select ENABLE_ARM_SOC_BOOT0_HOOK
974 select GPIO_EXTRA_HEADER
977 bool "Support Nuvoton SoCs"
998 select LINUX_KERNEL_IMAGE_HEADER
999 select OF_BOARD_SETUP
1004 select POSITION_INDEPENDENT
1010 select SYSRESET_WATCHDOG
1011 select SYSRESET_WATCHDOG_AUTO
1015 imply DISTRO_DEFAULTS
1016 imply OF_HAS_PRIOR_STAGE
1019 bool "Actions Semi OWL SoCs"
1022 select GPIO_EXTRA_HEADER
1027 select SYS_RELOC_GD_ENV_ADDR
1031 bool "QEMU Virtual Platform"
1040 imply OF_HAS_PRIOR_STAGE
1043 imply SYS_WHITE_ON_BLACK
1044 imply SYS_CONSOLE_IS_IN_ENV
1045 imply PRE_CONSOLE_BUFFER
1053 bool "Renesas ARM SoCs"
1056 select GPIO_EXTRA_HEADER
1057 imply BOARD_EARLY_INIT_F
1060 imply SYS_THUMB_BUILD
1061 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1063 config ARCH_SNAPDRAGON
1064 bool "Qualcomm Snapdragon SoCs"
1069 select GPIO_EXTRA_HEADER
1078 bool "Altera SOCFPGA family"
1079 select ARCH_EARLY_INIT_R
1080 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1081 select ARM64 if TARGET_SOCFPGA_SOC64
1082 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1086 select GPIO_EXTRA_HEADER
1087 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1089 select SPL_DM_RESET if DM_RESET
1090 select SPL_DM_SERIAL
1091 select SPL_LIBCOMMON_SUPPORT
1092 select SPL_LIBGENERIC_SUPPORT
1093 select SPL_OF_CONTROL
1094 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1100 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1102 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1103 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1113 imply SPL_DM_SPI_FLASH
1114 imply SPL_LIBDISK_SUPPORT
1116 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1117 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1118 imply SPL_SPI_FLASH_SUPPORT
1123 bool "Support sunxi (Allwinner) SoCs"
1126 select CMD_MMC if MMC
1127 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1131 select DM_I2C if I2C
1132 select DM_SPI if SPI
1133 select DM_SPI_FLASH if SPI
1135 select DM_MMC if MMC
1137 select OF_BOARD_SETUP
1141 select SPECIFY_CONSOLE_INDEX
1142 select SPL_SEPARATE_BSS if SPL
1143 select SPL_STACK_R if SPL
1144 select SPL_SYS_MALLOC_SIMPLE if SPL
1145 select SPL_SYS_THUMB_BUILD if !ARM64
1148 select SYS_THUMB_BUILD if !ARM64
1149 select USB if DISTRO_DEFAULTS
1150 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1151 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1152 select SPL_USE_TINY_PRINTF
1154 select SYS_RELOC_GD_ENV_ADDR
1155 imply BOARD_LATE_INIT
1158 imply CMD_UBI if MTD_RAW_NAND
1159 imply DISTRO_DEFAULTS
1161 imply DM_REGULATOR_FIXED
1164 imply OF_LIBFDT_OVERLAY
1165 imply PRE_CONSOLE_BUFFER
1167 imply SPL_LIBCOMMON_SUPPORT
1168 imply SPL_LIBGENERIC_SUPPORT
1169 imply SPL_MMC if MMC
1173 imply SYSRESET_WATCHDOG
1174 imply SYSRESET_WATCHDOG_AUTO
1179 bool "ST-Ericsson U8500 Series"
1183 select DM_MMC if MMC
1185 select DM_USB_GADGET if DM_USB
1189 imply AB8500_USB_PHY
1190 imply ARM_PL180_MMCI
1195 imply NOMADIK_MTU_TIMER
1200 imply SYS_THUMB_BUILD
1201 imply SYSRESET_SYSCON
1204 bool "Support Xilinx Versal Platform"
1208 select DM_MMC if MMC
1213 imply BOARD_LATE_INIT
1214 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1216 config ARCH_VERSAL_NET
1217 bool "Support Xilinx Versal NET Platform"
1221 select DM_MMC if MMC
1224 imply BOARD_LATE_INIT
1225 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1228 bool "Freescale Vybrid"
1230 select GPIO_EXTRA_HEADER
1231 select IOMUX_SHARE_CONF_REG
1233 select SYS_FSL_ERRATUM_ESDHC111
1238 bool "Xilinx Zynq based platform"
1239 select ARM_TWD_TIMER
1240 select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
1244 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1246 select DM_MMC if MMC
1252 select SPL_BOARD_INIT if SPL
1253 select SPL_CLK if SPL
1254 select SPL_DM if SPL
1255 select SPL_DM_SPI if SPL
1256 select SPL_DM_SPI_FLASH if SPL
1257 select SPL_OF_CONTROL if SPL
1258 select SPL_SEPARATE_BSS if SPL
1259 select SPL_TIMER if SPL
1262 imply BOARD_LATE_INIT
1266 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1269 config ARCH_ZYNQMP_R5
1270 bool "Xilinx ZynqMP R5 based platform"
1274 select DM_MMC if MMC
1281 bool "Xilinx ZynqMP based platform"
1285 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1287 select DM_MMC if MMC
1289 select DM_SPI if SPI
1290 select DM_SPI_FLASH if DM_SPI
1294 select SPL_BOARD_INIT if SPL
1295 select SPL_CLK if SPL
1296 select SPL_DM if SPL
1297 select SPL_DM_SPI if SPI && SPL_DM
1298 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1299 select SPL_DM_MAILBOX if SPL
1300 imply SPL_FIRMWARE if SPL
1301 select SPL_SEPARATE_BSS if SPL
1303 imply ZYNQMP_IPI if DM_MAILBOX
1305 imply BOARD_LATE_INIT
1307 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1311 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1315 select GPIO_EXTRA_HEADER
1316 imply DISTRO_DEFAULTS
1318 imply SPL_TIMER if SPL
1320 config ARCH_VEXPRESS64
1321 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1329 select MTD_NOR_FLASH if MTD
1330 select FLASH_CFI_DRIVER if MTD
1331 select ENV_IS_IN_FLASH if MTD
1332 imply DISTRO_DEFAULTS
1334 config TARGET_CORSTONE1000
1335 bool "Support Corstone1000 Platform"
1340 config TARGET_TOTAL_COMPUTE
1341 bool "Support Total Compute Platform"
1349 config TARGET_LS2080A_EMU
1350 bool "Support ls2080a_emu"
1353 select ARMV8_MULTIENTRY
1354 select FSL_DDR_SYNC_REFRESH
1355 select GPIO_EXTRA_HEADER
1357 Support for Freescale LS2080A_EMU platform.
1358 The LS2080A Development System (EMULATOR) is a pre-silicon
1359 development platform that supports the QorIQ LS2080A
1360 Layerscape Architecture processor.
1362 config TARGET_LS1088AQDS
1363 bool "Support ls1088aqds"
1366 select ARMV8_MULTIENTRY
1367 select ARCH_SUPPORT_TFABOOT
1368 select BOARD_LATE_INIT
1369 select GPIO_EXTRA_HEADER
1371 select FSL_DDR_INTERACTIVE if !SD_BOOT
1373 Support for NXP LS1088AQDS platform.
1374 The LS1088A Development System (QDS) is a high-performance
1375 development platform that supports the QorIQ LS1088A
1376 Layerscape Architecture processor.
1378 config TARGET_LS2080AQDS
1379 bool "Support ls2080aqds"
1382 select ARMV8_MULTIENTRY
1383 select ARCH_SUPPORT_TFABOOT
1384 select BOARD_LATE_INIT
1385 select GPIO_EXTRA_HEADER
1390 select FSL_DDR_INTERACTIVE if !SPL
1392 Support for Freescale LS2080AQDS platform.
1393 The LS2080A Development System (QDS) is a high-performance
1394 development platform that supports the QorIQ LS2080A
1395 Layerscape Architecture processor.
1397 config TARGET_LS2080ARDB
1398 bool "Support ls2080ardb"
1401 select ARMV8_MULTIENTRY
1402 select ARCH_SUPPORT_TFABOOT
1403 select BOARD_LATE_INIT
1406 select FSL_DDR_INTERACTIVE if !SPL
1407 select GPIO_EXTRA_HEADER
1411 Support for Freescale LS2080ARDB platform.
1412 The LS2080A Reference design board (RDB) is a high-performance
1413 development platform that supports the QorIQ LS2080A
1414 Layerscape Architecture processor.
1416 config TARGET_LS2081ARDB
1417 bool "Support ls2081ardb"
1420 select ARMV8_MULTIENTRY
1421 select BOARD_LATE_INIT
1422 select GPIO_EXTRA_HEADER
1425 Support for Freescale LS2081ARDB platform.
1426 The LS2081A Reference design board (RDB) is a high-performance
1427 development platform that supports the QorIQ LS2081A/LS2041A
1428 Layerscape Architecture processor.
1430 config TARGET_LX2160ARDB
1431 bool "Support lx2160ardb"
1434 select ARMV8_MULTIENTRY
1435 select ARCH_SUPPORT_TFABOOT
1436 select BOARD_LATE_INIT
1437 select GPIO_EXTRA_HEADER
1439 Support for NXP LX2160ARDB platform.
1440 The lx2160ardb (LX2160A Reference design board (RDB)
1441 is a high-performance development platform that supports the
1442 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1444 config TARGET_LX2160AQDS
1445 bool "Support lx2160aqds"
1448 select ARMV8_MULTIENTRY
1449 select ARCH_SUPPORT_TFABOOT
1450 select BOARD_LATE_INIT
1451 select GPIO_EXTRA_HEADER
1453 Support for NXP LX2160AQDS platform.
1454 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1455 is a high-performance development platform that supports the
1456 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1458 config TARGET_LX2162AQDS
1459 bool "Support lx2162aqds"
1461 select ARCH_MISC_INIT
1463 select ARMV8_MULTIENTRY
1464 select ARCH_SUPPORT_TFABOOT
1465 select BOARD_LATE_INIT
1466 select GPIO_EXTRA_HEADER
1468 Support for NXP LX2162AQDS platform.
1469 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1472 bool "Support HiKey 96boards Consumer Edition Platform"
1477 select GPIO_EXTRA_HEADER
1480 select SPECIFY_CONSOLE_INDEX
1483 Support for HiKey 96boards platform. It features a HI6220
1484 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1486 config TARGET_HIKEY960
1487 bool "Support HiKey960 96boards Consumer Edition Platform"
1491 select GPIO_EXTRA_HEADER
1496 Support for HiKey960 96boards platform. It features a HI3660
1497 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1499 config TARGET_POPLAR
1500 bool "Support Poplar 96boards Enterprise Edition Platform"
1504 select GPIO_EXTRA_HEADER
1509 Support for Poplar 96boards EE platform. It features a HI3798cv200
1510 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1511 making it capable of running any commercial set-top solution based on
1514 config TARGET_LS1012AQDS
1515 bool "Support ls1012aqds"
1518 select ARCH_SUPPORT_TFABOOT
1519 select BOARD_LATE_INIT
1520 select GPIO_EXTRA_HEADER
1522 Support for Freescale LS1012AQDS platform.
1523 The LS1012A Development System (QDS) is a high-performance
1524 development platform that supports the QorIQ LS1012A
1525 Layerscape Architecture processor.
1527 config TARGET_LS1012ARDB
1528 bool "Support ls1012ardb"
1531 select ARCH_SUPPORT_TFABOOT
1532 select BOARD_LATE_INIT
1533 select GPIO_EXTRA_HEADER
1537 Support for Freescale LS1012ARDB platform.
1538 The LS1012A Reference design board (RDB) is a high-performance
1539 development platform that supports the QorIQ LS1012A
1540 Layerscape Architecture processor.
1542 config TARGET_LS1012A2G5RDB
1543 bool "Support ls1012a2g5rdb"
1546 select ARCH_SUPPORT_TFABOOT
1547 select BOARD_LATE_INIT
1548 select GPIO_EXTRA_HEADER
1551 Support for Freescale LS1012A2G5RDB platform.
1552 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1553 development platform that supports the QorIQ LS1012A
1554 Layerscape Architecture processor.
1556 config TARGET_LS1012AFRWY
1557 bool "Support ls1012afrwy"
1560 select ARCH_SUPPORT_TFABOOT
1561 select BOARD_LATE_INIT
1562 select GPIO_EXTRA_HEADER
1566 Support for Freescale LS1012AFRWY platform.
1567 The LS1012A FRWY board (FRWY) is a high-performance
1568 development platform that supports the QorIQ LS1012A
1569 Layerscape Architecture processor.
1571 config TARGET_LS1012AFRDM
1572 bool "Support ls1012afrdm"
1575 select ARCH_SUPPORT_TFABOOT
1576 select GPIO_EXTRA_HEADER
1578 Support for Freescale LS1012AFRDM platform.
1579 The LS1012A Freedom board (FRDM) is a high-performance
1580 development platform that supports the QorIQ LS1012A
1581 Layerscape Architecture processor.
1583 config TARGET_LS1028AQDS
1584 bool "Support ls1028aqds"
1587 select ARMV8_MULTIENTRY
1588 select ARCH_SUPPORT_TFABOOT
1589 select BOARD_LATE_INIT
1590 select GPIO_EXTRA_HEADER
1592 Support for Freescale LS1028AQDS platform
1593 The LS1028A Development System (QDS) is a high-performance
1594 development platform that supports the QorIQ LS1028A
1595 Layerscape Architecture processor.
1597 config TARGET_LS1028ARDB
1598 bool "Support ls1028ardb"
1601 select ARMV8_MULTIENTRY
1602 select ARCH_SUPPORT_TFABOOT
1603 select BOARD_LATE_INIT
1604 select GPIO_EXTRA_HEADER
1606 Support for Freescale LS1028ARDB platform
1607 The LS1028A Development System (RDB) is a high-performance
1608 development platform that supports the QorIQ LS1028A
1609 Layerscape Architecture processor.
1611 config TARGET_LS1088ARDB
1612 bool "Support ls1088ardb"
1615 select ARMV8_MULTIENTRY
1616 select ARCH_SUPPORT_TFABOOT
1617 select BOARD_LATE_INIT
1619 select FSL_DDR_INTERACTIVE if !SD_BOOT
1620 select GPIO_EXTRA_HEADER
1622 Support for NXP LS1088ARDB platform.
1623 The LS1088A Reference design board (RDB) is a high-performance
1624 development platform that supports the QorIQ LS1088A
1625 Layerscape Architecture processor.
1627 config TARGET_LS1021AQDS
1628 bool "Support ls1021aqds"
1630 select ARCH_SUPPORT_PSCI
1631 select BOARD_EARLY_INIT_F
1632 select BOARD_LATE_INIT
1634 select CPU_V7_HAS_NONSEC
1635 select CPU_V7_HAS_VIRT
1636 select LS1_DEEP_SLEEP
1637 select PEN_ADDR_BIG_ENDIAN
1640 select FSL_DDR_INTERACTIVE
1641 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1642 select GPIO_EXTRA_HEADER
1643 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1646 config TARGET_LS1021ATWR
1647 bool "Support ls1021atwr"
1649 select ARCH_SUPPORT_PSCI
1650 select BOARD_EARLY_INIT_F
1651 select BOARD_LATE_INIT
1653 select CPU_V7_HAS_NONSEC
1654 select CPU_V7_HAS_VIRT
1655 select LS1_DEEP_SLEEP
1656 select PEN_ADDR_BIG_ENDIAN
1658 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1659 select GPIO_EXTRA_HEADER
1662 config TARGET_PG_WCOM_SELI8
1663 bool "Support Hitachi-Powergrids SELI8 service unit card"
1665 select ARCH_SUPPORT_PSCI
1666 select BOARD_EARLY_INIT_F
1667 select BOARD_LATE_INIT
1669 select CPU_V7_HAS_NONSEC
1670 select CPU_V7_HAS_VIRT
1672 select FSL_DDR_INTERACTIVE
1673 select GPIO_EXTRA_HEADER
1677 Support for Hitachi-Powergrids SELI8 service unit card.
1678 SELI8 is a QorIQ LS1021a based service unit card used
1679 in XMC20 and FOX615 product families.
1681 config TARGET_PG_WCOM_EXPU1
1682 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1684 select ARCH_SUPPORT_PSCI
1685 select BOARD_EARLY_INIT_F
1686 select BOARD_LATE_INIT
1688 select CPU_V7_HAS_NONSEC
1689 select CPU_V7_HAS_VIRT
1691 select FSL_DDR_INTERACTIVE
1695 Support for Hitachi-Powergrids EXPU1 service unit card.
1696 EXPU1 is a QorIQ LS1021a based service unit card used
1697 in XMC20 and FOX615 product families.
1699 config TARGET_LS1021ATSN
1700 bool "Support ls1021atsn"
1702 select ARCH_SUPPORT_PSCI
1703 select BOARD_EARLY_INIT_F
1704 select BOARD_LATE_INIT
1706 select CPU_V7_HAS_NONSEC
1707 select CPU_V7_HAS_VIRT
1708 select LS1_DEEP_SLEEP
1710 select GPIO_EXTRA_HEADER
1713 config TARGET_LS1021AIOT
1714 bool "Support ls1021aiot"
1716 select ARCH_SUPPORT_PSCI
1717 select BOARD_LATE_INIT
1719 select CPU_V7_HAS_NONSEC
1720 select CPU_V7_HAS_VIRT
1721 select PEN_ADDR_BIG_ENDIAN
1723 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1724 select GPIO_EXTRA_HEADER
1727 Support for Freescale LS1021AIOT platform.
1728 The LS1021A Freescale board (IOT) is a high-performance
1729 development platform that supports the QorIQ LS1021A
1730 Layerscape Architecture processor.
1732 config TARGET_LS1043AQDS
1733 bool "Support ls1043aqds"
1736 select ARMV8_MULTIENTRY
1737 select ARCH_SUPPORT_TFABOOT
1738 select BOARD_EARLY_INIT_F
1739 select BOARD_LATE_INIT
1741 select FSL_DDR_INTERACTIVE if !SPL
1742 select FSL_DSPI if !SPL_NO_DSPI
1743 select DM_SPI_FLASH if FSL_DSPI
1744 select GPIO_EXTRA_HEADER
1748 Support for Freescale LS1043AQDS platform.
1750 config TARGET_LS1043ARDB
1751 bool "Support ls1043ardb"
1754 select ARMV8_MULTIENTRY
1755 select ARCH_SUPPORT_TFABOOT
1756 select BOARD_EARLY_INIT_F
1757 select BOARD_LATE_INIT
1759 select FSL_DSPI if !SPL_NO_DSPI
1760 select DM_SPI_FLASH if FSL_DSPI
1761 select GPIO_EXTRA_HEADER
1763 Support for Freescale LS1043ARDB platform.
1765 config TARGET_LS1046AQDS
1766 bool "Support ls1046aqds"
1769 select ARMV8_MULTIENTRY
1770 select ARCH_SUPPORT_TFABOOT
1771 select BOARD_EARLY_INIT_F
1772 select BOARD_LATE_INIT
1773 select DM_SPI_FLASH if DM_SPI
1775 select FSL_DDR_BIST if !SPL
1776 select FSL_DDR_INTERACTIVE if !SPL
1777 select FSL_DDR_INTERACTIVE if !SPL
1778 select GPIO_EXTRA_HEADER
1781 Support for Freescale LS1046AQDS platform.
1782 The LS1046A Development System (QDS) is a high-performance
1783 development platform that supports the QorIQ LS1046A
1784 Layerscape Architecture processor.
1786 config TARGET_LS1046ARDB
1787 bool "Support ls1046ardb"
1790 select ARMV8_MULTIENTRY
1791 select ARCH_SUPPORT_TFABOOT
1792 select BOARD_EARLY_INIT_F
1793 select BOARD_LATE_INIT
1794 select DM_SPI_FLASH if DM_SPI
1795 select POWER_MC34VR500
1798 select FSL_DDR_INTERACTIVE if !SPL
1799 select GPIO_EXTRA_HEADER
1802 Support for Freescale LS1046ARDB platform.
1803 The LS1046A Reference Design Board (RDB) is a high-performance
1804 development platform that supports the QorIQ LS1046A
1805 Layerscape Architecture processor.
1807 config TARGET_LS1046AFRWY
1808 bool "Support ls1046afrwy"
1811 select ARMV8_MULTIENTRY
1812 select ARCH_SUPPORT_TFABOOT
1813 select BOARD_EARLY_INIT_F
1814 select BOARD_LATE_INIT
1815 select DM_SPI_FLASH if DM_SPI
1816 select GPIO_EXTRA_HEADER
1819 Support for Freescale LS1046AFRWY platform.
1820 The LS1046A Freeway Board (FRWY) is a high-performance
1821 development platform that supports the QorIQ LS1046A
1822 Layerscape Architecture processor.
1828 select ARMV8_MULTIENTRY
1843 select GPIO_EXTRA_HEADER
1844 select SPL_DM if SPL
1845 select SPL_DM_SPI if SPL
1846 select SPL_DM_SPI_FLASH if SPL
1847 select SPL_DM_I2C if SPL
1848 select SPL_DM_MMC if SPL
1849 select SPL_DM_SERIAL if SPL
1851 Support for Kontron SMARC-sAL28 board.
1854 bool "Support ten64"
1856 select ARCH_MISC_INIT
1858 select ARMV8_MULTIENTRY
1859 select ARCH_SUPPORT_TFABOOT
1860 select BOARD_LATE_INIT
1862 select FSL_DDR_INTERACTIVE if !SD_BOOT
1863 select GPIO_EXTRA_HEADER
1865 Support for Traverse Technologies Ten64 board, based
1868 config ARCH_UNIPHIER
1869 bool "Socionext UniPhier SoCs"
1870 select BOARD_LATE_INIT
1878 select OF_BOARD_SETUP
1882 select SPL_BOARD_INIT if SPL
1883 select SPL_DM if SPL
1884 select SPL_LIBCOMMON_SUPPORT if SPL
1885 select SPL_LIBGENERIC_SUPPORT if SPL
1886 select SPL_OF_CONTROL if SPL
1887 select SPL_PINCTRL if SPL
1890 imply DISTRO_DEFAULTS
1893 Support for UniPhier SoC family developed by Socionext Inc.
1894 (formerly, System LSI Business Division of Panasonic Corporation)
1896 config ARCH_SYNQUACER
1897 bool "Socionext SynQuacer SoCs"
1903 select SYSRESET_PSCI
1906 Support for SynQuacer SoC family developed by Socionext Inc.
1907 This SoC is used on 96boards EE DeveloperBox.
1910 bool "Support STMicroelectronics STM32 MCU with cortex M"
1917 bool "Support STMicroelectronics SoCs"
1926 Support for STMicroelectronics STiH407/10 SoC family.
1927 This SoC is used on Linaro 96Board STiH410-B2260
1930 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1931 select ARCH_MISC_INIT
1932 select ARCH_SUPPORT_TFABOOT
1933 select BOARD_LATE_INIT
1942 select OF_SYSTEM_SETUP
1947 select SYS_THUMB_BUILD if !ARM64
1951 imply OF_LIBFDT_OVERLAY
1952 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1956 Support for STM32MP SoC family developed by STMicroelectronics,
1957 MPUs based on ARM cortex A core
1958 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1959 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1961 SPL is the unsecure FSBL for the basic boot chain.
1963 config ARCH_ROCKCHIP
1964 bool "Support Rockchip SoCs"
1966 select BINMAN if SPL_OPTEE || SPL
1976 select ENABLE_ARM_SOC_BOOT0_HOOK
1979 select SPL_DM if SPL
1980 select SPL_DM_SPI if SPL
1981 select SPL_DM_SPI_FLASH if SPL
1983 select SYS_THUMB_BUILD if !ARM64
1986 imply DEBUG_UART_BOARD_INIT
1987 imply BOOTSTD_DEFAULTS
1989 imply SARADC_ROCKCHIP
1991 imply SPL_SYS_MALLOC_SIMPLE
1994 imply USB_FUNCTION_FASTBOOT
1996 config ARCH_OCTEONTX
1997 bool "Support OcteonTX SoCs"
2000 select GPIO_EXTRA_HEADER
2004 select BOARD_LATE_INIT
2005 select SYS_CACHE_SHIFT_7
2006 select SYS_PCI_64BIT if PCI
2007 imply OF_HAS_PRIOR_STAGE
2009 config ARCH_OCTEONTX2
2010 bool "Support OcteonTX2 SoCs"
2013 select GPIO_EXTRA_HEADER
2017 select BOARD_LATE_INIT
2018 select SYS_CACHE_SHIFT_7
2019 select SYS_PCI_64BIT if PCI
2020 imply OF_HAS_PRIOR_STAGE
2022 config TARGET_THUNDERX_88XX
2023 bool "Support ThunderX 88xx"
2025 select GPIO_EXTRA_HEADER
2028 select SYS_CACHE_SHIFT_7
2031 bool "Support Aspeed SoCs"
2036 config TARGET_DURIAN
2037 bool "Support Phytium Durian Platform"
2039 select GPIO_EXTRA_HEADER
2041 Support for durian platform.
2042 It has 2GB Sdram, uart and pcie.
2044 config TARGET_POMELO
2045 bool "Support Phytium Pomelo Platform"
2058 Support for pomelo platform.
2059 It has 8GB Sdram, uart and pcie.
2061 config TARGET_PRESIDIO_ASIC
2062 bool "Support Cortina Presidio ASIC Platform"
2066 config TARGET_XENGUEST_ARM64
2067 bool "Xen guest ARM64"
2071 select LINUX_KERNEL_IMAGE_HEADER
2073 imply OF_HAS_PRIOR_STAGE
2076 bool "Support HPE GXP SoCs"
2083 config SUPPORT_PASSING_ATAGS
2084 bool "Support pre-devicetree ATAG-based booting"
2086 imply SETUP_MEMORY_TAGS
2088 Support for booting older Linux kernels, using ATAGs rather than
2089 passing a devicetree. This is option is rarely used, and the
2090 semantics are defined at
2091 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2093 config SETUP_MEMORY_TAGS
2094 bool "Pass memory size information via ATAG"
2095 depends on SUPPORT_PASSING_ATAGS
2098 bool "Pass Linux kernel cmdline via ATAG"
2099 depends on SUPPORT_PASSING_ATAGS
2102 bool "Pass initrd starting point and size via ATAG"
2103 depends on SUPPORT_PASSING_ATAGS
2106 bool "Pass system revision via ATAG"
2107 depends on SUPPORT_PASSING_ATAGS
2110 bool "Pass system serial number via ATAG"
2111 depends on SUPPORT_PASSING_ATAGS
2113 config STATIC_MACH_TYPE
2114 bool "Statically define the Machine ID number"
2115 default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2117 When booting via ATAGs, enable this option if we know the correct
2118 machine ID number to use at compile time. Some systems will be
2119 passed the number dynamically by whatever loads U-Boot.
2122 int "Machine ID number"
2123 depends on STATIC_MACH_TYPE
2124 default 527 if TARGET_DS109
2125 default 3036 if TARGET_DS414
2126 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2128 When booting via ATAGs, the machine type must be passed as a number.
2129 For the full list see https://www.arm.linux.org.uk/developer/machines
2131 config ARCH_SUPPORT_TFABOOT
2135 bool "Support for booting from TF-A"
2136 depends on ARCH_SUPPORT_TFABOOT
2138 Some platforms support the setup of secure registers (for instance
2139 for CPU errata handling) or provide secure services like PSCI.
2140 Those services could also be provided by other firmware parts
2141 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2142 does not need to (and cannot) execute this code.
2143 Enabling this option will make a U-Boot binary that is relying
2144 on other firmware layers to provide secure functionality.
2146 config TI_SECURE_DEVICE
2147 bool "HS Device Type Support"
2148 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2150 If a high secure (HS) device type is being used, this config
2151 must be set. This option impacts various aspects of the
2152 build system (to create signed boot images that can be
2153 authenticated) and the code. See the doc/README.ti-secure
2154 file for further details.
2156 config SYS_KWD_CONFIG
2157 string "kwbimage config file path"
2158 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2159 default "arch/arm/mach-mvebu/kwbimage.cfg"
2161 Path within the source directory to the kwbimage.cfg file to use
2162 when packaging the U-Boot image for use.
2164 source "arch/arm/mach-apple/Kconfig"
2166 source "arch/arm/mach-aspeed/Kconfig"
2168 source "arch/arm/mach-at91/Kconfig"
2170 source "arch/arm/mach-bcm283x/Kconfig"
2172 source "arch/arm/mach-bcmbca/Kconfig"
2174 source "arch/arm/mach-bcmstb/Kconfig"
2176 source "arch/arm/mach-davinci/Kconfig"
2178 source "arch/arm/mach-exynos/Kconfig"
2180 source "arch/arm/mach-hpe/gxp/Kconfig"
2182 source "arch/arm/mach-highbank/Kconfig"
2184 source "arch/arm/mach-histb/Kconfig"
2186 source "arch/arm/mach-integrator/Kconfig"
2188 source "arch/arm/mach-ipq40xx/Kconfig"
2190 source "arch/arm/mach-k3/Kconfig"
2192 source "arch/arm/mach-keystone/Kconfig"
2194 source "arch/arm/mach-kirkwood/Kconfig"
2196 source "arch/arm/mach-lpc32xx/Kconfig"
2198 source "arch/arm/mach-mvebu/Kconfig"
2200 source "arch/arm/mach-octeontx/Kconfig"
2202 source "arch/arm/mach-octeontx2/Kconfig"
2204 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2206 source "arch/arm/mach-imx/mx3/Kconfig"
2208 source "arch/arm/mach-imx/mx5/Kconfig"
2210 source "arch/arm/mach-imx/mx6/Kconfig"
2212 source "arch/arm/mach-imx/mx7/Kconfig"
2214 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2216 source "arch/arm/mach-imx/imx8/Kconfig"
2218 source "arch/arm/mach-imx/imx8m/Kconfig"
2220 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2222 source "arch/arm/mach-imx/imx9/Kconfig"
2224 source "arch/arm/mach-imx/imxrt/Kconfig"
2226 source "arch/arm/mach-imx/mxs/Kconfig"
2228 source "arch/arm/mach-omap2/Kconfig"
2230 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2232 source "arch/arm/mach-orion5x/Kconfig"
2234 source "arch/arm/mach-owl/Kconfig"
2236 source "arch/arm/mach-rmobile/Kconfig"
2238 source "arch/arm/mach-meson/Kconfig"
2240 source "arch/arm/mach-mediatek/Kconfig"
2242 source "arch/arm/mach-qemu/Kconfig"
2244 source "arch/arm/mach-rockchip/Kconfig"
2246 source "arch/arm/mach-s5pc1xx/Kconfig"
2248 source "arch/arm/mach-snapdragon/Kconfig"
2250 source "arch/arm/mach-socfpga/Kconfig"
2252 source "arch/arm/mach-sti/Kconfig"
2254 source "arch/arm/mach-stm32/Kconfig"
2256 source "arch/arm/mach-stm32mp/Kconfig"
2258 source "arch/arm/mach-sunxi/Kconfig"
2260 source "arch/arm/mach-tegra/Kconfig"
2262 source "arch/arm/mach-u8500/Kconfig"
2264 source "arch/arm/mach-uniphier/Kconfig"
2266 source "arch/arm/cpu/armv7/vf610/Kconfig"
2268 source "arch/arm/mach-zynq/Kconfig"
2270 source "arch/arm/mach-zynqmp/Kconfig"
2272 source "arch/arm/mach-versal/Kconfig"
2274 source "arch/arm/mach-versal-net/Kconfig"
2276 source "arch/arm/mach-zynqmp-r5/Kconfig"
2278 source "arch/arm/cpu/armv7/Kconfig"
2280 source "arch/arm/cpu/armv8/Kconfig"
2282 source "arch/arm/mach-imx/Kconfig"
2284 source "arch/arm/mach-nexell/Kconfig"
2286 source "arch/arm/mach-npcm/Kconfig"
2288 source "board/armltd/total_compute/Kconfig"
2289 source "board/armltd/corstone1000/Kconfig"
2290 source "board/bosch/shc/Kconfig"
2291 source "board/bosch/guardian/Kconfig"
2292 source "board/Marvell/octeontx/Kconfig"
2293 source "board/Marvell/octeontx2/Kconfig"
2294 source "board/armltd/vexpress/Kconfig"
2295 source "board/armltd/vexpress64/Kconfig"
2296 source "board/cortina/presidio-asic/Kconfig"
2297 source "board/broadcom/bcmns/Kconfig"
2298 source "board/broadcom/bcmns3/Kconfig"
2299 source "board/cavium/thunderx/Kconfig"
2300 source "board/eets/pdu001/Kconfig"
2301 source "board/emulation/qemu-arm/Kconfig"
2302 source "board/freescale/ls2080aqds/Kconfig"
2303 source "board/freescale/ls2080ardb/Kconfig"
2304 source "board/freescale/ls1088a/Kconfig"
2305 source "board/freescale/ls1028a/Kconfig"
2306 source "board/freescale/ls1021aqds/Kconfig"
2307 source "board/freescale/ls1043aqds/Kconfig"
2308 source "board/freescale/ls1021atwr/Kconfig"
2309 source "board/freescale/ls1021atsn/Kconfig"
2310 source "board/freescale/ls1021aiot/Kconfig"
2311 source "board/freescale/ls1046aqds/Kconfig"
2312 source "board/freescale/ls1043ardb/Kconfig"
2313 source "board/freescale/ls1046ardb/Kconfig"
2314 source "board/freescale/ls1046afrwy/Kconfig"
2315 source "board/freescale/ls1012aqds/Kconfig"
2316 source "board/freescale/ls1012ardb/Kconfig"
2317 source "board/freescale/ls1012afrdm/Kconfig"
2318 source "board/freescale/lx2160a/Kconfig"
2319 source "board/grinn/chiliboard/Kconfig"
2320 source "board/hisilicon/hikey/Kconfig"
2321 source "board/hisilicon/hikey960/Kconfig"
2322 source "board/hisilicon/poplar/Kconfig"
2323 source "board/isee/igep003x/Kconfig"
2324 source "board/kontron/sl28/Kconfig"
2325 source "board/myir/mys_6ulx/Kconfig"
2326 source "board/samsung/common/Kconfig"
2327 source "board/siemens/common/Kconfig"
2328 source "board/seeed/npi_imx6ull/Kconfig"
2329 source "board/socionext/developerbox/Kconfig"
2330 source "board/st/stv0991/Kconfig"
2331 source "board/tcl/sl50/Kconfig"
2332 source "board/traverse/ten64/Kconfig"
2333 source "board/variscite/dart_6ul/Kconfig"
2334 source "board/vscom/baltos/Kconfig"
2335 source "board/phytium/durian/Kconfig"
2336 source "board/phytium/pomelo/Kconfig"
2337 source "board/xen/xenguest_arm64/Kconfig"
2339 source "arch/arm/Kconfig.debug"