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1 menu "ARM architecture"
2 depends on ARM
3
4 config SYS_ARCH
5 default "arm"
6
7 config ARM64
8 bool
9 select PHYS_64BIT
10 select SYS_CACHE_SHIFT_6
11
12 config ARM64_CRC32
13 bool "Enable support for CRC32 instruction"
14 depends on ARM64
15 default y
16 help
17 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
18 This is faster than software crc32 calculation. This instruction may
19 not be present on all ARMv8.0, but is always present on ARMv8.1 and
20 newer.
21
22 config POSITION_INDEPENDENT
23 bool "Generate position-independent pre-relocation code"
24 depends on ARM64 || CPU_V7A
25 help
26 U-Boot expects to be linked to a specific hard-coded address, and to
27 be loaded to and run from that address. This option lifts that
28 restriction, thus allowing the code to be loaded to and executed from
29 almost any 4K aligned address. This logic relies on the relocation
30 information that is embedded in the binary to support U-Boot
31 relocating itself to the top-of-RAM later during execution.
32
33 config INIT_SP_RELATIVE
34 bool "Specify the early stack pointer relative to the .bss section"
35 depends on ARM64
36 default n if ARCH_QEMU
37 default y if POSITION_INDEPENDENT
38 help
39 U-Boot typically uses a hard-coded value for the stack pointer
40 before relocation. Enable this option to instead calculate the
41 initial SP at run-time. This is useful to avoid hard-coding addresses
42 into U-Boot, so that it can be loaded and executed at arbitrary
43 addresses and thus avoid using arbitrary addresses at runtime.
44
45 If this option is enabled, the early stack pointer is set to
46 &_bss_start with a offset value added. The offset is specified by
47 SYS_INIT_SP_BSS_OFFSET.
48
49 config SYS_INIT_SP_BSS_OFFSET
50 int "Early stack offset from the .bss base address"
51 depends on ARM64
52 depends on INIT_SP_RELATIVE
53 default 524288
54 help
55 This option's value is the offset added to &_bss_start in order to
56 calculate the stack pointer. This offset should be large enough so
57 that the early malloc region, global data (gd), and early stack usage
58 do not overlap any appended DTB.
59
60 config LINUX_KERNEL_IMAGE_HEADER
61 depends on ARM64
62 bool
63 help
64 Place a Linux kernel image header at the start of the U-Boot binary.
65 The format of the header is described in the Linux kernel source at
66 Documentation/arm64/booting.txt. This feature is useful since the
67 image header reports the amount of memory (BSS and similar) that
68 U-Boot needs to use, but which isn't part of the binary.
69
70 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
71 depends on LINUX_KERNEL_IMAGE_HEADER
72 hex
73 help
74 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
75 TEXT_OFFSET value written to the Linux kernel image header.
76
77 config GICV2
78 bool
79
80 config GICV3
81 bool
82
83 config GIC_V3_ITS
84 bool "ARM GICV3 ITS"
85 select REGMAP
86 select SYSCON
87 select IRQ
88 help
89 ARM GICV3 Interrupt translation service (ITS).
90 Basic support for programming locality specific peripheral
91 interrupts (LPI) configuration tables and enable LPI tables.
92 LPI configuration table can be used by u-boot or Linux.
93 ARM GICV3 has limitation, once the LPI table is enabled, LPI
94 configuration table can not be re-programmed, unless GICV3 reset.
95
96 config STATIC_RELA
97 bool
98 default y if ARM64
99
100 config DMA_ADDR_T_64BIT
101 bool
102 default y if ARM64
103
104 config HAS_VBAR
105 bool
106
107 config HAS_THUMB2
108 bool
109
110 config GPIO_EXTRA_HEADER
111 bool
112
113 # Used for compatibility with asm files copied from the kernel
114 config ARM_ASM_UNIFIED
115 bool
116 default y
117
118 # Used for compatibility with asm files copied from the kernel
119 config THUMB2_KERNEL
120 bool
121
122 config SYS_ICACHE_OFF
123 bool "Do not enable icache"
124 help
125 Do not enable instruction cache in U-Boot.
126
127 config SPL_SYS_ICACHE_OFF
128 bool "Do not enable icache in SPL"
129 depends on SPL
130 default SYS_ICACHE_OFF
131 help
132 Do not enable instruction cache in SPL.
133
134 config SYS_DCACHE_OFF
135 bool "Do not enable dcache"
136 help
137 Do not enable data cache in U-Boot.
138
139 config SPL_SYS_DCACHE_OFF
140 bool "Do not enable dcache in SPL"
141 depends on SPL
142 default SYS_DCACHE_OFF
143 help
144 Do not enable data cache in SPL.
145
146 config SYS_ARM_CACHE_CP15
147 bool "CP15 based cache enabling support"
148 help
149 Select this if your processor suports enabling caches by using
150 CP15 registers.
151
152 config SYS_ARM_MMU
153 bool "MMU-based Paged Memory Management Support"
154 select SYS_ARM_CACHE_CP15
155 help
156 Select if you want MMU-based virtualised addressing space
157 support via paged memory management.
158
159 config SYS_ARM_MPU
160 bool 'Use the ARM v7 PMSA Compliant MPU'
161 help
162 Some ARM systems without an MMU have instead a Memory Protection
163 Unit (MPU) that defines the type and permissions for regions of
164 memory.
165 If your CPU has an MPU then you should choose 'y' here unless you
166 know that you do not want to use the MPU.
167
168 # If set, the workarounds for these ARM errata are applied early during U-Boot
169 # startup. Note that in general these options force the workarounds to be
170 # applied; no CPU-type/version detection exists, unlike the similar options in
171 # the Linux kernel. Do not set these options unless they apply! Also note that
172 # the following can be machine-specific errata. These do have ability to
173 # provide rudimentary version and machine-specific checks, but expect no
174 # product checks:
175 # CONFIG_ARM_ERRATA_430973
176 # CONFIG_ARM_ERRATA_454179
177 # CONFIG_ARM_ERRATA_621766
178 # CONFIG_ARM_ERRATA_798870
179 # CONFIG_ARM_ERRATA_801819
180 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
181 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
182
183 config ARM_ERRATA_430973
184 bool
185
186 config ARM_ERRATA_454179
187 bool
188
189 config ARM_ERRATA_621766
190 bool
191
192 config ARM_ERRATA_716044
193 bool
194
195 config ARM_ERRATA_725233
196 bool
197
198 config ARM_ERRATA_742230
199 bool
200
201 config ARM_ERRATA_743622
202 bool
203
204 config ARM_ERRATA_751472
205 bool
206
207 config ARM_ERRATA_761320
208 bool
209
210 config ARM_ERRATA_773022
211 bool
212
213 config ARM_ERRATA_774769
214 bool
215
216 config ARM_ERRATA_794072
217 bool
218
219 config ARM_ERRATA_798870
220 bool
221
222 config ARM_ERRATA_801819
223 bool
224
225 config ARM_ERRATA_826974
226 bool
227
228 config ARM_ERRATA_828024
229 bool
230
231 config ARM_ERRATA_829520
232 bool
233
234 config ARM_ERRATA_833069
235 bool
236
237 config ARM_ERRATA_833471
238 bool
239
240 config ARM_ERRATA_845369
241 bool
242
243 config ARM_ERRATA_852421
244 bool
245
246 config ARM_ERRATA_852423
247 bool
248
249 config ARM_ERRATA_855873
250 bool
251
252 config ARM_CORTEX_A8_CVE_2017_5715
253 bool
254
255 config ARM_CORTEX_A15_CVE_2017_5715
256 bool
257
258 config CPU_ARM720T
259 bool
260 select SYS_CACHE_SHIFT_5
261 imply SYS_ARM_MMU
262
263 config CPU_ARM920T
264 bool
265 select SYS_CACHE_SHIFT_5
266 imply SYS_ARM_MMU
267
268 config CPU_ARM926EJS
269 bool
270 select SYS_CACHE_SHIFT_5
271 imply SYS_ARM_MMU
272
273 config CPU_ARM946ES
274 bool
275 select SYS_CACHE_SHIFT_5
276 imply SYS_ARM_MMU
277
278 config CPU_ARM1136
279 bool
280 select SYS_CACHE_SHIFT_5
281 imply SYS_ARM_MMU
282
283 config CPU_ARM1176
284 bool
285 select HAS_VBAR
286 select SYS_CACHE_SHIFT_5
287 imply SYS_ARM_MMU
288
289 config CPU_V7A
290 bool
291 select HAS_THUMB2
292 select HAS_VBAR
293 select SYS_CACHE_SHIFT_6
294 imply SYS_ARM_MMU
295
296 config CPU_V7M
297 bool
298 select HAS_THUMB2
299 select SYS_ARM_MPU
300 select SYS_CACHE_SHIFT_5
301 select SYS_THUMB_BUILD
302 select THUMB2_KERNEL
303
304 config CPU_V7R
305 bool
306 select HAS_THUMB2
307 select SYS_ARM_CACHE_CP15
308 select SYS_ARM_MPU
309 select SYS_CACHE_SHIFT_6
310
311 config CPU_PXA
312 bool
313 select SYS_CACHE_SHIFT_5
314 imply SYS_ARM_MMU
315
316 config CPU_SA1100
317 bool
318 select SYS_CACHE_SHIFT_5
319 imply SYS_ARM_MMU
320
321 config SYS_CPU
322 default "arm720t" if CPU_ARM720T
323 default "arm920t" if CPU_ARM920T
324 default "arm926ejs" if CPU_ARM926EJS
325 default "arm946es" if CPU_ARM946ES
326 default "arm1136" if CPU_ARM1136
327 default "arm1176" if CPU_ARM1176
328 default "armv7" if CPU_V7A
329 default "armv7" if CPU_V7R
330 default "armv7m" if CPU_V7M
331 default "pxa" if CPU_PXA
332 default "sa1100" if CPU_SA1100
333 default "armv8" if ARM64
334
335 config SYS_ARM_ARCH
336 int
337 default 4 if CPU_ARM720T
338 default 4 if CPU_ARM920T
339 default 5 if CPU_ARM926EJS
340 default 5 if CPU_ARM946ES
341 default 6 if CPU_ARM1136
342 default 6 if CPU_ARM1176
343 default 7 if CPU_V7A
344 default 7 if CPU_V7M
345 default 7 if CPU_V7R
346 default 5 if CPU_PXA
347 default 4 if CPU_SA1100
348 default 8 if ARM64
349
350 choice
351 prompt "Select the ARM data write cache policy"
352 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
353 CPU_PXA || RZA1
354 default SYS_ARM_CACHE_WRITEBACK
355
356 config SYS_ARM_CACHE_WRITEBACK
357 bool "Write-back (WB)"
358 help
359 A write updates the cache only and marks the cache line as dirty.
360 External memory is updated only when the line is evicted or explicitly
361 cleaned.
362
363 config SYS_ARM_CACHE_WRITETHROUGH
364 bool "Write-through (WT)"
365 help
366 A write updates both the cache and the external memory system.
367 This does not mark the cache line as dirty.
368
369 config SYS_ARM_CACHE_WRITEALLOC
370 bool "Write allocation (WA)"
371 help
372 A cache line is allocated on a write miss. This means that executing a
373 store instruction on the processor might cause a burst read to occur.
374 There is a linefill to obtain the data for the cache line, before the
375 write is performed.
376 endchoice
377
378 config ARCH_CPU_INIT
379 bool "Enable ARCH_CPU_INIT"
380 help
381 Some architectures require a call to arch_cpu_init().
382 Say Y here to enable it
383
384 config SYS_ARCH_TIMER
385 bool "ARM Generic Timer support"
386 depends on CPU_V7A || ARM64
387 default y if ARM64
388 help
389 The ARM Generic Timer (aka arch-timer) provides an architected
390 interface to a timer source on an SoC.
391 It is mandatory for ARMv8 implementation and widely available
392 on ARMv7 systems.
393
394 config ARM_SMCCC
395 bool "Support for ARM SMC Calling Convention (SMCCC)"
396 depends on CPU_V7A || ARM64
397 select ARM_PSCI_FW
398 help
399 Say Y here if you want to enable ARM SMC Calling Convention.
400 This should be enabled if U-Boot needs to communicate with system
401 firmware (for example, PSCI) according to SMCCC.
402
403 config SEMIHOSTING
404 bool "support boot from semihosting"
405 help
406 In emulated environments, semihosting is a way for
407 the hosted environment to call out to the emulator to
408 retrieve files from the host machine.
409
410 config SYS_THUMB_BUILD
411 bool "Build U-Boot using the Thumb instruction set"
412 depends on !ARM64
413 help
414 Use this flag to build U-Boot using the Thumb instruction set for
415 ARM architectures. Thumb instruction set provides better code
416 density. For ARM architectures that support Thumb2 this flag will
417 result in Thumb2 code generated by GCC.
418
419 config SPL_SYS_THUMB_BUILD
420 bool "Build SPL using the Thumb instruction set"
421 default y if SYS_THUMB_BUILD
422 depends on !ARM64 && SPL
423 help
424 Use this flag to build SPL using the Thumb instruction set for
425 ARM architectures. Thumb instruction set provides better code
426 density. For ARM architectures that support Thumb2 this flag will
427 result in Thumb2 code generated by GCC.
428
429 config TPL_SYS_THUMB_BUILD
430 bool "Build TPL using the Thumb instruction set"
431 default y if SYS_THUMB_BUILD
432 depends on TPL && !ARM64
433 help
434 Use this flag to build TPL using the Thumb instruction set for
435 ARM architectures. Thumb instruction set provides better code
436 density. For ARM architectures that support Thumb2 this flag will
437 result in Thumb2 code generated by GCC.
438
439
440 config SYS_L2CACHE_OFF
441 bool "L2cache off"
442 help
443 If SoC does not support L2CACHE or one does not want to enable
444 L2CACHE, choose this option.
445
446 config ENABLE_ARM_SOC_BOOT0_HOOK
447 bool "prepare BOOT0 header"
448 help
449 If the SoC's BOOT0 requires a header area filled with (magic)
450 values, then choose this option, and create a file included as
451 <asm/arch/boot0.h> which contains the required assembler code.
452
453 config ARM_CORTEX_CPU_IS_UP
454 bool
455
456 config USE_ARCH_MEMCPY
457 bool "Use an assembly optimized implementation of memcpy"
458 default y if !ARM64
459 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
460 help
461 Enable the generation of an optimized version of memcpy.
462 Such an implementation may be faster under some conditions
463 but may increase the binary size.
464
465 config SPL_USE_ARCH_MEMCPY
466 bool "Use an assembly optimized implementation of memcpy for SPL"
467 default y if USE_ARCH_MEMCPY
468 depends on SPL
469 help
470 Enable the generation of an optimized version of memcpy.
471 Such an implementation may be faster under some conditions
472 but may increase the binary size.
473
474 config TPL_USE_ARCH_MEMCPY
475 bool "Use an assembly optimized implementation of memcpy for TPL"
476 default y if USE_ARCH_MEMCPY
477 depends on TPL
478 help
479 Enable the generation of an optimized version of memcpy.
480 Such an implementation may be faster under some conditions
481 but may increase the binary size.
482
483 config USE_ARCH_MEMMOVE
484 bool "Use an assembly optimized implementation of memmove" if !ARM64
485 default USE_ARCH_MEMCPY if ARM64
486 depends on ARM64
487 help
488 Enable the generation of an optimized version of memmove.
489 Such an implementation may be faster under some conditions
490 but may increase the binary size.
491
492 config SPL_USE_ARCH_MEMMOVE
493 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
494 default SPL_USE_ARCH_MEMCPY if ARM64
495 depends on SPL && ARM64
496 help
497 Enable the generation of an optimized version of memmove.
498 Such an implementation may be faster under some conditions
499 but may increase the binary size.
500
501 config TPL_USE_ARCH_MEMMOVE
502 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
503 default TPL_USE_ARCH_MEMCPY if ARM64
504 depends on TPL && ARM64
505 help
506 Enable the generation of an optimized version of memmove.
507 Such an implementation may be faster under some conditions
508 but may increase the binary size.
509
510 config USE_ARCH_MEMSET
511 bool "Use an assembly optimized implementation of memset"
512 default y if !ARM64
513 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
514 help
515 Enable the generation of an optimized version of memset.
516 Such an implementation may be faster under some conditions
517 but may increase the binary size.
518
519 config SPL_USE_ARCH_MEMSET
520 bool "Use an assembly optimized implementation of memset for SPL"
521 default y if USE_ARCH_MEMSET
522 depends on SPL
523 help
524 Enable the generation of an optimized version of memset.
525 Such an implementation may be faster under some conditions
526 but may increase the binary size.
527
528 config TPL_USE_ARCH_MEMSET
529 bool "Use an assembly optimized implementation of memset for TPL"
530 default y if USE_ARCH_MEMSET
531 depends on TPL
532 help
533 Enable the generation of an optimized version of memset.
534 Such an implementation may be faster under some conditions
535 but may increase the binary size.
536
537 config ARM64_SUPPORT_AARCH32
538 bool "ARM64 system support AArch32 execution state"
539 depends on ARM64
540 default y if !TARGET_THUNDERX_88XX
541 help
542 This ARM64 system supports AArch32 execution state.
543
544 choice
545 prompt "Target select"
546 default TARGET_HIKEY
547
548 config ARCH_AT91
549 bool "Atmel AT91"
550 select GPIO_EXTRA_HEADER
551 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
552 select SPL_SEPARATE_BSS if SPL
553
554 config ARCH_DAVINCI
555 bool "TI DaVinci"
556 select CPU_ARM926EJS
557 select GPIO_EXTRA_HEADER
558 select SPL_DM_SPI if SPL
559 imply CMD_SAVES
560 help
561 Support for TI's DaVinci platform.
562
563 config ARCH_KIRKWOOD
564 bool "Marvell Kirkwood"
565 select ARCH_MISC_INIT
566 select BOARD_EARLY_INIT_F
567 select CPU_ARM926EJS
568 select GPIO_EXTRA_HEADER
569
570 config ARCH_MVEBU
571 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
572 select DM
573 select DM_ETH
574 select DM_SERIAL
575 select DM_SPI
576 select DM_SPI_FLASH
577 select GPIO_EXTRA_HEADER
578 select SPL_DM_SPI if SPL
579 select SPL_DM_SPI_FLASH if SPL
580 select OF_CONTROL
581 select OF_SEPARATE
582 select SPI
583 imply CMD_DM
584
585 config ARCH_ORION5X
586 bool "Marvell Orion"
587 select CPU_ARM926EJS
588 select GPIO_EXTRA_HEADER
589
590 config TARGET_STV0991
591 bool "Support stv0991"
592 select CPU_V7A
593 select DM
594 select DM_SERIAL
595 select DM_SPI
596 select DM_SPI_FLASH
597 select GPIO_EXTRA_HEADER
598 select PL01X_SERIAL
599 select SPI
600 select SPI_FLASH
601 imply CMD_DM
602
603 config ARCH_BCM283X
604 bool "Broadcom BCM283X family"
605 select DM
606 select DM_GPIO
607 select DM_SERIAL
608 select GPIO_EXTRA_HEADER
609 select OF_CONTROL
610 select PL01X_SERIAL
611 select SERIAL_SEARCH_ALL
612 imply CMD_DM
613 imply FAT_WRITE
614
615 config ARCH_BCM63158
616 bool "Broadcom BCM63158 family"
617 select DM
618 select OF_CONTROL
619 imply CMD_DM
620
621 config ARCH_BCM68360
622 bool "Broadcom BCM68360 family"
623 select DM
624 select OF_CONTROL
625 imply CMD_DM
626
627 config ARCH_BCM6858
628 bool "Broadcom BCM6858 family"
629 select DM
630 select OF_CONTROL
631 imply CMD_DM
632
633 config ARCH_BCMSTB
634 bool "Broadcom BCM7XXX family"
635 select CPU_V7A
636 select DM
637 select GPIO_EXTRA_HEADER
638 select OF_CONTROL
639 imply CMD_DM
640 help
641 This enables support for Broadcom ARM-based set-top box
642 chipsets, including the 7445 family of chips.
643
644 config TARGET_VEXPRESS_CA9X4
645 bool "Support vexpress_ca9x4"
646 select CPU_V7A
647 select PL011_SERIAL
648
649 config TARGET_BCMCYGNUS
650 bool "Support bcmcygnus"
651 select CPU_V7A
652 select GPIO_EXTRA_HEADER
653 imply BCM_SF2_ETH
654 imply BCM_SF2_ETH_GMAC
655 imply CMD_HASH
656 imply CRC32_VERIFY
657 imply FAT_WRITE
658 imply HASH_VERIFY
659 imply NETDEVICES
660
661 config TARGET_BCMNS2
662 bool "Support Broadcom Northstar2"
663 select ARM64
664 select GPIO_EXTRA_HEADER
665 help
666 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
667 ARMv8 Cortex-A57 processors targeting a broad range of networking
668 applications.
669
670 config TARGET_BCMNS3
671 bool "Support Broadcom NS3"
672 select ARM64
673 select BOARD_LATE_INIT
674 help
675 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
676 ARMv8 Cortex-A72 processors targeting a broad range of networking
677 applications.
678
679 config ARCH_EXYNOS
680 bool "Samsung EXYNOS"
681 select DM
682 select DM_GPIO
683 select DM_I2C
684 select DM_ETH
685 select DM_KEYBOARD
686 select DM_SERIAL
687 select DM_SPI
688 select DM_SPI_FLASH
689 select SPI
690 select GPIO_EXTRA_HEADER
691 imply SYS_THUMB_BUILD
692 imply CMD_DM
693 imply FAT_WRITE
694
695 config ARCH_S5PC1XX
696 bool "Samsung S5PC1XX"
697 select CPU_V7A
698 select DM
699 select DM_GPIO
700 select DM_I2C
701 select DM_SERIAL
702 select GPIO_EXTRA_HEADER
703 imply CMD_DM
704
705 config ARCH_HIGHBANK
706 bool "Calxeda Highbank"
707 select CPU_V7A
708 select PL01X_SERIAL
709 select DM
710 select DM_SERIAL
711 select OF_CONTROL
712 select OF_BOARD
713 select CLK
714 select CLK_CCF
715 select AHCI
716 select DM_ETH
717 select PHYS_64BIT
718
719 config ARCH_INTEGRATOR
720 bool "ARM Ltd. Integrator family"
721 select DM
722 select DM_SERIAL
723 select GPIO_EXTRA_HEADER
724 select PL01X_SERIAL
725 imply CMD_DM
726
727 config ARCH_IPQ40XX
728 bool "Qualcomm IPQ40xx SoCs"
729 select CPU_V7A
730 select DM
731 select DM_GPIO
732 select DM_SERIAL
733 select DM_RESET
734 select GPIO_EXTRA_HEADER
735 select MSM_SMEM
736 select PINCTRL
737 select CLK
738 select SMEM
739 select OF_CONTROL
740 imply CMD_DM
741
742 config ARCH_KEYSTONE
743 bool "TI Keystone"
744 select CMD_POWEROFF
745 select CPU_V7A
746 select DDR_SPD
747 select GPIO_EXTRA_HEADER
748 select SUPPORT_SPL
749 select SYS_ARCH_TIMER
750 select SYS_THUMB_BUILD
751 imply CMD_MTDPARTS
752 imply CMD_SAVES
753 imply FIT
754
755 config ARCH_K3
756 bool "Texas Instruments' K3 Architecture"
757 select SPL
758 select SUPPORT_SPL
759 select FIT
760
761 config ARCH_OMAP2PLUS
762 bool "TI OMAP2+"
763 select CPU_V7A
764 select GPIO_EXTRA_HEADER
765 select SPL_BOARD_INIT if SPL
766 select SPL_STACK_R if SPL
767 select SUPPORT_SPL
768 imply TI_SYSC if DM && OF_CONTROL
769 imply FIT
770
771 config ARCH_MESON
772 bool "Amlogic Meson"
773 select GPIO_EXTRA_HEADER
774 imply DISTRO_DEFAULTS
775 imply DM_RNG
776 help
777 Support for the Meson SoC family developed by Amlogic Inc.,
778 targeted at media players and tablet computers. We currently
779 support the S905 (GXBaby) 64-bit SoC.
780
781 config ARCH_MEDIATEK
782 bool "MediaTek SoCs"
783 select DM
784 select GPIO_EXTRA_HEADER
785 select OF_CONTROL
786 select SPL_DM if SPL
787 select SPL_LIBCOMMON_SUPPORT if SPL
788 select SPL_LIBGENERIC_SUPPORT if SPL
789 select SPL_OF_CONTROL if SPL
790 select SUPPORT_SPL
791 help
792 Support for the MediaTek SoCs family developed by MediaTek Inc.
793 Please refer to doc/README.mediatek for more information.
794
795 config ARCH_LPC32XX
796 bool "NXP LPC32xx platform"
797 select CPU_ARM926EJS
798 select DM
799 select DM_GPIO
800 select DM_SERIAL
801 select GPIO_EXTRA_HEADER
802 select SPL_DM if SPL
803 select SUPPORT_SPL
804 imply CMD_DM
805
806 config ARCH_IMX8
807 bool "NXP i.MX8 platform"
808 select ARM64
809 select DM
810 select GPIO_EXTRA_HEADER
811 select MACH_IMX
812 select OF_CONTROL
813 select ENABLE_ARM_SOC_BOOT0_HOOK
814
815 config ARCH_IMX8M
816 bool "NXP i.MX8M platform"
817 select ARM64
818 select GPIO_EXTRA_HEADER
819 select MACH_IMX
820 select SYS_FSL_HAS_SEC if IMX_HAB
821 select SYS_FSL_SEC_COMPAT_4
822 select SYS_FSL_SEC_LE
823 select SYS_I2C_MXC
824 select DM
825 select SUPPORT_SPL
826 imply CMD_DM
827
828 config ARCH_IMX8ULP
829 bool "NXP i.MX8ULP platform"
830 select ARM64
831 select DM
832 select MACH_IMX
833 select OF_CONTROL
834 select SUPPORT_SPL
835 select GPIO_EXTRA_HEADER
836 imply CMD_DM
837
838 config ARCH_IMXRT
839 bool "NXP i.MXRT platform"
840 select CPU_V7M
841 select DM
842 select DM_SERIAL
843 select GPIO_EXTRA_HEADER
844 select MACH_IMX
845 select SUPPORT_SPL
846 imply CMD_DM
847
848 config ARCH_MX23
849 bool "NXP i.MX23 family"
850 select CPU_ARM926EJS
851 select GPIO_EXTRA_HEADER
852 select MACH_IMX
853 select PL011_SERIAL
854 select SUPPORT_SPL
855
856 config ARCH_MX28
857 bool "NXP i.MX28 family"
858 select CPU_ARM926EJS
859 select GPIO_EXTRA_HEADER
860 select PL011_SERIAL
861 select MACH_IMX
862 select SUPPORT_SPL
863
864 config ARCH_MX31
865 bool "NXP i.MX31 family"
866 select CPU_ARM1136
867 select GPIO_EXTRA_HEADER
868 select MACH_IMX
869
870 config ARCH_MX7ULP
871 bool "NXP MX7ULP"
872 select CPU_V7A
873 select GPIO_EXTRA_HEADER
874 select MACH_IMX
875 select SYS_FSL_HAS_SEC if IMX_HAB
876 select SYS_FSL_SEC_COMPAT_4
877 select SYS_FSL_SEC_LE
878 select ROM_UNIFIED_SECTIONS
879 imply MXC_GPIO
880 imply SYS_THUMB_BUILD
881
882 config ARCH_MX7
883 bool "Freescale MX7"
884 select ARCH_MISC_INIT
885 select CPU_V7A
886 select GPIO_EXTRA_HEADER
887 select MACH_IMX
888 select SYS_FSL_HAS_SEC if IMX_HAB
889 select SYS_FSL_SEC_COMPAT_4
890 select SYS_FSL_SEC_LE
891 imply BOARD_EARLY_INIT_F
892 imply MXC_GPIO
893 imply SYS_THUMB_BUILD
894
895 config ARCH_MX6
896 bool "Freescale MX6"
897 select CPU_V7A
898 select GPIO_EXTRA_HEADER
899 select MACH_IMX
900 select SYS_FSL_HAS_SEC
901 select SYS_FSL_SEC_COMPAT_4
902 select SYS_FSL_SEC_LE
903 imply MXC_GPIO
904 imply SYS_THUMB_BUILD
905
906 if ARCH_MX6
907 config SPL_LDSCRIPT
908 default "arch/arm/mach-omap2/u-boot-spl.lds"
909 endif
910
911 config ARCH_MX5
912 bool "Freescale MX5"
913 select BOARD_EARLY_INIT_F
914 select CPU_V7A
915 select GPIO_EXTRA_HEADER
916 select MACH_IMX
917 imply MXC_GPIO
918
919 config ARCH_NEXELL
920 bool "Nexell S5P4418/S5P6818 SoC"
921 select ENABLE_ARM_SOC_BOOT0_HOOK
922 select DM
923 select GPIO_EXTRA_HEADER
924
925 config ARCH_OWL
926 bool "Actions Semi OWL SoCs"
927 select DM
928 select DM_ETH
929 select DM_SERIAL
930 select GPIO_EXTRA_HEADER
931 select OWL_SERIAL
932 select CLK
933 select CLK_OWL
934 select OF_CONTROL
935 select SYS_RELOC_GD_ENV_ADDR
936 imply CMD_DM
937
938 config ARCH_QEMU
939 bool "QEMU Virtual Platform"
940 select DM
941 select DM_SERIAL
942 select OF_CONTROL
943 select PL01X_SERIAL
944 imply CMD_DM
945 imply DM_RNG
946 imply DM_RTC
947 imply RTC_PL031
948
949 config ARCH_RMOBILE
950 bool "Renesas ARM SoCs"
951 select DM
952 select DM_SERIAL
953 select GPIO_EXTRA_HEADER
954 imply BOARD_EARLY_INIT_F
955 imply CMD_DM
956 imply FAT_WRITE
957 imply SYS_THUMB_BUILD
958 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
959
960 config ARCH_SNAPDRAGON
961 bool "Qualcomm Snapdragon SoCs"
962 select ARM64
963 select DM
964 select DM_GPIO
965 select DM_SERIAL
966 select GPIO_EXTRA_HEADER
967 select MSM_SMEM
968 select OF_CONTROL
969 select OF_SEPARATE
970 select SMEM
971 select SPMI
972 imply CMD_DM
973
974 config ARCH_SOCFPGA
975 bool "Altera SOCFPGA family"
976 select ARCH_EARLY_INIT_R
977 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
978 select ARM64 if TARGET_SOCFPGA_SOC64
979 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
980 select DM
981 select DM_SERIAL
982 select GICV2
983 select GPIO_EXTRA_HEADER
984 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
985 select OF_CONTROL
986 select SPL_DM_RESET if DM_RESET
987 select SPL_DM_SERIAL
988 select SPL_LIBCOMMON_SUPPORT
989 select SPL_LIBGENERIC_SUPPORT
990 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
991 select SPL_OF_CONTROL
992 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
993 select SPL_SERIAL
994 select SPL_SYSRESET
995 select SPL_WATCHDOG
996 select SUPPORT_SPL
997 select SYS_NS16550
998 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
999 select SYSRESET
1000 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1001 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1002 imply CMD_DM
1003 imply CMD_MTDPARTS
1004 imply CRC32_VERIFY
1005 imply DM_SPI
1006 imply DM_SPI_FLASH
1007 imply FAT_WRITE
1008 imply SPL
1009 imply SPL_DM
1010 imply SPL_DM_SPI
1011 imply SPL_DM_SPI_FLASH
1012 imply SPL_LIBDISK_SUPPORT
1013 imply SPL_MMC
1014 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1015 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1016 imply SPL_SPI_FLASH_SUPPORT
1017 imply SPL_SPI
1018 imply L2X0_CACHE
1019
1020 config ARCH_SUNXI
1021 bool "Support sunxi (Allwinner) SoCs"
1022 select BINMAN
1023 select CMD_GPIO
1024 select CMD_MMC if MMC
1025 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1026 select CLK
1027 select DM
1028 select DM_ETH
1029 select DM_GPIO
1030 select DM_I2C if I2C
1031 select DM_KEYBOARD
1032 select DM_MMC if MMC
1033 select DM_SCSI if SCSI
1034 select DM_SERIAL
1035 select GPIO_EXTRA_HEADER
1036 select OF_BOARD_SETUP
1037 select OF_CONTROL
1038 select OF_SEPARATE
1039 select SPECIFY_CONSOLE_INDEX
1040 select SPL_STACK_R if SPL
1041 select SPL_SYS_MALLOC_SIMPLE if SPL
1042 select SPL_SYS_THUMB_BUILD if !ARM64
1043 select SUNXI_GPIO
1044 select SYS_NS16550
1045 select SYS_THUMB_BUILD if !ARM64
1046 select USB if DISTRO_DEFAULTS
1047 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1048 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1049 select SPL_USE_TINY_PRINTF
1050 select USE_PREBOOT
1051 select SYS_RELOC_GD_ENV_ADDR
1052 imply BOARD_LATE_INIT
1053 imply CMD_DM
1054 imply CMD_GPT
1055 imply CMD_UBI if MTD_RAW_NAND
1056 imply DISTRO_DEFAULTS
1057 imply FAT_WRITE
1058 imply FIT
1059 imply OF_LIBFDT_OVERLAY
1060 imply PRE_CONSOLE_BUFFER
1061 imply SPL_GPIO
1062 imply SPL_LIBCOMMON_SUPPORT
1063 imply SPL_LIBGENERIC_SUPPORT
1064 imply SPL_MMC if MMC
1065 imply SPL_POWER
1066 imply SPL_SERIAL
1067 imply USB_GADGET
1068
1069 config ARCH_U8500
1070 bool "ST-Ericsson U8500 Series"
1071 select CPU_V7A
1072 select DM
1073 select DM_GPIO
1074 select DM_MMC if MMC
1075 select DM_SERIAL
1076 select DM_USB_GADGET if DM_USB
1077 select OF_CONTROL
1078 select SYSRESET
1079 select TIMER
1080 imply AB8500_USB_PHY
1081 imply ARM_PL180_MMCI
1082 imply CLK
1083 imply DM_PMIC
1084 imply DM_RTC
1085 imply NOMADIK_GPIO
1086 imply NOMADIK_MTU_TIMER
1087 imply PHY
1088 imply PL01X_SERIAL
1089 imply PMIC_AB8500
1090 imply RTC_PL031
1091 imply SYS_THUMB_BUILD
1092 imply SYSRESET_SYSCON
1093
1094 config ARCH_VERSAL
1095 bool "Support Xilinx Versal Platform"
1096 select ARM64
1097 select CLK
1098 select DM
1099 select DM_ETH if NET
1100 select DM_MMC if MMC
1101 select DM_SERIAL
1102 select GICV3
1103 select GPIO_EXTRA_HEADER
1104 select OF_CONTROL
1105 select SOC_DEVICE
1106 imply BOARD_LATE_INIT
1107 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1108
1109 config ARCH_VF610
1110 bool "Freescale Vybrid"
1111 select CPU_V7A
1112 select GPIO_EXTRA_HEADER
1113 select MACH_IMX
1114 select SYS_FSL_ERRATUM_ESDHC111
1115 imply CMD_MTDPARTS
1116 imply MTD_RAW_NAND
1117
1118 config ARCH_ZYNQ
1119 bool "Xilinx Zynq based platform"
1120 select CLK
1121 select CLK_ZYNQ
1122 select CPU_V7A
1123 select DM
1124 select DM_ETH if NET
1125 select DM_MMC if MMC
1126 select DM_SERIAL
1127 select DM_SPI
1128 select DM_SPI_FLASH
1129 select GPIO_EXTRA_HEADER
1130 select OF_CONTROL
1131 select SPI
1132 select SPL_BOARD_INIT if SPL
1133 select SPL_CLK if SPL
1134 select SPL_DM if SPL
1135 select SPL_DM_SPI if SPL
1136 select SPL_DM_SPI_FLASH if SPL
1137 select SPL_OF_CONTROL if SPL
1138 select SPL_SEPARATE_BSS if SPL
1139 select SUPPORT_SPL
1140 imply ARCH_EARLY_INIT_R
1141 imply BOARD_LATE_INIT
1142 imply CMD_CLK
1143 imply CMD_DM
1144 imply CMD_SPL
1145 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1146 imply FAT_WRITE
1147
1148 config ARCH_ZYNQMP_R5
1149 bool "Xilinx ZynqMP R5 based platform"
1150 select CLK
1151 select CPU_V7R
1152 select DM
1153 select DM_ETH if NET
1154 select DM_MMC if MMC
1155 select DM_SERIAL
1156 select GPIO_EXTRA_HEADER
1157 select OF_CONTROL
1158 imply CMD_DM
1159 imply DM_USB_GADGET
1160
1161 config ARCH_ZYNQMP
1162 bool "Xilinx ZynqMP based platform"
1163 select ARM64
1164 select CLK
1165 select DM
1166 select DM_ETH if NET
1167 select DM_MAILBOX
1168 select DM_MMC if MMC
1169 select DM_SERIAL
1170 select DM_SPI if SPI
1171 select DM_SPI_FLASH if DM_SPI
1172 select FIRMWARE
1173 select GICV2
1174 select GPIO_EXTRA_HEADER
1175 select OF_CONTROL
1176 select SPL_BOARD_INIT if SPL
1177 select SPL_CLK if SPL
1178 select SPL_DM if SPL
1179 select SPL_DM_SPI if SPI && SPL_DM
1180 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1181 select SPL_DM_MAILBOX if SPL
1182 select SPL_FIRMWARE if SPL
1183 select SPL_SEPARATE_BSS if SPL
1184 select SUPPORT_SPL
1185 select ZYNQMP_IPI
1186 select SOC_DEVICE
1187 imply BOARD_LATE_INIT
1188 imply CMD_DM
1189 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1190 imply FAT_WRITE
1191 imply MP
1192 imply DM_USB_GADGET
1193
1194 config ARCH_TEGRA
1195 bool "NVIDIA Tegra"
1196 select GPIO_EXTRA_HEADER
1197 imply DISTRO_DEFAULTS
1198 imply FAT_WRITE
1199
1200 config TARGET_VEXPRESS64_AEMV8A
1201 bool "Support vexpress_aemv8a"
1202 select ARM64
1203 select GPIO_EXTRA_HEADER
1204 select PL01X_SERIAL
1205
1206 config TARGET_VEXPRESS64_BASE_FVP
1207 bool "Support Versatile Express ARMv8a FVP BASE model"
1208 select ARM64
1209 select GPIO_EXTRA_HEADER
1210 select PL01X_SERIAL
1211 select SEMIHOSTING
1212
1213 config TARGET_VEXPRESS64_JUNO
1214 bool "Support Versatile Express Juno Development Platform"
1215 select ARM64
1216 select GPIO_EXTRA_HEADER
1217 select PL01X_SERIAL
1218 select DM
1219 select OF_CONTROL
1220 select OF_BOARD
1221 select CLK
1222 select DM_SERIAL
1223 select ARM_PSCI_FW
1224 select PSCI_RESET
1225 select DM_ETH
1226 select BLK
1227 select USB
1228
1229 config TARGET_TOTAL_COMPUTE
1230 bool "Support Total Compute Platform"
1231 select ARM64
1232 select PL01X_SERIAL
1233 select DM
1234 select DM_SERIAL
1235 select DM_MMC
1236 select DM_GPIO
1237
1238 config TARGET_LS2080A_EMU
1239 bool "Support ls2080a_emu"
1240 select ARCH_LS2080A
1241 select ARM64
1242 select ARMV8_MULTIENTRY
1243 select FSL_DDR_SYNC_REFRESH
1244 select GPIO_EXTRA_HEADER
1245 help
1246 Support for Freescale LS2080A_EMU platform.
1247 The LS2080A Development System (EMULATOR) is a pre-silicon
1248 development platform that supports the QorIQ LS2080A
1249 Layerscape Architecture processor.
1250
1251 config TARGET_LS1088AQDS
1252 bool "Support ls1088aqds"
1253 select ARCH_LS1088A
1254 select ARM64
1255 select ARMV8_MULTIENTRY
1256 select ARCH_SUPPORT_TFABOOT
1257 select BOARD_LATE_INIT
1258 select GPIO_EXTRA_HEADER
1259 select SUPPORT_SPL
1260 select FSL_DDR_INTERACTIVE if !SD_BOOT
1261 help
1262 Support for NXP LS1088AQDS platform.
1263 The LS1088A Development System (QDS) is a high-performance
1264 development platform that supports the QorIQ LS1088A
1265 Layerscape Architecture processor.
1266
1267 config TARGET_LS2080AQDS
1268 bool "Support ls2080aqds"
1269 select ARCH_LS2080A
1270 select ARM64
1271 select ARMV8_MULTIENTRY
1272 select ARCH_SUPPORT_TFABOOT
1273 select BOARD_LATE_INIT
1274 select GPIO_EXTRA_HEADER
1275 select SUPPORT_SPL
1276 imply SCSI
1277 imply SCSI_AHCI
1278 select FSL_DDR_BIST
1279 select FSL_DDR_INTERACTIVE if !SPL
1280 help
1281 Support for Freescale LS2080AQDS platform.
1282 The LS2080A Development System (QDS) is a high-performance
1283 development platform that supports the QorIQ LS2080A
1284 Layerscape Architecture processor.
1285
1286 config TARGET_LS2080ARDB
1287 bool "Support ls2080ardb"
1288 select ARCH_LS2080A
1289 select ARM64
1290 select ARMV8_MULTIENTRY
1291 select ARCH_SUPPORT_TFABOOT
1292 select BOARD_LATE_INIT
1293 select SUPPORT_SPL
1294 select FSL_DDR_BIST
1295 select FSL_DDR_INTERACTIVE if !SPL
1296 select GPIO_EXTRA_HEADER
1297 imply SCSI
1298 imply SCSI_AHCI
1299 help
1300 Support for Freescale LS2080ARDB platform.
1301 The LS2080A Reference design board (RDB) is a high-performance
1302 development platform that supports the QorIQ LS2080A
1303 Layerscape Architecture processor.
1304
1305 config TARGET_LS2081ARDB
1306 bool "Support ls2081ardb"
1307 select ARCH_LS2080A
1308 select ARM64
1309 select ARMV8_MULTIENTRY
1310 select BOARD_LATE_INIT
1311 select GPIO_EXTRA_HEADER
1312 select SUPPORT_SPL
1313 help
1314 Support for Freescale LS2081ARDB platform.
1315 The LS2081A Reference design board (RDB) is a high-performance
1316 development platform that supports the QorIQ LS2081A/LS2041A
1317 Layerscape Architecture processor.
1318
1319 config TARGET_LX2160ARDB
1320 bool "Support lx2160ardb"
1321 select ARCH_LX2160A
1322 select ARM64
1323 select ARMV8_MULTIENTRY
1324 select ARCH_SUPPORT_TFABOOT
1325 select BOARD_LATE_INIT
1326 select GPIO_EXTRA_HEADER
1327 help
1328 Support for NXP LX2160ARDB platform.
1329 The lx2160ardb (LX2160A Reference design board (RDB)
1330 is a high-performance development platform that supports the
1331 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1332
1333 config TARGET_LX2160AQDS
1334 bool "Support lx2160aqds"
1335 select ARCH_LX2160A
1336 select ARM64
1337 select ARMV8_MULTIENTRY
1338 select ARCH_SUPPORT_TFABOOT
1339 select BOARD_LATE_INIT
1340 select GPIO_EXTRA_HEADER
1341 help
1342 Support for NXP LX2160AQDS platform.
1343 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1344 is a high-performance development platform that supports the
1345 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1346
1347 config TARGET_LX2162AQDS
1348 bool "Support lx2162aqds"
1349 select ARCH_LX2162A
1350 select ARCH_MISC_INIT
1351 select ARM64
1352 select ARMV8_MULTIENTRY
1353 select ARCH_SUPPORT_TFABOOT
1354 select BOARD_LATE_INIT
1355 select GPIO_EXTRA_HEADER
1356 help
1357 Support for NXP LX2162AQDS platform.
1358 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1359
1360 config TARGET_HIKEY
1361 bool "Support HiKey 96boards Consumer Edition Platform"
1362 select ARM64
1363 select DM
1364 select DM_GPIO
1365 select DM_SERIAL
1366 select GPIO_EXTRA_HEADER
1367 select OF_CONTROL
1368 select PL01X_SERIAL
1369 select SPECIFY_CONSOLE_INDEX
1370 imply CMD_DM
1371 help
1372 Support for HiKey 96boards platform. It features a HI6220
1373 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1374
1375 config TARGET_HIKEY960
1376 bool "Support HiKey960 96boards Consumer Edition Platform"
1377 select ARM64
1378 select DM
1379 select DM_SERIAL
1380 select GPIO_EXTRA_HEADER
1381 select OF_CONTROL
1382 select PL01X_SERIAL
1383 imply CMD_DM
1384 help
1385 Support for HiKey960 96boards platform. It features a HI3660
1386 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1387
1388 config TARGET_POPLAR
1389 bool "Support Poplar 96boards Enterprise Edition Platform"
1390 select ARM64
1391 select DM
1392 select DM_SERIAL
1393 select GPIO_EXTRA_HEADER
1394 select OF_CONTROL
1395 select PL01X_SERIAL
1396 imply CMD_DM
1397 help
1398 Support for Poplar 96boards EE platform. It features a HI3798cv200
1399 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1400 making it capable of running any commercial set-top solution based on
1401 Linux or Android.
1402
1403 config TARGET_LS1012AQDS
1404 bool "Support ls1012aqds"
1405 select ARCH_LS1012A
1406 select ARM64
1407 select ARCH_SUPPORT_TFABOOT
1408 select BOARD_LATE_INIT
1409 select GPIO_EXTRA_HEADER
1410 help
1411 Support for Freescale LS1012AQDS platform.
1412 The LS1012A Development System (QDS) is a high-performance
1413 development platform that supports the QorIQ LS1012A
1414 Layerscape Architecture processor.
1415
1416 config TARGET_LS1012ARDB
1417 bool "Support ls1012ardb"
1418 select ARCH_LS1012A
1419 select ARM64
1420 select ARCH_SUPPORT_TFABOOT
1421 select BOARD_LATE_INIT
1422 select GPIO_EXTRA_HEADER
1423 imply SCSI
1424 imply SCSI_AHCI
1425 help
1426 Support for Freescale LS1012ARDB platform.
1427 The LS1012A Reference design board (RDB) is a high-performance
1428 development platform that supports the QorIQ LS1012A
1429 Layerscape Architecture processor.
1430
1431 config TARGET_LS1012A2G5RDB
1432 bool "Support ls1012a2g5rdb"
1433 select ARCH_LS1012A
1434 select ARM64
1435 select ARCH_SUPPORT_TFABOOT
1436 select BOARD_LATE_INIT
1437 select GPIO_EXTRA_HEADER
1438 imply SCSI
1439 help
1440 Support for Freescale LS1012A2G5RDB platform.
1441 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1442 development platform that supports the QorIQ LS1012A
1443 Layerscape Architecture processor.
1444
1445 config TARGET_LS1012AFRWY
1446 bool "Support ls1012afrwy"
1447 select ARCH_LS1012A
1448 select ARM64
1449 select ARCH_SUPPORT_TFABOOT
1450 select BOARD_LATE_INIT
1451 select GPIO_EXTRA_HEADER
1452 imply SCSI
1453 imply SCSI_AHCI
1454 help
1455 Support for Freescale LS1012AFRWY platform.
1456 The LS1012A FRWY board (FRWY) is a high-performance
1457 development platform that supports the QorIQ LS1012A
1458 Layerscape Architecture processor.
1459
1460 config TARGET_LS1012AFRDM
1461 bool "Support ls1012afrdm"
1462 select ARCH_LS1012A
1463 select ARM64
1464 select ARCH_SUPPORT_TFABOOT
1465 select GPIO_EXTRA_HEADER
1466 help
1467 Support for Freescale LS1012AFRDM platform.
1468 The LS1012A Freedom board (FRDM) is a high-performance
1469 development platform that supports the QorIQ LS1012A
1470 Layerscape Architecture processor.
1471
1472 config TARGET_LS1028AQDS
1473 bool "Support ls1028aqds"
1474 select ARCH_LS1028A
1475 select ARM64
1476 select ARMV8_MULTIENTRY
1477 select ARCH_SUPPORT_TFABOOT
1478 select BOARD_LATE_INIT
1479 select GPIO_EXTRA_HEADER
1480 help
1481 Support for Freescale LS1028AQDS platform
1482 The LS1028A Development System (QDS) is a high-performance
1483 development platform that supports the QorIQ LS1028A
1484 Layerscape Architecture processor.
1485
1486 config TARGET_LS1028ARDB
1487 bool "Support ls1028ardb"
1488 select ARCH_LS1028A
1489 select ARM64
1490 select ARMV8_MULTIENTRY
1491 select ARCH_SUPPORT_TFABOOT
1492 select BOARD_LATE_INIT
1493 select GPIO_EXTRA_HEADER
1494 help
1495 Support for Freescale LS1028ARDB platform
1496 The LS1028A Development System (RDB) is a high-performance
1497 development platform that supports the QorIQ LS1028A
1498 Layerscape Architecture processor.
1499
1500 config TARGET_LS1088ARDB
1501 bool "Support ls1088ardb"
1502 select ARCH_LS1088A
1503 select ARM64
1504 select ARMV8_MULTIENTRY
1505 select ARCH_SUPPORT_TFABOOT
1506 select BOARD_LATE_INIT
1507 select SUPPORT_SPL
1508 select FSL_DDR_INTERACTIVE if !SD_BOOT
1509 select GPIO_EXTRA_HEADER
1510 help
1511 Support for NXP LS1088ARDB platform.
1512 The LS1088A Reference design board (RDB) is a high-performance
1513 development platform that supports the QorIQ LS1088A
1514 Layerscape Architecture processor.
1515
1516 config TARGET_LS1021AQDS
1517 bool "Support ls1021aqds"
1518 select ARCH_LS1021A
1519 select ARCH_SUPPORT_PSCI
1520 select BOARD_EARLY_INIT_F
1521 select BOARD_LATE_INIT
1522 select CPU_V7A
1523 select CPU_V7_HAS_NONSEC
1524 select CPU_V7_HAS_VIRT
1525 select LS1_DEEP_SLEEP
1526 select SUPPORT_SPL
1527 select SYS_FSL_DDR
1528 select FSL_DDR_INTERACTIVE
1529 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1530 select GPIO_EXTRA_HEADER
1531 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1532 imply SCSI
1533
1534 config TARGET_LS1021ATWR
1535 bool "Support ls1021atwr"
1536 select ARCH_LS1021A
1537 select ARCH_SUPPORT_PSCI
1538 select BOARD_EARLY_INIT_F
1539 select BOARD_LATE_INIT
1540 select CPU_V7A
1541 select CPU_V7_HAS_NONSEC
1542 select CPU_V7_HAS_VIRT
1543 select LS1_DEEP_SLEEP
1544 select SUPPORT_SPL
1545 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1546 select GPIO_EXTRA_HEADER
1547 imply SCSI
1548
1549 config TARGET_PG_WCOM_SELI8
1550 bool "Support Hitachi-Powergrids SELI8 service unit card"
1551 select ARCH_LS1021A
1552 select ARCH_SUPPORT_PSCI
1553 select BOARD_EARLY_INIT_F
1554 select BOARD_LATE_INIT
1555 select CPU_V7A
1556 select CPU_V7_HAS_NONSEC
1557 select CPU_V7_HAS_VIRT
1558 select SYS_FSL_DDR
1559 select FSL_DDR_INTERACTIVE
1560 select GPIO_EXTRA_HEADER
1561 select VENDOR_KM
1562 imply SCSI
1563 help
1564 Support for Hitachi-Powergrids SELI8 service unit card.
1565 SELI8 is a QorIQ LS1021a based service unit card used
1566 in XMC20 and FOX615 product families.
1567
1568 config TARGET_PG_WCOM_EXPU1
1569 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1570 select ARCH_LS1021A
1571 select ARCH_SUPPORT_PSCI
1572 select BOARD_EARLY_INIT_F
1573 select BOARD_LATE_INIT
1574 select CPU_V7A
1575 select CPU_V7_HAS_NONSEC
1576 select CPU_V7_HAS_VIRT
1577 select SYS_FSL_DDR
1578 select FSL_DDR_INTERACTIVE
1579 select VENDOR_KM
1580 imply SCSI
1581 help
1582 Support for Hitachi-Powergrids EXPU1 service unit card.
1583 EXPU1 is a QorIQ LS1021a based service unit card used
1584 in XMC20 and FOX615 product families.
1585
1586 config TARGET_LS1021ATSN
1587 bool "Support ls1021atsn"
1588 select ARCH_LS1021A
1589 select ARCH_SUPPORT_PSCI
1590 select BOARD_EARLY_INIT_F
1591 select BOARD_LATE_INIT
1592 select CPU_V7A
1593 select CPU_V7_HAS_NONSEC
1594 select CPU_V7_HAS_VIRT
1595 select LS1_DEEP_SLEEP
1596 select SUPPORT_SPL
1597 select GPIO_EXTRA_HEADER
1598 imply SCSI
1599
1600 config TARGET_LS1021AIOT
1601 bool "Support ls1021aiot"
1602 select ARCH_LS1021A
1603 select ARCH_SUPPORT_PSCI
1604 select BOARD_LATE_INIT
1605 select CPU_V7A
1606 select CPU_V7_HAS_NONSEC
1607 select CPU_V7_HAS_VIRT
1608 select SUPPORT_SPL
1609 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1610 select GPIO_EXTRA_HEADER
1611 imply SCSI
1612 help
1613 Support for Freescale LS1021AIOT platform.
1614 The LS1021A Freescale board (IOT) is a high-performance
1615 development platform that supports the QorIQ LS1021A
1616 Layerscape Architecture processor.
1617
1618 config TARGET_LS1043AQDS
1619 bool "Support ls1043aqds"
1620 select ARCH_LS1043A
1621 select ARM64
1622 select ARMV8_MULTIENTRY
1623 select ARCH_SUPPORT_TFABOOT
1624 select BOARD_EARLY_INIT_F
1625 select BOARD_LATE_INIT
1626 select SUPPORT_SPL
1627 select FSL_DDR_INTERACTIVE if !SPL
1628 select FSL_DSPI if !SPL_NO_DSPI
1629 select DM_SPI_FLASH if FSL_DSPI
1630 select GPIO_EXTRA_HEADER
1631 imply SCSI
1632 imply SCSI_AHCI
1633 help
1634 Support for Freescale LS1043AQDS platform.
1635
1636 config TARGET_LS1043ARDB
1637 bool "Support ls1043ardb"
1638 select ARCH_LS1043A
1639 select ARM64
1640 select ARMV8_MULTIENTRY
1641 select ARCH_SUPPORT_TFABOOT
1642 select BOARD_EARLY_INIT_F
1643 select BOARD_LATE_INIT
1644 select SUPPORT_SPL
1645 select FSL_DSPI if !SPL_NO_DSPI
1646 select DM_SPI_FLASH if FSL_DSPI
1647 select GPIO_EXTRA_HEADER
1648 help
1649 Support for Freescale LS1043ARDB platform.
1650
1651 config TARGET_LS1046AQDS
1652 bool "Support ls1046aqds"
1653 select ARCH_LS1046A
1654 select ARM64
1655 select ARMV8_MULTIENTRY
1656 select ARCH_SUPPORT_TFABOOT
1657 select BOARD_EARLY_INIT_F
1658 select BOARD_LATE_INIT
1659 select DM_SPI_FLASH if DM_SPI
1660 select SUPPORT_SPL
1661 select FSL_DDR_BIST if !SPL
1662 select FSL_DDR_INTERACTIVE if !SPL
1663 select FSL_DDR_INTERACTIVE if !SPL
1664 select GPIO_EXTRA_HEADER
1665 imply SCSI
1666 help
1667 Support for Freescale LS1046AQDS platform.
1668 The LS1046A Development System (QDS) is a high-performance
1669 development platform that supports the QorIQ LS1046A
1670 Layerscape Architecture processor.
1671
1672 config TARGET_LS1046ARDB
1673 bool "Support ls1046ardb"
1674 select ARCH_LS1046A
1675 select ARM64
1676 select ARMV8_MULTIENTRY
1677 select ARCH_SUPPORT_TFABOOT
1678 select BOARD_EARLY_INIT_F
1679 select BOARD_LATE_INIT
1680 select DM_SPI_FLASH if DM_SPI
1681 select POWER_MC34VR500
1682 select SUPPORT_SPL
1683 select FSL_DDR_BIST
1684 select FSL_DDR_INTERACTIVE if !SPL
1685 select GPIO_EXTRA_HEADER
1686 imply SCSI
1687 help
1688 Support for Freescale LS1046ARDB platform.
1689 The LS1046A Reference Design Board (RDB) is a high-performance
1690 development platform that supports the QorIQ LS1046A
1691 Layerscape Architecture processor.
1692
1693 config TARGET_LS1046AFRWY
1694 bool "Support ls1046afrwy"
1695 select ARCH_LS1046A
1696 select ARM64
1697 select ARMV8_MULTIENTRY
1698 select ARCH_SUPPORT_TFABOOT
1699 select BOARD_EARLY_INIT_F
1700 select BOARD_LATE_INIT
1701 select DM_SPI_FLASH if DM_SPI
1702 select GPIO_EXTRA_HEADER
1703 imply SCSI
1704 help
1705 Support for Freescale LS1046AFRWY platform.
1706 The LS1046A Freeway Board (FRWY) is a high-performance
1707 development platform that supports the QorIQ LS1046A
1708 Layerscape Architecture processor.
1709
1710 config TARGET_SL28
1711 bool "Support sl28"
1712 select ARCH_LS1028A
1713 select ARM64
1714 select ARMV8_MULTIENTRY
1715 select SUPPORT_SPL
1716 select BINMAN
1717 select DM
1718 select DM_GPIO
1719 select DM_I2C
1720 select DM_MMC
1721 select DM_SPI_FLASH
1722 select DM_ETH
1723 select DM_MDIO
1724 select PCI
1725 select DM_RNG
1726 select DM_RTC
1727 select DM_SCSI
1728 select DM_SERIAL
1729 select DM_SPI
1730 select GPIO_EXTRA_HEADER
1731 select SPL_DM if SPL
1732 select SPL_DM_SPI if SPL
1733 select SPL_DM_SPI_FLASH if SPL
1734 select SPL_DM_I2C if SPL
1735 select SPL_DM_MMC if SPL
1736 select SPL_DM_SERIAL if SPL
1737 help
1738 Support for Kontron SMARC-sAL28 board.
1739
1740 config TARGET_COLIBRI_PXA270
1741 bool "Support colibri_pxa270"
1742 select CPU_PXA
1743 select GPIO_EXTRA_HEADER
1744
1745 config ARCH_UNIPHIER
1746 bool "Socionext UniPhier SoCs"
1747 select BOARD_LATE_INIT
1748 select DM
1749 select DM_ETH
1750 select DM_GPIO
1751 select DM_I2C
1752 select DM_MMC
1753 select DM_MTD
1754 select DM_RESET
1755 select DM_SERIAL
1756 select OF_BOARD_SETUP
1757 select OF_CONTROL
1758 select OF_LIBFDT
1759 select PINCTRL
1760 select SPL_BOARD_INIT if SPL
1761 select SPL_DM if SPL
1762 select SPL_LIBCOMMON_SUPPORT if SPL
1763 select SPL_LIBGENERIC_SUPPORT if SPL
1764 select SPL_OF_CONTROL if SPL
1765 select SPL_PINCTRL if SPL
1766 select SUPPORT_SPL
1767 imply CMD_DM
1768 imply DISTRO_DEFAULTS
1769 imply FAT_WRITE
1770 help
1771 Support for UniPhier SoC family developed by Socionext Inc.
1772 (formerly, System LSI Business Division of Panasonic Corporation)
1773
1774 config ARCH_SYNQUACER
1775 bool "Socionext SynQuacer SoCs"
1776 select ARM64
1777 select DM
1778 select GIC_V3
1779 select PSCI_RESET
1780 select SYSRESET
1781 select SYSRESET_PSCI
1782 select OF_CONTROL
1783 help
1784 Support for SynQuacer SoC family developed by Socionext Inc.
1785 This SoC is used on 96boards EE DeveloperBox.
1786
1787 config ARCH_STM32
1788 bool "Support STMicroelectronics STM32 MCU with cortex M"
1789 select CPU_V7M
1790 select DM
1791 select DM_SERIAL
1792 select GPIO_EXTRA_HEADER
1793 imply CMD_DM
1794
1795 config ARCH_STI
1796 bool "Support STMicrolectronics SoCs"
1797 select BLK
1798 select CPU_V7A
1799 select DM
1800 select DM_MMC
1801 select DM_RESET
1802 select DM_SERIAL
1803 imply CMD_DM
1804 help
1805 Support for STMicroelectronics STiH407/10 SoC family.
1806 This SoC is used on Linaro 96Board STiH410-B2260
1807
1808 config ARCH_STM32MP
1809 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1810 select ARCH_MISC_INIT
1811 select ARCH_SUPPORT_TFABOOT
1812 select BOARD_LATE_INIT
1813 select CLK
1814 select DM
1815 select DM_GPIO
1816 select DM_RESET
1817 select DM_SERIAL
1818 select GPIO_EXTRA_HEADER
1819 select MISC
1820 select OF_CONTROL
1821 select OF_LIBFDT
1822 select OF_SYSTEM_SETUP
1823 select PINCTRL
1824 select REGMAP
1825 select SUPPORT_SPL
1826 select SYSCON
1827 select SYSRESET
1828 select SYS_THUMB_BUILD
1829 imply SPL_SYSRESET
1830 imply CMD_DM
1831 imply CMD_POWEROFF
1832 imply OF_LIBFDT_OVERLAY
1833 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1834 imply USE_PREBOOT
1835 help
1836 Support for STM32MP SoC family developed by STMicroelectronics,
1837 MPUs based on ARM cortex A core
1838 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1839 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1840 chain.
1841 SPL is the unsecure FSBL for the basic boot chain.
1842
1843 config ARCH_ROCKCHIP
1844 bool "Support Rockchip SoCs"
1845 select BLK
1846 select BINMAN if SPL_OPTEE || (SPL && !ARM64)
1847 select DM
1848 select DM_GPIO
1849 select DM_I2C
1850 select DM_MMC
1851 select DM_PWM
1852 select DM_REGULATOR
1853 select DM_SERIAL
1854 select DM_SPI
1855 select DM_SPI_FLASH
1856 select ENABLE_ARM_SOC_BOOT0_HOOK
1857 select OF_CONTROL
1858 select SPI
1859 select SPL_DM if SPL
1860 select SPL_DM_SPI if SPL
1861 select SPL_DM_SPI_FLASH if SPL
1862 select SYS_MALLOC_F
1863 select SYS_THUMB_BUILD if !ARM64
1864 imply ADC
1865 imply CMD_DM
1866 imply DEBUG_UART_BOARD_INIT
1867 imply DISTRO_DEFAULTS
1868 imply FAT_WRITE
1869 imply SARADC_ROCKCHIP
1870 imply SPL_SYSRESET
1871 imply SPL_SYS_MALLOC_SIMPLE
1872 imply SYS_NS16550
1873 imply TPL_SYSRESET
1874 imply USB_FUNCTION_FASTBOOT
1875
1876 config ARCH_OCTEONTX
1877 bool "Support OcteonTX SoCs"
1878 select CLK
1879 select DM
1880 select GPIO_EXTRA_HEADER
1881 select ARM64
1882 select OF_CONTROL
1883 select OF_LIVE
1884 select BOARD_LATE_INIT
1885 select SYS_CACHE_SHIFT_7
1886
1887 config ARCH_OCTEONTX2
1888 bool "Support OcteonTX2 SoCs"
1889 select CLK
1890 select DM
1891 select GPIO_EXTRA_HEADER
1892 select ARM64
1893 select OF_CONTROL
1894 select OF_LIVE
1895 select BOARD_LATE_INIT
1896 select SYS_CACHE_SHIFT_7
1897
1898 config TARGET_THUNDERX_88XX
1899 bool "Support ThunderX 88xx"
1900 select ARM64
1901 select GPIO_EXTRA_HEADER
1902 select OF_CONTROL
1903 select PL01X_SERIAL
1904 select SYS_CACHE_SHIFT_7
1905
1906 config ARCH_ASPEED
1907 bool "Support Aspeed SoCs"
1908 select DM
1909 select OF_CONTROL
1910 imply CMD_DM
1911
1912 config TARGET_DURIAN
1913 bool "Support Phytium Durian Platform"
1914 select ARM64
1915 select GPIO_EXTRA_HEADER
1916 help
1917 Support for durian platform.
1918 It has 2GB Sdram, uart and pcie.
1919
1920 config TARGET_PRESIDIO_ASIC
1921 bool "Support Cortina Presidio ASIC Platform"
1922 select ARM64
1923 select GICV2
1924
1925 config TARGET_XENGUEST_ARM64
1926 bool "Xen guest ARM64"
1927 select ARM64
1928 select XEN
1929 select OF_CONTROL
1930 select LINUX_KERNEL_IMAGE_HEADER
1931 select XEN_SERIAL
1932 select SSCANF
1933 endchoice
1934
1935 config SUPPORT_PASSING_ATAGS
1936 bool "Support pre-devicetree ATAG-based booting"
1937 depends on !ARM64
1938 imply SETUP_MEMORY_TAGS
1939 help
1940 Support for booting older Linux kernels, using ATAGs rather than
1941 passing a devicetree. This is option is rarely used, and the
1942 semantics are defined at
1943 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
1944
1945 config SETUP_MEMORY_TAGS
1946 bool "Pass memory size information via ATAG"
1947 depends on SUPPORT_PASSING_ATAGS
1948
1949 config CMDLINE_TAG
1950 bool "Pass Linux kernel cmdline via ATAG"
1951 depends on SUPPORT_PASSING_ATAGS
1952
1953 config INITRD_TAG
1954 bool "Pass initrd starting point and size via ATAG"
1955 depends on SUPPORT_PASSING_ATAGS
1956
1957 config REVISION_TAG
1958 bool "Pass system revision via ATAG"
1959 depends on SUPPORT_PASSING_ATAGS
1960
1961 config SERIAL_TAG
1962 bool "Pass system serial number via ATAG"
1963 depends on SUPPORT_PASSING_ATAGS
1964
1965 config STATIC_MACH_TYPE
1966 bool "Statically define the Machine ID number"
1967 help
1968 When booting via ATAGs, enable this option if we know the correct
1969 machine ID number to use at compile time. Some systems will be
1970 passed the number dynamically by whatever loads U-Boot.
1971
1972 config MACH_TYPE
1973 int "Machine ID number"
1974 depends on STATIC_MACH_TYPE
1975 help
1976 When booting via ATAGs, the machine type must be passed as a number.
1977 For the full list see https://www.arm.linux.org.uk/developer/machines
1978
1979 config ARCH_SUPPORT_TFABOOT
1980 bool
1981
1982 config TFABOOT
1983 bool "Support for booting from TF-A"
1984 depends on ARCH_SUPPORT_TFABOOT
1985 help
1986 Some platforms support the setup of secure registers (for instance
1987 for CPU errata handling) or provide secure services like PSCI.
1988 Those services could also be provided by other firmware parts
1989 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1990 does not need to (and cannot) execute this code.
1991 Enabling this option will make a U-Boot binary that is relying
1992 on other firmware layers to provide secure functionality.
1993
1994 config TI_SECURE_DEVICE
1995 bool "HS Device Type Support"
1996 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1997 help
1998 If a high secure (HS) device type is being used, this config
1999 must be set. This option impacts various aspects of the
2000 build system (to create signed boot images that can be
2001 authenticated) and the code. See the doc/README.ti-secure
2002 file for further details.
2003
2004 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
2005 config ISW_ENTRY_ADDR
2006 hex "Address in memory or XIP address of bootloader entry point"
2007 default 0x402F4000 if AM43XX
2008 default 0x402F0400 if AM33XX
2009 default 0x40301350 if OMAP54XX
2010 help
2011 After any reset, the boot ROM searches the boot media for a valid
2012 boot image. For non-XIP devices, the ROM then copies the image into
2013 internal memory. For all boot modes, after the ROM processes the
2014 boot image it eventually computes the entry point address depending
2015 on the device type (secure/non-secure), boot media (xip/non-xip) and
2016 image headers.
2017 endif
2018
2019 source "arch/arm/mach-aspeed/Kconfig"
2020
2021 source "arch/arm/mach-at91/Kconfig"
2022
2023 source "arch/arm/mach-bcm283x/Kconfig"
2024
2025 source "arch/arm/mach-bcmstb/Kconfig"
2026
2027 source "arch/arm/mach-davinci/Kconfig"
2028
2029 source "arch/arm/mach-exynos/Kconfig"
2030
2031 source "arch/arm/mach-highbank/Kconfig"
2032
2033 source "arch/arm/mach-integrator/Kconfig"
2034
2035 source "arch/arm/mach-ipq40xx/Kconfig"
2036
2037 source "arch/arm/mach-k3/Kconfig"
2038
2039 source "arch/arm/mach-keystone/Kconfig"
2040
2041 source "arch/arm/mach-kirkwood/Kconfig"
2042
2043 source "arch/arm/mach-lpc32xx/Kconfig"
2044
2045 source "arch/arm/mach-mvebu/Kconfig"
2046
2047 source "arch/arm/mach-octeontx/Kconfig"
2048
2049 source "arch/arm/mach-octeontx2/Kconfig"
2050
2051 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2052
2053 source "arch/arm/mach-imx/mx3/Kconfig"
2054
2055 source "arch/arm/mach-imx/mx5/Kconfig"
2056
2057 source "arch/arm/mach-imx/mx6/Kconfig"
2058
2059 source "arch/arm/mach-imx/mx7/Kconfig"
2060
2061 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2062
2063 source "arch/arm/mach-imx/imx8/Kconfig"
2064
2065 source "arch/arm/mach-imx/imx8m/Kconfig"
2066
2067 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2068
2069 source "arch/arm/mach-imx/imxrt/Kconfig"
2070
2071 source "arch/arm/mach-imx/mxs/Kconfig"
2072
2073 source "arch/arm/mach-omap2/Kconfig"
2074
2075 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2076
2077 source "arch/arm/mach-orion5x/Kconfig"
2078
2079 source "arch/arm/mach-owl/Kconfig"
2080
2081 source "arch/arm/mach-rmobile/Kconfig"
2082
2083 source "arch/arm/mach-meson/Kconfig"
2084
2085 source "arch/arm/mach-mediatek/Kconfig"
2086
2087 source "arch/arm/mach-qemu/Kconfig"
2088
2089 source "arch/arm/mach-rockchip/Kconfig"
2090
2091 source "arch/arm/mach-s5pc1xx/Kconfig"
2092
2093 source "arch/arm/mach-snapdragon/Kconfig"
2094
2095 source "arch/arm/mach-socfpga/Kconfig"
2096
2097 source "arch/arm/mach-sti/Kconfig"
2098
2099 source "arch/arm/mach-stm32/Kconfig"
2100
2101 source "arch/arm/mach-stm32mp/Kconfig"
2102
2103 source "arch/arm/mach-sunxi/Kconfig"
2104
2105 source "arch/arm/mach-tegra/Kconfig"
2106
2107 source "arch/arm/mach-u8500/Kconfig"
2108
2109 source "arch/arm/mach-uniphier/Kconfig"
2110
2111 source "arch/arm/cpu/armv7/vf610/Kconfig"
2112
2113 source "arch/arm/mach-zynq/Kconfig"
2114
2115 source "arch/arm/mach-zynqmp/Kconfig"
2116
2117 source "arch/arm/mach-versal/Kconfig"
2118
2119 source "arch/arm/mach-zynqmp-r5/Kconfig"
2120
2121 source "arch/arm/cpu/armv7/Kconfig"
2122
2123 source "arch/arm/cpu/armv8/Kconfig"
2124
2125 source "arch/arm/mach-imx/Kconfig"
2126
2127 source "arch/arm/mach-nexell/Kconfig"
2128
2129 source "board/armltd/total_compute/Kconfig"
2130
2131 source "board/bosch/shc/Kconfig"
2132 source "board/bosch/guardian/Kconfig"
2133 source "board/Marvell/octeontx/Kconfig"
2134 source "board/Marvell/octeontx2/Kconfig"
2135 source "board/armltd/vexpress/Kconfig"
2136 source "board/armltd/vexpress64/Kconfig"
2137 source "board/cortina/presidio-asic/Kconfig"
2138 source "board/broadcom/bcm963158/Kconfig"
2139 source "board/broadcom/bcm968360bg/Kconfig"
2140 source "board/broadcom/bcm968580xref/Kconfig"
2141 source "board/broadcom/bcmns3/Kconfig"
2142 source "board/cavium/thunderx/Kconfig"
2143 source "board/eets/pdu001/Kconfig"
2144 source "board/emulation/qemu-arm/Kconfig"
2145 source "board/freescale/ls2080aqds/Kconfig"
2146 source "board/freescale/ls2080ardb/Kconfig"
2147 source "board/freescale/ls1088a/Kconfig"
2148 source "board/freescale/ls1028a/Kconfig"
2149 source "board/freescale/ls1021aqds/Kconfig"
2150 source "board/freescale/ls1043aqds/Kconfig"
2151 source "board/freescale/ls1021atwr/Kconfig"
2152 source "board/freescale/ls1021atsn/Kconfig"
2153 source "board/freescale/ls1021aiot/Kconfig"
2154 source "board/freescale/ls1046aqds/Kconfig"
2155 source "board/freescale/ls1043ardb/Kconfig"
2156 source "board/freescale/ls1046ardb/Kconfig"
2157 source "board/freescale/ls1046afrwy/Kconfig"
2158 source "board/freescale/ls1012aqds/Kconfig"
2159 source "board/freescale/ls1012ardb/Kconfig"
2160 source "board/freescale/ls1012afrdm/Kconfig"
2161 source "board/freescale/lx2160a/Kconfig"
2162 source "board/grinn/chiliboard/Kconfig"
2163 source "board/hisilicon/hikey/Kconfig"
2164 source "board/hisilicon/hikey960/Kconfig"
2165 source "board/hisilicon/poplar/Kconfig"
2166 source "board/isee/igep003x/Kconfig"
2167 source "board/kontron/sl28/Kconfig"
2168 source "board/myir/mys_6ulx/Kconfig"
2169 source "board/seeed/npi_imx6ull/Kconfig"
2170 source "board/socionext/developerbox/Kconfig"
2171 source "board/st/stv0991/Kconfig"
2172 source "board/tcl/sl50/Kconfig"
2173 source "board/toradex/colibri_pxa270/Kconfig"
2174 source "board/variscite/dart_6ul/Kconfig"
2175 source "board/vscom/baltos/Kconfig"
2176 source "board/phytium/durian/Kconfig"
2177 source "board/xen/xenguest_arm64/Kconfig"
2178 source "board/keymile/Kconfig"
2179
2180 source "arch/arm/Kconfig.debug"
2181
2182 endmenu
2183
2184 config SPL_LDSCRIPT
2185 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2186 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2187 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64