1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
15 depends on ARM64 && CC_IS_GCC
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMNS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
416 config SYS_THUMB_BUILD
417 bool "Build U-Boot using the Thumb instruction set"
420 Use this flag to build U-Boot using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config SPL_SYS_THUMB_BUILD
426 bool "Build SPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on !ARM64 && SPL
430 Use this flag to build SPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
435 config TPL_SYS_THUMB_BUILD
436 bool "Build TPL using the Thumb instruction set"
437 default y if SYS_THUMB_BUILD
438 depends on TPL && !ARM64
440 Use this flag to build TPL using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
446 bool "ARM PL310 L2 cache controller"
448 Enable support for ARM PL310 L2 cache controller in U-Boot
450 config SPL_SYS_L2_PL310
451 bool "ARM PL310 L2 cache controller in SPL"
453 Enable support for ARM PL310 L2 cache controller in SPL
455 config SYS_L2CACHE_OFF
458 If SoC does not support L2CACHE or one does not want to enable
459 L2CACHE, choose this option.
461 config ENABLE_ARM_SOC_BOOT0_HOOK
462 bool "prepare BOOT0 header"
464 If the SoC's BOOT0 requires a header area filled with (magic)
465 values, then choose this option, and create a file included as
466 <asm/arch/boot0.h> which contains the required assembler code.
468 config USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy"
471 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config SPL_USE_ARCH_MEMCPY
478 bool "Use an assembly optimized implementation of memcpy for SPL"
479 default y if USE_ARCH_MEMCPY
482 Enable the generation of an optimized version of memcpy.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config TPL_USE_ARCH_MEMCPY
487 bool "Use an assembly optimized implementation of memcpy for TPL"
488 default y if USE_ARCH_MEMCPY
491 Enable the generation of an optimized version of memcpy.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config USE_ARCH_MEMMOVE
496 bool "Use an assembly optimized implementation of memmove" if !ARM64
497 default USE_ARCH_MEMCPY if ARM64
500 Enable the generation of an optimized version of memmove.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SPL_USE_ARCH_MEMMOVE
505 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
506 default SPL_USE_ARCH_MEMCPY if ARM64
507 depends on SPL && ARM64
509 Enable the generation of an optimized version of memmove.
510 Such an implementation may be faster under some conditions
511 but may increase the binary size.
513 config TPL_USE_ARCH_MEMMOVE
514 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
515 default TPL_USE_ARCH_MEMCPY if ARM64
516 depends on TPL && ARM64
518 Enable the generation of an optimized version of memmove.
519 Such an implementation may be faster under some conditions
520 but may increase the binary size.
522 config USE_ARCH_MEMSET
523 bool "Use an assembly optimized implementation of memset"
525 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
527 Enable the generation of an optimized version of memset.
528 Such an implementation may be faster under some conditions
529 but may increase the binary size.
531 config SPL_USE_ARCH_MEMSET
532 bool "Use an assembly optimized implementation of memset for SPL"
533 default y if USE_ARCH_MEMSET
536 Enable the generation of an optimized version of memset.
537 Such an implementation may be faster under some conditions
538 but may increase the binary size.
540 config TPL_USE_ARCH_MEMSET
541 bool "Use an assembly optimized implementation of memset for TPL"
542 default y if USE_ARCH_MEMSET
545 Enable the generation of an optimized version of memset.
546 Such an implementation may be faster under some conditions
547 but may increase the binary size.
549 config ARM64_SUPPORT_AARCH32
550 bool "ARM64 system support AArch32 execution state"
552 default y if !TARGET_THUNDERX_88XX
554 This ARM64 system supports AArch32 execution state.
560 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
563 prompt "Target select"
568 select GPIO_EXTRA_HEADER
569 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
570 select SPL_SEPARATE_BSS if SPL
571 imply SYS_THUMB_BUILD
576 select GPIO_EXTRA_HEADER
577 select SPL_DM_SPI if SPL
580 Support for TI's DaVinci platform.
583 bool "Hisilicon HiSTB SoCs"
590 Support for HiSTB SoCs.
593 bool "Marvell Kirkwood"
594 select ARCH_MISC_INIT
595 select BOARD_EARLY_INIT_F
597 select GPIO_EXTRA_HEADER
601 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
602 select ARCH_EARLY_INIT_R if ARM64
607 select GPIO_EXTRA_HEADER
608 select SPL_DM_SPI if SPL
609 select SPL_DM_SPI_FLASH if SPL
610 select SPL_TIMER if SPL
611 select TIMER if !ARM64
620 select GPIO_EXTRA_HEADER
621 select SPL_SEPARATE_BSS if SPL
624 config TARGET_STV0991
625 bool "Support stv0991"
631 select GPIO_EXTRA_HEADER
638 bool "Broadcom BCM283X family"
642 select GPIO_EXTRA_HEADER
645 select SERIAL_SEARCH_ALL
650 bool "Broadcom BCM7XXX family"
653 select GPIO_EXTRA_HEADER
656 imply OF_HAS_PRIOR_STAGE
658 This enables support for Broadcom ARM-based set-top box
659 chipsets, including the 7445 family of chips.
662 bool "Broadcom broadband chip family"
667 config TARGET_VEXPRESS_CA9X4
668 bool "Support vexpress_ca9x4"
673 bool "Support Broadcom Northstar"
681 select ARM_GLOBAL_TIMER
682 imply SYS_THUMB_BUILD
685 imply NAND_BRCMNAND_IPROC
687 Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
688 ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
692 bool "Support Broadcom Northstar2"
694 select GPIO_EXTRA_HEADER
696 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
697 ARMv8 Cortex-A57 processors targeting a broad range of networking
701 bool "Support Broadcom NS3"
703 select BOARD_LATE_INIT
705 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
706 ARMv8 Cortex-A72 processors targeting a broad range of networking
710 bool "Samsung EXYNOS"
719 select GPIO_EXTRA_HEADER
720 imply SYS_THUMB_BUILD
725 bool "Samsung S5PC1XX"
731 select GPIO_EXTRA_HEADER
735 bool "Calxeda Highbank"
747 imply OF_HAS_PRIOR_STAGE
749 config ARCH_INTEGRATOR
750 bool "ARM Ltd. Integrator family"
753 select GPIO_EXTRA_HEADER
758 bool "Qualcomm IPQ40xx SoCs"
764 select GPIO_EXTRA_HEADER
778 select SYS_ARCH_TIMER
779 select SYS_THUMB_BUILD
785 bool "Texas Instruments' K3 Architecture"
790 select FIT_SIGNATURE if ARM64
791 imply TI_SECURE_DEVICE
793 config ARCH_OMAP2PLUS
796 select GPIO_EXTRA_HEADER
797 select SPL_BOARD_INIT if SPL
798 select SPL_STACK_R if SPL
800 imply TI_SYSC if DM && OF_CONTROL
802 imply SPL_SEPARATE_BSS
806 select GPIO_EXTRA_HEADER
807 imply DISTRO_DEFAULTS
810 Support for the Meson SoC family developed by Amlogic Inc.,
811 targeted at media players and tablet computers. We currently
812 support the S905 (GXBaby) 64-bit SoC.
817 select GPIO_EXTRA_HEADER
820 select SPL_LIBCOMMON_SUPPORT if SPL
821 select SPL_LIBGENERIC_SUPPORT if SPL
822 select SPL_OF_CONTROL if SPL
825 Support for the MediaTek SoCs family developed by MediaTek Inc.
826 Please refer to doc/README.mediatek for more information.
829 bool "NXP LPC32xx platform"
834 select GPIO_EXTRA_HEADER
840 bool "NXP i.MX8 platform"
842 select SYS_FSL_HAS_SEC
843 select SYS_FSL_SEC_COMPAT_4
844 select SYS_FSL_SEC_LE
847 select GPIO_EXTRA_HEADER
850 select ENABLE_ARM_SOC_BOOT0_HOOK
853 bool "NXP i.MX8M platform"
855 select GPIO_EXTRA_HEADER
857 select SYS_FSL_HAS_SEC
858 select SYS_FSL_SEC_COMPAT_4
859 select SYS_FSL_SEC_LE
862 select DM_EVENT if CLK
867 bool "NXP i.MX8ULP platform"
874 select GPIO_EXTRA_HEADER
880 bool "NXP i.MX9 platform"
886 select GPIO_EXTRA_HEADER
892 bool "NXP i.MXRT platform"
896 select GPIO_EXTRA_HEADER
902 bool "NXP i.MX23 family"
904 select GPIO_EXTRA_HEADER
909 bool "NXP i.MX28 family"
911 select GPIO_EXTRA_HEADER
916 bool "NXP i.MX31 family"
918 select GPIO_EXTRA_HEADER
923 select BOARD_POSTCLK_INIT
925 select GPIO_EXTRA_HEADER
927 select SYS_FSL_HAS_SEC
928 select SYS_FSL_SEC_COMPAT_4
929 select SYS_FSL_SEC_LE
930 select ROM_UNIFIED_SECTIONS
932 imply SYS_THUMB_BUILD
936 select ARCH_MISC_INIT
938 select GPIO_EXTRA_HEADER
941 select SYS_FSL_HAS_SEC
942 select SYS_FSL_SEC_COMPAT_4
943 select SYS_FSL_SEC_LE
944 imply BOARD_EARLY_INIT_F
946 imply SYS_THUMB_BUILD
950 select BOARD_POSTCLK_INIT
952 select GPIO_EXTRA_HEADER
955 select SYS_FSL_HAS_SEC
956 select SYS_FSL_SEC_COMPAT_4
957 select SYS_FSL_SEC_LE
958 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
960 imply SYS_THUMB_BUILD
961 imply SPL_SEPARATE_BSS
965 select BOARD_EARLY_INIT_F
967 select GPIO_EXTRA_HEADER
972 bool "Nexell S5P4418/S5P6818 SoC"
973 select ENABLE_ARM_SOC_BOOT0_HOOK
975 select GPIO_EXTRA_HEADER
978 bool "Support Nuvoton SoCs"
999 select LINUX_KERNEL_IMAGE_HEADER
1000 select OF_BOARD_SETUP
1005 select POSITION_INDEPENDENT
1011 select SYSRESET_WATCHDOG
1012 select SYSRESET_WATCHDOG_AUTO
1016 imply DISTRO_DEFAULTS
1017 imply OF_HAS_PRIOR_STAGE
1020 bool "Actions Semi OWL SoCs"
1023 select GPIO_EXTRA_HEADER
1028 select SYS_RELOC_GD_ENV_ADDR
1032 bool "QEMU Virtual Platform"
1041 imply OF_HAS_PRIOR_STAGE
1044 imply SYS_WHITE_ON_BLACK
1045 imply SYS_CONSOLE_IS_IN_ENV
1046 imply PRE_CONSOLE_BUFFER
1054 bool "Renesas ARM SoCs"
1057 select GPIO_EXTRA_HEADER
1058 imply BOARD_EARLY_INIT_F
1061 imply SYS_THUMB_BUILD
1062 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1064 config ARCH_SNAPDRAGON
1065 bool "Qualcomm Snapdragon SoCs"
1070 select GPIO_EXTRA_HEADER
1079 bool "Altera SOCFPGA family"
1080 select ARCH_EARLY_INIT_R
1081 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1082 select ARM64 if TARGET_SOCFPGA_SOC64
1083 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1087 select GPIO_EXTRA_HEADER
1088 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1090 select SPL_DM_RESET if DM_RESET
1091 select SPL_DM_SERIAL
1092 select SPL_LIBCOMMON_SUPPORT
1093 select SPL_LIBGENERIC_SUPPORT
1094 select SPL_OF_CONTROL
1095 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1101 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1103 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1104 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1114 imply SPL_DM_SPI_FLASH
1115 imply SPL_LIBDISK_SUPPORT
1117 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1118 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1119 imply SPL_SPI_FLASH_SUPPORT
1124 bool "Support sunxi (Allwinner) SoCs"
1127 select CMD_MMC if MMC
1128 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1132 select DM_I2C if I2C
1133 select DM_SPI if SPI
1134 select DM_SPI_FLASH if SPI
1136 select DM_MMC if MMC
1138 select OF_BOARD_SETUP
1142 select SPECIFY_CONSOLE_INDEX
1143 select SPL_SEPARATE_BSS if SPL
1144 select SPL_STACK_R if SPL
1145 select SPL_SYS_MALLOC_SIMPLE if SPL
1146 select SPL_SYS_THUMB_BUILD if !ARM64
1149 select SYS_THUMB_BUILD if !ARM64
1150 select USB if DISTRO_DEFAULTS
1151 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1152 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1153 select SPL_USE_TINY_PRINTF
1155 select SYS_RELOC_GD_ENV_ADDR
1156 imply BOARD_LATE_INIT
1159 imply CMD_UBI if MTD_RAW_NAND
1160 imply DISTRO_DEFAULTS
1162 imply DM_REGULATOR_FIXED
1165 imply OF_LIBFDT_OVERLAY
1166 imply PRE_CONSOLE_BUFFER
1168 imply SPL_LIBCOMMON_SUPPORT
1169 imply SPL_LIBGENERIC_SUPPORT
1170 imply SPL_MMC if MMC
1174 imply SYSRESET_WATCHDOG
1175 imply SYSRESET_WATCHDOG_AUTO
1180 bool "ST-Ericsson U8500 Series"
1184 select DM_MMC if MMC
1186 select DM_USB_GADGET if DM_USB
1190 imply AB8500_USB_PHY
1191 imply ARM_PL180_MMCI
1196 imply NOMADIK_MTU_TIMER
1201 imply SYS_THUMB_BUILD
1202 imply SYSRESET_SYSCON
1205 bool "Support Xilinx Versal Platform"
1209 select DM_MMC if MMC
1214 imply BOARD_LATE_INIT
1215 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1217 config ARCH_VERSAL_NET
1218 bool "Support Xilinx Versal NET Platform"
1222 select DM_MMC if MMC
1225 imply BOARD_LATE_INIT
1226 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1229 bool "Freescale Vybrid"
1231 select GPIO_EXTRA_HEADER
1232 select IOMUX_SHARE_CONF_REG
1234 select SYS_FSL_ERRATUM_ESDHC111
1239 bool "Xilinx Zynq based platform"
1240 select ARM_TWD_TIMER
1241 select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
1245 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1247 select DM_MMC if MMC
1253 select SPL_BOARD_INIT if SPL
1254 select SPL_CLK if SPL
1255 select SPL_DM if SPL
1256 select SPL_DM_SPI if SPL
1257 select SPL_DM_SPI_FLASH if SPL
1258 select SPL_OF_CONTROL if SPL
1259 select SPL_SEPARATE_BSS if SPL
1260 select SPL_TIMER if SPL
1263 imply BOARD_LATE_INIT
1267 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1270 config ARCH_ZYNQMP_R5
1271 bool "Xilinx ZynqMP R5 based platform"
1275 select DM_MMC if MMC
1282 bool "Xilinx ZynqMP based platform"
1286 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1288 select DM_MMC if MMC
1290 select DM_SPI if SPI
1291 select DM_SPI_FLASH if DM_SPI
1295 select SPL_BOARD_INIT if SPL
1296 select SPL_CLK if SPL
1297 select SPL_DM if SPL
1298 select SPL_DM_SPI if SPI && SPL_DM
1299 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1300 select SPL_DM_MAILBOX if SPL
1301 imply SPL_FIRMWARE if SPL
1302 select SPL_SEPARATE_BSS if SPL
1304 imply ZYNQMP_IPI if DM_MAILBOX
1306 imply BOARD_LATE_INIT
1308 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1312 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1316 select GPIO_EXTRA_HEADER
1317 imply DISTRO_DEFAULTS
1319 imply SPL_TIMER if SPL
1321 config ARCH_VEXPRESS64
1322 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1330 select MTD_NOR_FLASH if MTD
1331 select FLASH_CFI_DRIVER if MTD
1332 select ENV_IS_IN_FLASH if MTD
1333 imply DISTRO_DEFAULTS
1335 config TARGET_CORSTONE1000
1336 bool "Support Corstone1000 Platform"
1341 config TARGET_TOTAL_COMPUTE
1342 bool "Support Total Compute Platform"
1350 config TARGET_LS2080A_EMU
1351 bool "Support ls2080a_emu"
1354 select ARMV8_MULTIENTRY
1355 select FSL_DDR_SYNC_REFRESH
1356 select GPIO_EXTRA_HEADER
1358 Support for Freescale LS2080A_EMU platform.
1359 The LS2080A Development System (EMULATOR) is a pre-silicon
1360 development platform that supports the QorIQ LS2080A
1361 Layerscape Architecture processor.
1363 config TARGET_LS1088AQDS
1364 bool "Support ls1088aqds"
1367 select ARMV8_MULTIENTRY
1368 select ARCH_SUPPORT_TFABOOT
1369 select BOARD_LATE_INIT
1370 select GPIO_EXTRA_HEADER
1372 select FSL_DDR_INTERACTIVE if !SD_BOOT
1374 Support for NXP LS1088AQDS platform.
1375 The LS1088A Development System (QDS) is a high-performance
1376 development platform that supports the QorIQ LS1088A
1377 Layerscape Architecture processor.
1379 config TARGET_LS2080AQDS
1380 bool "Support ls2080aqds"
1383 select ARMV8_MULTIENTRY
1384 select ARCH_SUPPORT_TFABOOT
1385 select BOARD_LATE_INIT
1386 select GPIO_EXTRA_HEADER
1391 select FSL_DDR_INTERACTIVE if !SPL
1393 Support for Freescale LS2080AQDS platform.
1394 The LS2080A Development System (QDS) is a high-performance
1395 development platform that supports the QorIQ LS2080A
1396 Layerscape Architecture processor.
1398 config TARGET_LS2080ARDB
1399 bool "Support ls2080ardb"
1402 select ARMV8_MULTIENTRY
1403 select ARCH_SUPPORT_TFABOOT
1404 select BOARD_LATE_INIT
1407 select FSL_DDR_INTERACTIVE if !SPL
1408 select GPIO_EXTRA_HEADER
1412 Support for Freescale LS2080ARDB platform.
1413 The LS2080A Reference design board (RDB) is a high-performance
1414 development platform that supports the QorIQ LS2080A
1415 Layerscape Architecture processor.
1417 config TARGET_LS2081ARDB
1418 bool "Support ls2081ardb"
1421 select ARMV8_MULTIENTRY
1422 select BOARD_LATE_INIT
1423 select GPIO_EXTRA_HEADER
1426 Support for Freescale LS2081ARDB platform.
1427 The LS2081A Reference design board (RDB) is a high-performance
1428 development platform that supports the QorIQ LS2081A/LS2041A
1429 Layerscape Architecture processor.
1431 config TARGET_LX2160ARDB
1432 bool "Support lx2160ardb"
1435 select ARMV8_MULTIENTRY
1436 select ARCH_SUPPORT_TFABOOT
1437 select BOARD_LATE_INIT
1438 select GPIO_EXTRA_HEADER
1440 Support for NXP LX2160ARDB platform.
1441 The lx2160ardb (LX2160A Reference design board (RDB)
1442 is a high-performance development platform that supports the
1443 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1445 config TARGET_LX2160AQDS
1446 bool "Support lx2160aqds"
1449 select ARMV8_MULTIENTRY
1450 select ARCH_SUPPORT_TFABOOT
1451 select BOARD_LATE_INIT
1452 select GPIO_EXTRA_HEADER
1454 Support for NXP LX2160AQDS platform.
1455 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1456 is a high-performance development platform that supports the
1457 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1459 config TARGET_LX2162AQDS
1460 bool "Support lx2162aqds"
1462 select ARCH_MISC_INIT
1464 select ARMV8_MULTIENTRY
1465 select ARCH_SUPPORT_TFABOOT
1466 select BOARD_LATE_INIT
1467 select GPIO_EXTRA_HEADER
1469 Support for NXP LX2162AQDS platform.
1470 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1473 bool "Support HiKey 96boards Consumer Edition Platform"
1478 select GPIO_EXTRA_HEADER
1481 select SPECIFY_CONSOLE_INDEX
1484 Support for HiKey 96boards platform. It features a HI6220
1485 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1487 config TARGET_HIKEY960
1488 bool "Support HiKey960 96boards Consumer Edition Platform"
1492 select GPIO_EXTRA_HEADER
1497 Support for HiKey960 96boards platform. It features a HI3660
1498 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1500 config TARGET_POPLAR
1501 bool "Support Poplar 96boards Enterprise Edition Platform"
1505 select GPIO_EXTRA_HEADER
1510 Support for Poplar 96boards EE platform. It features a HI3798cv200
1511 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1512 making it capable of running any commercial set-top solution based on
1515 config TARGET_LS1012AQDS
1516 bool "Support ls1012aqds"
1519 select ARCH_SUPPORT_TFABOOT
1520 select BOARD_LATE_INIT
1521 select GPIO_EXTRA_HEADER
1523 Support for Freescale LS1012AQDS platform.
1524 The LS1012A Development System (QDS) is a high-performance
1525 development platform that supports the QorIQ LS1012A
1526 Layerscape Architecture processor.
1528 config TARGET_LS1012ARDB
1529 bool "Support ls1012ardb"
1532 select ARCH_SUPPORT_TFABOOT
1533 select BOARD_LATE_INIT
1534 select GPIO_EXTRA_HEADER
1538 Support for Freescale LS1012ARDB platform.
1539 The LS1012A Reference design board (RDB) is a high-performance
1540 development platform that supports the QorIQ LS1012A
1541 Layerscape Architecture processor.
1543 config TARGET_LS1012A2G5RDB
1544 bool "Support ls1012a2g5rdb"
1547 select ARCH_SUPPORT_TFABOOT
1548 select BOARD_LATE_INIT
1549 select GPIO_EXTRA_HEADER
1552 Support for Freescale LS1012A2G5RDB platform.
1553 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1554 development platform that supports the QorIQ LS1012A
1555 Layerscape Architecture processor.
1557 config TARGET_LS1012AFRWY
1558 bool "Support ls1012afrwy"
1561 select ARCH_SUPPORT_TFABOOT
1562 select BOARD_LATE_INIT
1563 select GPIO_EXTRA_HEADER
1567 Support for Freescale LS1012AFRWY platform.
1568 The LS1012A FRWY board (FRWY) is a high-performance
1569 development platform that supports the QorIQ LS1012A
1570 Layerscape Architecture processor.
1572 config TARGET_LS1012AFRDM
1573 bool "Support ls1012afrdm"
1576 select ARCH_SUPPORT_TFABOOT
1577 select GPIO_EXTRA_HEADER
1579 Support for Freescale LS1012AFRDM platform.
1580 The LS1012A Freedom board (FRDM) is a high-performance
1581 development platform that supports the QorIQ LS1012A
1582 Layerscape Architecture processor.
1584 config TARGET_LS1028AQDS
1585 bool "Support ls1028aqds"
1588 select ARMV8_MULTIENTRY
1589 select ARCH_SUPPORT_TFABOOT
1590 select BOARD_LATE_INIT
1591 select GPIO_EXTRA_HEADER
1593 Support for Freescale LS1028AQDS platform
1594 The LS1028A Development System (QDS) is a high-performance
1595 development platform that supports the QorIQ LS1028A
1596 Layerscape Architecture processor.
1598 config TARGET_LS1028ARDB
1599 bool "Support ls1028ardb"
1602 select ARMV8_MULTIENTRY
1603 select ARCH_SUPPORT_TFABOOT
1604 select BOARD_LATE_INIT
1605 select GPIO_EXTRA_HEADER
1607 Support for Freescale LS1028ARDB platform
1608 The LS1028A Development System (RDB) is a high-performance
1609 development platform that supports the QorIQ LS1028A
1610 Layerscape Architecture processor.
1612 config TARGET_LS1088ARDB
1613 bool "Support ls1088ardb"
1616 select ARMV8_MULTIENTRY
1617 select ARCH_SUPPORT_TFABOOT
1618 select BOARD_LATE_INIT
1620 select FSL_DDR_INTERACTIVE if !SD_BOOT
1621 select GPIO_EXTRA_HEADER
1623 Support for NXP LS1088ARDB platform.
1624 The LS1088A Reference design board (RDB) is a high-performance
1625 development platform that supports the QorIQ LS1088A
1626 Layerscape Architecture processor.
1628 config TARGET_LS1021AQDS
1629 bool "Support ls1021aqds"
1631 select ARCH_SUPPORT_PSCI
1632 select BOARD_EARLY_INIT_F
1633 select BOARD_LATE_INIT
1635 select CPU_V7_HAS_NONSEC
1636 select CPU_V7_HAS_VIRT
1637 select LS1_DEEP_SLEEP
1638 select PEN_ADDR_BIG_ENDIAN
1641 select FSL_DDR_INTERACTIVE
1642 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1643 select GPIO_EXTRA_HEADER
1644 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1647 config TARGET_LS1021ATWR
1648 bool "Support ls1021atwr"
1650 select ARCH_SUPPORT_PSCI
1651 select BOARD_EARLY_INIT_F
1652 select BOARD_LATE_INIT
1654 select CPU_V7_HAS_NONSEC
1655 select CPU_V7_HAS_VIRT
1656 select LS1_DEEP_SLEEP
1657 select PEN_ADDR_BIG_ENDIAN
1659 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1660 select GPIO_EXTRA_HEADER
1663 config TARGET_PG_WCOM_SELI8
1664 bool "Support Hitachi-Powergrids SELI8 service unit card"
1666 select ARCH_SUPPORT_PSCI
1667 select BOARD_EARLY_INIT_F
1668 select BOARD_LATE_INIT
1670 select CPU_V7_HAS_NONSEC
1671 select CPU_V7_HAS_VIRT
1673 select FSL_DDR_INTERACTIVE
1674 select GPIO_EXTRA_HEADER
1678 Support for Hitachi-Powergrids SELI8 service unit card.
1679 SELI8 is a QorIQ LS1021a based service unit card used
1680 in XMC20 and FOX615 product families.
1682 config TARGET_PG_WCOM_EXPU1
1683 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1685 select ARCH_SUPPORT_PSCI
1686 select BOARD_EARLY_INIT_F
1687 select BOARD_LATE_INIT
1689 select CPU_V7_HAS_NONSEC
1690 select CPU_V7_HAS_VIRT
1692 select FSL_DDR_INTERACTIVE
1696 Support for Hitachi-Powergrids EXPU1 service unit card.
1697 EXPU1 is a QorIQ LS1021a based service unit card used
1698 in XMC20 and FOX615 product families.
1700 config TARGET_LS1021ATSN
1701 bool "Support ls1021atsn"
1703 select ARCH_SUPPORT_PSCI
1704 select BOARD_EARLY_INIT_F
1705 select BOARD_LATE_INIT
1707 select CPU_V7_HAS_NONSEC
1708 select CPU_V7_HAS_VIRT
1709 select LS1_DEEP_SLEEP
1711 select GPIO_EXTRA_HEADER
1714 config TARGET_LS1021AIOT
1715 bool "Support ls1021aiot"
1717 select ARCH_SUPPORT_PSCI
1718 select BOARD_LATE_INIT
1720 select CPU_V7_HAS_NONSEC
1721 select CPU_V7_HAS_VIRT
1722 select PEN_ADDR_BIG_ENDIAN
1724 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1725 select GPIO_EXTRA_HEADER
1728 Support for Freescale LS1021AIOT platform.
1729 The LS1021A Freescale board (IOT) is a high-performance
1730 development platform that supports the QorIQ LS1021A
1731 Layerscape Architecture processor.
1733 config TARGET_LS1043AQDS
1734 bool "Support ls1043aqds"
1737 select ARMV8_MULTIENTRY
1738 select ARCH_SUPPORT_TFABOOT
1739 select BOARD_EARLY_INIT_F
1740 select BOARD_LATE_INIT
1742 select FSL_DDR_INTERACTIVE if !SPL
1743 select FSL_DSPI if !SPL_NO_DSPI
1744 select DM_SPI_FLASH if FSL_DSPI
1745 select GPIO_EXTRA_HEADER
1749 Support for Freescale LS1043AQDS platform.
1751 config TARGET_LS1043ARDB
1752 bool "Support ls1043ardb"
1755 select ARMV8_MULTIENTRY
1756 select ARCH_SUPPORT_TFABOOT
1757 select BOARD_EARLY_INIT_F
1758 select BOARD_LATE_INIT
1760 select FSL_DSPI if !SPL_NO_DSPI
1761 select DM_SPI_FLASH if FSL_DSPI
1762 select GPIO_EXTRA_HEADER
1764 Support for Freescale LS1043ARDB platform.
1766 config TARGET_LS1046AQDS
1767 bool "Support ls1046aqds"
1770 select ARMV8_MULTIENTRY
1771 select ARCH_SUPPORT_TFABOOT
1772 select BOARD_EARLY_INIT_F
1773 select BOARD_LATE_INIT
1774 select DM_SPI_FLASH if DM_SPI
1776 select FSL_DDR_BIST if !SPL
1777 select FSL_DDR_INTERACTIVE if !SPL
1778 select FSL_DDR_INTERACTIVE if !SPL
1779 select GPIO_EXTRA_HEADER
1782 Support for Freescale LS1046AQDS platform.
1783 The LS1046A Development System (QDS) is a high-performance
1784 development platform that supports the QorIQ LS1046A
1785 Layerscape Architecture processor.
1787 config TARGET_LS1046ARDB
1788 bool "Support ls1046ardb"
1791 select ARMV8_MULTIENTRY
1792 select ARCH_SUPPORT_TFABOOT
1793 select BOARD_EARLY_INIT_F
1794 select BOARD_LATE_INIT
1795 select DM_SPI_FLASH if DM_SPI
1796 select POWER_MC34VR500
1799 select FSL_DDR_INTERACTIVE if !SPL
1800 select GPIO_EXTRA_HEADER
1803 Support for Freescale LS1046ARDB platform.
1804 The LS1046A Reference Design Board (RDB) is a high-performance
1805 development platform that supports the QorIQ LS1046A
1806 Layerscape Architecture processor.
1808 config TARGET_LS1046AFRWY
1809 bool "Support ls1046afrwy"
1812 select ARMV8_MULTIENTRY
1813 select ARCH_SUPPORT_TFABOOT
1814 select BOARD_EARLY_INIT_F
1815 select BOARD_LATE_INIT
1816 select DM_SPI_FLASH if DM_SPI
1817 select GPIO_EXTRA_HEADER
1820 Support for Freescale LS1046AFRWY platform.
1821 The LS1046A Freeway Board (FRWY) is a high-performance
1822 development platform that supports the QorIQ LS1046A
1823 Layerscape Architecture processor.
1829 select ARMV8_MULTIENTRY
1844 select GPIO_EXTRA_HEADER
1845 select SPL_DM if SPL
1846 select SPL_DM_SPI if SPL
1847 select SPL_DM_SPI_FLASH if SPL
1848 select SPL_DM_I2C if SPL
1849 select SPL_DM_MMC if SPL
1850 select SPL_DM_SERIAL if SPL
1852 Support for Kontron SMARC-sAL28 board.
1855 bool "Support ten64"
1857 select ARCH_MISC_INIT
1859 select ARMV8_MULTIENTRY
1860 select ARCH_SUPPORT_TFABOOT
1861 select BOARD_LATE_INIT
1863 select FSL_DDR_INTERACTIVE if !SD_BOOT
1864 select GPIO_EXTRA_HEADER
1866 Support for Traverse Technologies Ten64 board, based
1869 config ARCH_UNIPHIER
1870 bool "Socionext UniPhier SoCs"
1871 select BOARD_LATE_INIT
1879 select OF_BOARD_SETUP
1883 select SPL_BOARD_INIT if SPL
1884 select SPL_DM if SPL
1885 select SPL_LIBCOMMON_SUPPORT if SPL
1886 select SPL_LIBGENERIC_SUPPORT if SPL
1887 select SPL_OF_CONTROL if SPL
1888 select SPL_PINCTRL if SPL
1891 imply DISTRO_DEFAULTS
1894 Support for UniPhier SoC family developed by Socionext Inc.
1895 (formerly, System LSI Business Division of Panasonic Corporation)
1897 config ARCH_SYNQUACER
1898 bool "Socionext SynQuacer SoCs"
1904 select SYSRESET_PSCI
1907 Support for SynQuacer SoC family developed by Socionext Inc.
1908 This SoC is used on 96boards EE DeveloperBox.
1911 bool "Support STMicroelectronics STM32 MCU with cortex M"
1918 bool "Support STMicroelectronics SoCs"
1927 Support for STMicroelectronics STiH407/10 SoC family.
1928 This SoC is used on Linaro 96Board STiH410-B2260
1931 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1932 select ARCH_MISC_INIT
1933 select ARCH_SUPPORT_TFABOOT
1934 select BOARD_LATE_INIT
1943 select OF_SYSTEM_SETUP
1948 select SYS_THUMB_BUILD if !ARM64
1952 imply OF_LIBFDT_OVERLAY
1953 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1957 Support for STM32MP SoC family developed by STMicroelectronics,
1958 MPUs based on ARM cortex A core
1959 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1960 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1962 SPL is the unsecure FSBL for the basic boot chain.
1964 config ARCH_ROCKCHIP
1965 bool "Support Rockchip SoCs"
1967 select BINMAN if SPL_OPTEE || SPL
1977 select ENABLE_ARM_SOC_BOOT0_HOOK
1980 select SPL_DM if SPL
1981 select SPL_DM_SPI if SPL
1982 select SPL_DM_SPI_FLASH if SPL
1984 select SYS_THUMB_BUILD if !ARM64
1987 imply DEBUG_UART_BOARD_INIT
1988 imply BOOTSTD_DEFAULTS
1990 imply SARADC_ROCKCHIP
1992 imply SPL_SYS_MALLOC_SIMPLE
1995 imply USB_FUNCTION_FASTBOOT
1997 config ARCH_OCTEONTX
1998 bool "Support OcteonTX SoCs"
2001 select GPIO_EXTRA_HEADER
2005 select BOARD_LATE_INIT
2006 select SYS_CACHE_SHIFT_7
2007 select SYS_PCI_64BIT if PCI
2008 imply OF_HAS_PRIOR_STAGE
2010 config ARCH_OCTEONTX2
2011 bool "Support OcteonTX2 SoCs"
2014 select GPIO_EXTRA_HEADER
2018 select BOARD_LATE_INIT
2019 select SYS_CACHE_SHIFT_7
2020 select SYS_PCI_64BIT if PCI
2021 imply OF_HAS_PRIOR_STAGE
2023 config TARGET_THUNDERX_88XX
2024 bool "Support ThunderX 88xx"
2026 select GPIO_EXTRA_HEADER
2029 select SYS_CACHE_SHIFT_7
2032 bool "Support Aspeed SoCs"
2037 config TARGET_DURIAN
2038 bool "Support Phytium Durian Platform"
2040 select GPIO_EXTRA_HEADER
2042 Support for durian platform.
2043 It has 2GB Sdram, uart and pcie.
2045 config TARGET_POMELO
2046 bool "Support Phytium Pomelo Platform"
2059 Support for pomelo platform.
2060 It has 8GB Sdram, uart and pcie.
2062 config TARGET_PRESIDIO_ASIC
2063 bool "Support Cortina Presidio ASIC Platform"
2067 config TARGET_XENGUEST_ARM64
2068 bool "Xen guest ARM64"
2072 select LINUX_KERNEL_IMAGE_HEADER
2074 imply OF_HAS_PRIOR_STAGE
2077 bool "Support HPE GXP SoCs"
2084 config SUPPORT_PASSING_ATAGS
2085 bool "Support pre-devicetree ATAG-based booting"
2087 imply SETUP_MEMORY_TAGS
2089 Support for booting older Linux kernels, using ATAGs rather than
2090 passing a devicetree. This is option is rarely used, and the
2091 semantics are defined at
2092 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2094 config SETUP_MEMORY_TAGS
2095 bool "Pass memory size information via ATAG"
2096 depends on SUPPORT_PASSING_ATAGS
2099 bool "Pass Linux kernel cmdline via ATAG"
2100 depends on SUPPORT_PASSING_ATAGS
2103 bool "Pass initrd starting point and size via ATAG"
2104 depends on SUPPORT_PASSING_ATAGS
2107 bool "Pass system revision via ATAG"
2108 depends on SUPPORT_PASSING_ATAGS
2111 bool "Pass system serial number via ATAG"
2112 depends on SUPPORT_PASSING_ATAGS
2114 config STATIC_MACH_TYPE
2115 bool "Statically define the Machine ID number"
2116 default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2118 When booting via ATAGs, enable this option if we know the correct
2119 machine ID number to use at compile time. Some systems will be
2120 passed the number dynamically by whatever loads U-Boot.
2123 int "Machine ID number"
2124 depends on STATIC_MACH_TYPE
2125 default 527 if TARGET_DS109
2126 default 3036 if TARGET_DS414
2127 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2129 When booting via ATAGs, the machine type must be passed as a number.
2130 For the full list see https://www.arm.linux.org.uk/developer/machines
2132 config ARCH_SUPPORT_TFABOOT
2136 bool "Support for booting from TF-A"
2137 depends on ARCH_SUPPORT_TFABOOT
2139 Some platforms support the setup of secure registers (for instance
2140 for CPU errata handling) or provide secure services like PSCI.
2141 Those services could also be provided by other firmware parts
2142 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2143 does not need to (and cannot) execute this code.
2144 Enabling this option will make a U-Boot binary that is relying
2145 on other firmware layers to provide secure functionality.
2147 config TI_SECURE_DEVICE
2148 bool "HS Device Type Support"
2149 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2151 If a high secure (HS) device type is being used, this config
2152 must be set. This option impacts various aspects of the
2153 build system (to create signed boot images that can be
2154 authenticated) and the code. See the doc/README.ti-secure
2155 file for further details.
2157 config SYS_KWD_CONFIG
2158 string "kwbimage config file path"
2159 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2160 default "arch/arm/mach-mvebu/kwbimage.cfg"
2162 Path within the source directory to the kwbimage.cfg file to use
2163 when packaging the U-Boot image for use.
2165 source "arch/arm/mach-apple/Kconfig"
2167 source "arch/arm/mach-aspeed/Kconfig"
2169 source "arch/arm/mach-at91/Kconfig"
2171 source "arch/arm/mach-bcm283x/Kconfig"
2173 source "arch/arm/mach-bcmbca/Kconfig"
2175 source "arch/arm/mach-bcmstb/Kconfig"
2177 source "arch/arm/mach-davinci/Kconfig"
2179 source "arch/arm/mach-exynos/Kconfig"
2181 source "arch/arm/mach-hpe/gxp/Kconfig"
2183 source "arch/arm/mach-highbank/Kconfig"
2185 source "arch/arm/mach-histb/Kconfig"
2187 source "arch/arm/mach-integrator/Kconfig"
2189 source "arch/arm/mach-ipq40xx/Kconfig"
2191 source "arch/arm/mach-k3/Kconfig"
2193 source "arch/arm/mach-keystone/Kconfig"
2195 source "arch/arm/mach-kirkwood/Kconfig"
2197 source "arch/arm/mach-lpc32xx/Kconfig"
2199 source "arch/arm/mach-mvebu/Kconfig"
2201 source "arch/arm/mach-octeontx/Kconfig"
2203 source "arch/arm/mach-octeontx2/Kconfig"
2205 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2207 source "arch/arm/mach-imx/mx3/Kconfig"
2209 source "arch/arm/mach-imx/mx5/Kconfig"
2211 source "arch/arm/mach-imx/mx6/Kconfig"
2213 source "arch/arm/mach-imx/mx7/Kconfig"
2215 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2217 source "arch/arm/mach-imx/imx8/Kconfig"
2219 source "arch/arm/mach-imx/imx8m/Kconfig"
2221 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2223 source "arch/arm/mach-imx/imx9/Kconfig"
2225 source "arch/arm/mach-imx/imxrt/Kconfig"
2227 source "arch/arm/mach-imx/mxs/Kconfig"
2229 source "arch/arm/mach-omap2/Kconfig"
2231 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2233 source "arch/arm/mach-orion5x/Kconfig"
2235 source "arch/arm/mach-owl/Kconfig"
2237 source "arch/arm/mach-rmobile/Kconfig"
2239 source "arch/arm/mach-meson/Kconfig"
2241 source "arch/arm/mach-mediatek/Kconfig"
2243 source "arch/arm/mach-qemu/Kconfig"
2245 source "arch/arm/mach-rockchip/Kconfig"
2247 source "arch/arm/mach-s5pc1xx/Kconfig"
2249 source "arch/arm/mach-snapdragon/Kconfig"
2251 source "arch/arm/mach-socfpga/Kconfig"
2253 source "arch/arm/mach-sti/Kconfig"
2255 source "arch/arm/mach-stm32/Kconfig"
2257 source "arch/arm/mach-stm32mp/Kconfig"
2259 source "arch/arm/mach-sunxi/Kconfig"
2261 source "arch/arm/mach-tegra/Kconfig"
2263 source "arch/arm/mach-u8500/Kconfig"
2265 source "arch/arm/mach-uniphier/Kconfig"
2267 source "arch/arm/cpu/armv7/vf610/Kconfig"
2269 source "arch/arm/mach-zynq/Kconfig"
2271 source "arch/arm/mach-zynqmp/Kconfig"
2273 source "arch/arm/mach-versal/Kconfig"
2275 source "arch/arm/mach-versal-net/Kconfig"
2277 source "arch/arm/mach-zynqmp-r5/Kconfig"
2279 source "arch/arm/cpu/armv7/Kconfig"
2281 source "arch/arm/cpu/armv8/Kconfig"
2283 source "arch/arm/mach-imx/Kconfig"
2285 source "arch/arm/mach-nexell/Kconfig"
2287 source "arch/arm/mach-npcm/Kconfig"
2289 source "board/armltd/total_compute/Kconfig"
2290 source "board/armltd/corstone1000/Kconfig"
2291 source "board/bosch/shc/Kconfig"
2292 source "board/bosch/guardian/Kconfig"
2293 source "board/Marvell/octeontx/Kconfig"
2294 source "board/Marvell/octeontx2/Kconfig"
2295 source "board/armltd/vexpress/Kconfig"
2296 source "board/armltd/vexpress64/Kconfig"
2297 source "board/cortina/presidio-asic/Kconfig"
2298 source "board/broadcom/bcmns/Kconfig"
2299 source "board/broadcom/bcmns3/Kconfig"
2300 source "board/cavium/thunderx/Kconfig"
2301 source "board/eets/pdu001/Kconfig"
2302 source "board/emulation/qemu-arm/Kconfig"
2303 source "board/freescale/ls2080aqds/Kconfig"
2304 source "board/freescale/ls2080ardb/Kconfig"
2305 source "board/freescale/ls1088a/Kconfig"
2306 source "board/freescale/ls1028a/Kconfig"
2307 source "board/freescale/ls1021aqds/Kconfig"
2308 source "board/freescale/ls1043aqds/Kconfig"
2309 source "board/freescale/ls1021atwr/Kconfig"
2310 source "board/freescale/ls1021atsn/Kconfig"
2311 source "board/freescale/ls1021aiot/Kconfig"
2312 source "board/freescale/ls1046aqds/Kconfig"
2313 source "board/freescale/ls1043ardb/Kconfig"
2314 source "board/freescale/ls1046ardb/Kconfig"
2315 source "board/freescale/ls1046afrwy/Kconfig"
2316 source "board/freescale/ls1012aqds/Kconfig"
2317 source "board/freescale/ls1012ardb/Kconfig"
2318 source "board/freescale/ls1012afrdm/Kconfig"
2319 source "board/freescale/lx2160a/Kconfig"
2320 source "board/grinn/chiliboard/Kconfig"
2321 source "board/hisilicon/hikey/Kconfig"
2322 source "board/hisilicon/hikey960/Kconfig"
2323 source "board/hisilicon/poplar/Kconfig"
2324 source "board/isee/igep003x/Kconfig"
2325 source "board/kontron/sl28/Kconfig"
2326 source "board/myir/mys_6ulx/Kconfig"
2327 source "board/samsung/common/Kconfig"
2328 source "board/siemens/common/Kconfig"
2329 source "board/seeed/npi_imx6ull/Kconfig"
2330 source "board/socionext/developerbox/Kconfig"
2331 source "board/st/stv0991/Kconfig"
2332 source "board/tcl/sl50/Kconfig"
2333 source "board/traverse/ten64/Kconfig"
2334 source "board/variscite/dart_6ul/Kconfig"
2335 source "board/vscom/baltos/Kconfig"
2336 source "board/phytium/durian/Kconfig"
2337 source "board/phytium/pomelo/Kconfig"
2338 source "board/xen/xenguest_arm64/Kconfig"
2340 source "arch/arm/Kconfig.debug"