1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
15 depends on ARM64 && CC_IS_GCC
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMNS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
416 config SYS_THUMB_BUILD
417 bool "Build U-Boot using the Thumb instruction set"
420 Use this flag to build U-Boot using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config SPL_SYS_THUMB_BUILD
426 bool "Build SPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on !ARM64 && SPL
430 Use this flag to build SPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
435 config TPL_SYS_THUMB_BUILD
436 bool "Build TPL using the Thumb instruction set"
437 default y if SYS_THUMB_BUILD
438 depends on TPL && !ARM64
440 Use this flag to build TPL using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
446 bool "ARM PL310 L2 cache controller"
448 Enable support for ARM PL310 L2 cache controller in U-Boot
450 config SPL_SYS_L2_PL310
451 bool "ARM PL310 L2 cache controller in SPL"
453 Enable support for ARM PL310 L2 cache controller in SPL
455 config SYS_L2CACHE_OFF
458 If SoC does not support L2CACHE or one does not want to enable
459 L2CACHE, choose this option.
461 config ENABLE_ARM_SOC_BOOT0_HOOK
462 bool "prepare BOOT0 header"
464 If the SoC's BOOT0 requires a header area filled with (magic)
465 values, then choose this option, and create a file included as
466 <asm/arch/boot0.h> which contains the required assembler code.
468 config USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy"
471 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config SPL_USE_ARCH_MEMCPY
478 bool "Use an assembly optimized implementation of memcpy for SPL"
479 default y if USE_ARCH_MEMCPY
482 Enable the generation of an optimized version of memcpy.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config TPL_USE_ARCH_MEMCPY
487 bool "Use an assembly optimized implementation of memcpy for TPL"
488 default y if USE_ARCH_MEMCPY
491 Enable the generation of an optimized version of memcpy.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config USE_ARCH_MEMMOVE
496 bool "Use an assembly optimized implementation of memmove" if !ARM64
497 default USE_ARCH_MEMCPY if ARM64
500 Enable the generation of an optimized version of memmove.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SPL_USE_ARCH_MEMMOVE
505 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
506 default SPL_USE_ARCH_MEMCPY if ARM64
507 depends on SPL && ARM64
509 Enable the generation of an optimized version of memmove.
510 Such an implementation may be faster under some conditions
511 but may increase the binary size.
513 config TPL_USE_ARCH_MEMMOVE
514 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
515 default TPL_USE_ARCH_MEMCPY if ARM64
516 depends on TPL && ARM64
518 Enable the generation of an optimized version of memmove.
519 Such an implementation may be faster under some conditions
520 but may increase the binary size.
522 config USE_ARCH_MEMSET
523 bool "Use an assembly optimized implementation of memset"
525 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
527 Enable the generation of an optimized version of memset.
528 Such an implementation may be faster under some conditions
529 but may increase the binary size.
531 config SPL_USE_ARCH_MEMSET
532 bool "Use an assembly optimized implementation of memset for SPL"
533 default y if USE_ARCH_MEMSET
536 Enable the generation of an optimized version of memset.
537 Such an implementation may be faster under some conditions
538 but may increase the binary size.
540 config TPL_USE_ARCH_MEMSET
541 bool "Use an assembly optimized implementation of memset for TPL"
542 default y if USE_ARCH_MEMSET
545 Enable the generation of an optimized version of memset.
546 Such an implementation may be faster under some conditions
547 but may increase the binary size.
549 config ARM64_SUPPORT_AARCH32
550 bool "ARM64 system support AArch32 execution state"
552 default y if !TARGET_THUNDERX_88XX
554 This ARM64 system supports AArch32 execution state.
560 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
563 prompt "Target select"
568 select GPIO_EXTRA_HEADER
569 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
570 select SPL_SEPARATE_BSS if SPL
575 select GPIO_EXTRA_HEADER
576 select SPL_DM_SPI if SPL
579 Support for TI's DaVinci platform.
582 bool "Hisilicon HiSTB SoCs"
589 Support for HiSTB SoCs.
592 bool "Marvell Kirkwood"
593 select ARCH_MISC_INIT
594 select BOARD_EARLY_INIT_F
596 select GPIO_EXTRA_HEADER
600 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
601 select ARCH_EARLY_INIT_R if ARM64
606 select GPIO_EXTRA_HEADER
607 select SPL_DM_SPI if SPL
608 select SPL_DM_SPI_FLASH if SPL
609 select SPL_TIMER if SPL
610 select TIMER if !ARM64
619 select GPIO_EXTRA_HEADER
620 select SPL_SEPARATE_BSS if SPL
623 config TARGET_STV0991
624 bool "Support stv0991"
630 select GPIO_EXTRA_HEADER
637 bool "Broadcom BCM283X family"
641 select GPIO_EXTRA_HEADER
644 select SERIAL_SEARCH_ALL
649 bool "Broadcom BCM7XXX family"
652 select GPIO_EXTRA_HEADER
655 imply OF_HAS_PRIOR_STAGE
657 This enables support for Broadcom ARM-based set-top box
658 chipsets, including the 7445 family of chips.
661 bool "Broadcom broadband chip family"
666 config TARGET_VEXPRESS_CA9X4
667 bool "Support vexpress_ca9x4"
672 bool "Support Broadcom Northstar"
680 select ARM_GLOBAL_TIMER
681 imply SYS_THUMB_BUILD
684 imply NAND_BRCMNAND_IPROC
686 Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
687 ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
691 bool "Support Broadcom Northstar2"
693 select GPIO_EXTRA_HEADER
695 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
696 ARMv8 Cortex-A57 processors targeting a broad range of networking
700 bool "Support Broadcom NS3"
702 select BOARD_LATE_INIT
704 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
705 ARMv8 Cortex-A72 processors targeting a broad range of networking
709 bool "Samsung EXYNOS"
718 select GPIO_EXTRA_HEADER
719 imply SYS_THUMB_BUILD
724 bool "Samsung S5PC1XX"
730 select GPIO_EXTRA_HEADER
734 bool "Calxeda Highbank"
746 imply OF_HAS_PRIOR_STAGE
748 config ARCH_INTEGRATOR
749 bool "ARM Ltd. Integrator family"
752 select GPIO_EXTRA_HEADER
757 bool "Qualcomm IPQ40xx SoCs"
763 select GPIO_EXTRA_HEADER
777 select SYS_ARCH_TIMER
778 select SYS_THUMB_BUILD
784 bool "Texas Instruments' K3 Architecture"
789 select FIT_SIGNATURE if ARM64
791 config ARCH_OMAP2PLUS
794 select GPIO_EXTRA_HEADER
795 select SPL_BOARD_INIT if SPL
796 select SPL_STACK_R if SPL
798 imply TI_SYSC if DM && OF_CONTROL
800 imply SPL_SEPARATE_BSS
804 select GPIO_EXTRA_HEADER
805 imply DISTRO_DEFAULTS
808 Support for the Meson SoC family developed by Amlogic Inc.,
809 targeted at media players and tablet computers. We currently
810 support the S905 (GXBaby) 64-bit SoC.
815 select GPIO_EXTRA_HEADER
818 select SPL_LIBCOMMON_SUPPORT if SPL
819 select SPL_LIBGENERIC_SUPPORT if SPL
820 select SPL_OF_CONTROL if SPL
823 Support for the MediaTek SoCs family developed by MediaTek Inc.
824 Please refer to doc/README.mediatek for more information.
827 bool "NXP LPC32xx platform"
832 select GPIO_EXTRA_HEADER
838 bool "NXP i.MX8 platform"
840 select SYS_FSL_HAS_SEC
841 select SYS_FSL_SEC_COMPAT_4
842 select SYS_FSL_SEC_LE
845 select GPIO_EXTRA_HEADER
848 select ENABLE_ARM_SOC_BOOT0_HOOK
851 bool "NXP i.MX8M platform"
853 select GPIO_EXTRA_HEADER
855 select SYS_FSL_HAS_SEC
856 select SYS_FSL_SEC_COMPAT_4
857 select SYS_FSL_SEC_LE
860 select DM_EVENT if CLK
865 bool "NXP i.MX8ULP platform"
872 select GPIO_EXTRA_HEADER
878 bool "NXP i.MX9 platform"
884 select GPIO_EXTRA_HEADER
890 bool "NXP i.MXRT platform"
894 select GPIO_EXTRA_HEADER
900 bool "NXP i.MX23 family"
902 select GPIO_EXTRA_HEADER
907 bool "NXP i.MX28 family"
909 select GPIO_EXTRA_HEADER
914 bool "NXP i.MX31 family"
916 select GPIO_EXTRA_HEADER
921 select BOARD_POSTCLK_INIT
923 select GPIO_EXTRA_HEADER
925 select SYS_FSL_HAS_SEC
926 select SYS_FSL_SEC_COMPAT_4
927 select SYS_FSL_SEC_LE
928 select ROM_UNIFIED_SECTIONS
930 imply SYS_THUMB_BUILD
934 select ARCH_MISC_INIT
936 select GPIO_EXTRA_HEADER
939 select SYS_FSL_HAS_SEC
940 select SYS_FSL_SEC_COMPAT_4
941 select SYS_FSL_SEC_LE
942 imply BOARD_EARLY_INIT_F
944 imply SYS_THUMB_BUILD
948 select BOARD_POSTCLK_INIT
950 select GPIO_EXTRA_HEADER
953 select SYS_FSL_HAS_SEC
954 select SYS_FSL_SEC_COMPAT_4
955 select SYS_FSL_SEC_LE
956 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
958 imply SYS_THUMB_BUILD
959 imply SPL_SEPARATE_BSS
963 select BOARD_EARLY_INIT_F
965 select GPIO_EXTRA_HEADER
970 bool "Nexell S5P4418/S5P6818 SoC"
971 select ENABLE_ARM_SOC_BOOT0_HOOK
973 select GPIO_EXTRA_HEADER
976 bool "Support Nuvoton SoCs"
997 select LINUX_KERNEL_IMAGE_HEADER
998 select OF_BOARD_SETUP
1003 select POSITION_INDEPENDENT
1009 select SYSRESET_WATCHDOG
1010 select SYSRESET_WATCHDOG_AUTO
1014 imply DISTRO_DEFAULTS
1015 imply OF_HAS_PRIOR_STAGE
1018 bool "Actions Semi OWL SoCs"
1021 select GPIO_EXTRA_HEADER
1026 select SYS_RELOC_GD_ENV_ADDR
1030 bool "QEMU Virtual Platform"
1039 imply OF_HAS_PRIOR_STAGE
1042 imply SYS_WHITE_ON_BLACK
1043 imply SYS_CONSOLE_IS_IN_ENV
1044 imply PRE_CONSOLE_BUFFER
1052 bool "Renesas ARM SoCs"
1055 select GPIO_EXTRA_HEADER
1056 imply BOARD_EARLY_INIT_F
1059 imply SYS_THUMB_BUILD
1060 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1062 config ARCH_SNAPDRAGON
1063 bool "Qualcomm Snapdragon SoCs"
1068 select GPIO_EXTRA_HEADER
1077 bool "Altera SOCFPGA family"
1078 select ARCH_EARLY_INIT_R
1079 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1080 select ARM64 if TARGET_SOCFPGA_SOC64
1081 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1085 select GPIO_EXTRA_HEADER
1086 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1088 select SPL_DM_RESET if DM_RESET
1089 select SPL_DM_SERIAL
1090 select SPL_LIBCOMMON_SUPPORT
1091 select SPL_LIBGENERIC_SUPPORT
1092 select SPL_OF_CONTROL
1093 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1099 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1101 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1102 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1112 imply SPL_DM_SPI_FLASH
1113 imply SPL_LIBDISK_SUPPORT
1115 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1116 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1117 imply SPL_SPI_FLASH_SUPPORT
1122 bool "Support sunxi (Allwinner) SoCs"
1125 select CMD_MMC if MMC
1126 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1130 select DM_I2C if I2C
1131 select DM_SPI if SPI
1132 select DM_SPI_FLASH if SPI
1134 select DM_MMC if MMC
1135 select DM_SCSI if SCSI
1137 select GPIO_EXTRA_HEADER
1138 select OF_BOARD_SETUP
1142 select SPECIFY_CONSOLE_INDEX
1143 select SPL_SEPARATE_BSS if SPL
1144 select SPL_STACK_R if SPL
1145 select SPL_SYS_MALLOC_SIMPLE if SPL
1146 select SPL_SYS_THUMB_BUILD if !ARM64
1149 select SYS_THUMB_BUILD if !ARM64
1150 select USB if DISTRO_DEFAULTS
1151 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1152 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1153 select SPL_USE_TINY_PRINTF
1155 select SYS_RELOC_GD_ENV_ADDR
1156 imply BOARD_LATE_INIT
1159 imply CMD_UBI if MTD_RAW_NAND
1160 imply DISTRO_DEFAULTS
1163 imply OF_LIBFDT_OVERLAY
1164 imply PRE_CONSOLE_BUFFER
1166 imply SPL_LIBCOMMON_SUPPORT
1167 imply SPL_LIBGENERIC_SUPPORT
1168 imply SPL_MMC if MMC
1172 imply SYSRESET_WATCHDOG
1173 imply SYSRESET_WATCHDOG_AUTO
1178 bool "ST-Ericsson U8500 Series"
1182 select DM_MMC if MMC
1184 select DM_USB_GADGET if DM_USB
1188 imply AB8500_USB_PHY
1189 imply ARM_PL180_MMCI
1194 imply NOMADIK_MTU_TIMER
1199 imply SYS_THUMB_BUILD
1200 imply SYSRESET_SYSCON
1203 bool "Support Xilinx Versal Platform"
1207 select DM_MMC if MMC
1212 imply BOARD_LATE_INIT
1213 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1215 config ARCH_VERSAL_NET
1216 bool "Support Xilinx Versal NET Platform"
1220 select DM_MMC if MMC
1223 imply BOARD_LATE_INIT
1224 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1227 bool "Freescale Vybrid"
1229 select GPIO_EXTRA_HEADER
1230 select IOMUX_SHARE_CONF_REG
1232 select SYS_FSL_ERRATUM_ESDHC111
1237 bool "Xilinx Zynq based platform"
1238 select ARM_TWD_TIMER
1239 select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
1243 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1245 select DM_MMC if MMC
1251 select SPL_BOARD_INIT if SPL
1252 select SPL_CLK if SPL
1253 select SPL_DM if SPL
1254 select SPL_DM_SPI if SPL
1255 select SPL_DM_SPI_FLASH if SPL
1256 select SPL_OF_CONTROL if SPL
1257 select SPL_SEPARATE_BSS if SPL
1258 select SPL_TIMER if SPL
1261 imply BOARD_LATE_INIT
1265 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1268 config ARCH_ZYNQMP_R5
1269 bool "Xilinx ZynqMP R5 based platform"
1273 select DM_MMC if MMC
1280 bool "Xilinx ZynqMP based platform"
1284 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1286 select DM_MMC if MMC
1288 select DM_SPI if SPI
1289 select DM_SPI_FLASH if DM_SPI
1293 select SPL_BOARD_INIT if SPL
1294 select SPL_CLK if SPL
1295 select SPL_DM if SPL
1296 select SPL_DM_SPI if SPI && SPL_DM
1297 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1298 select SPL_DM_MAILBOX if SPL
1299 imply SPL_FIRMWARE if SPL
1300 select SPL_SEPARATE_BSS if SPL
1302 imply ZYNQMP_IPI if DM_MAILBOX
1304 imply BOARD_LATE_INIT
1306 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1310 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1314 select GPIO_EXTRA_HEADER
1315 imply DISTRO_DEFAULTS
1317 imply SPL_TIMER if SPL
1319 config ARCH_VEXPRESS64
1320 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1328 select MTD_NOR_FLASH if MTD
1329 select FLASH_CFI_DRIVER if MTD
1330 select ENV_IS_IN_FLASH if MTD
1331 imply DISTRO_DEFAULTS
1333 config TARGET_CORSTONE1000
1334 bool "Support Corstone1000 Platform"
1339 config TARGET_TOTAL_COMPUTE
1340 bool "Support Total Compute Platform"
1348 config TARGET_LS2080A_EMU
1349 bool "Support ls2080a_emu"
1352 select ARMV8_MULTIENTRY
1353 select FSL_DDR_SYNC_REFRESH
1354 select GPIO_EXTRA_HEADER
1356 Support for Freescale LS2080A_EMU platform.
1357 The LS2080A Development System (EMULATOR) is a pre-silicon
1358 development platform that supports the QorIQ LS2080A
1359 Layerscape Architecture processor.
1361 config TARGET_LS1088AQDS
1362 bool "Support ls1088aqds"
1365 select ARMV8_MULTIENTRY
1366 select ARCH_SUPPORT_TFABOOT
1367 select BOARD_LATE_INIT
1368 select GPIO_EXTRA_HEADER
1370 select FSL_DDR_INTERACTIVE if !SD_BOOT
1372 Support for NXP LS1088AQDS platform.
1373 The LS1088A Development System (QDS) is a high-performance
1374 development platform that supports the QorIQ LS1088A
1375 Layerscape Architecture processor.
1377 config TARGET_LS2080AQDS
1378 bool "Support ls2080aqds"
1381 select ARMV8_MULTIENTRY
1382 select ARCH_SUPPORT_TFABOOT
1383 select BOARD_LATE_INIT
1384 select GPIO_EXTRA_HEADER
1389 select FSL_DDR_INTERACTIVE if !SPL
1391 Support for Freescale LS2080AQDS platform.
1392 The LS2080A Development System (QDS) is a high-performance
1393 development platform that supports the QorIQ LS2080A
1394 Layerscape Architecture processor.
1396 config TARGET_LS2080ARDB
1397 bool "Support ls2080ardb"
1400 select ARMV8_MULTIENTRY
1401 select ARCH_SUPPORT_TFABOOT
1402 select BOARD_LATE_INIT
1405 select FSL_DDR_INTERACTIVE if !SPL
1406 select GPIO_EXTRA_HEADER
1410 Support for Freescale LS2080ARDB platform.
1411 The LS2080A Reference design board (RDB) is a high-performance
1412 development platform that supports the QorIQ LS2080A
1413 Layerscape Architecture processor.
1415 config TARGET_LS2081ARDB
1416 bool "Support ls2081ardb"
1419 select ARMV8_MULTIENTRY
1420 select BOARD_LATE_INIT
1421 select GPIO_EXTRA_HEADER
1424 Support for Freescale LS2081ARDB platform.
1425 The LS2081A Reference design board (RDB) is a high-performance
1426 development platform that supports the QorIQ LS2081A/LS2041A
1427 Layerscape Architecture processor.
1429 config TARGET_LX2160ARDB
1430 bool "Support lx2160ardb"
1433 select ARMV8_MULTIENTRY
1434 select ARCH_SUPPORT_TFABOOT
1435 select BOARD_LATE_INIT
1436 select GPIO_EXTRA_HEADER
1438 Support for NXP LX2160ARDB platform.
1439 The lx2160ardb (LX2160A Reference design board (RDB)
1440 is a high-performance development platform that supports the
1441 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1443 config TARGET_LX2160AQDS
1444 bool "Support lx2160aqds"
1447 select ARMV8_MULTIENTRY
1448 select ARCH_SUPPORT_TFABOOT
1449 select BOARD_LATE_INIT
1450 select GPIO_EXTRA_HEADER
1452 Support for NXP LX2160AQDS platform.
1453 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1454 is a high-performance development platform that supports the
1455 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1457 config TARGET_LX2162AQDS
1458 bool "Support lx2162aqds"
1460 select ARCH_MISC_INIT
1462 select ARMV8_MULTIENTRY
1463 select ARCH_SUPPORT_TFABOOT
1464 select BOARD_LATE_INIT
1465 select GPIO_EXTRA_HEADER
1467 Support for NXP LX2162AQDS platform.
1468 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1471 bool "Support HiKey 96boards Consumer Edition Platform"
1476 select GPIO_EXTRA_HEADER
1479 select SPECIFY_CONSOLE_INDEX
1482 Support for HiKey 96boards platform. It features a HI6220
1483 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1485 config TARGET_HIKEY960
1486 bool "Support HiKey960 96boards Consumer Edition Platform"
1490 select GPIO_EXTRA_HEADER
1495 Support for HiKey960 96boards platform. It features a HI3660
1496 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1498 config TARGET_POPLAR
1499 bool "Support Poplar 96boards Enterprise Edition Platform"
1503 select GPIO_EXTRA_HEADER
1508 Support for Poplar 96boards EE platform. It features a HI3798cv200
1509 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1510 making it capable of running any commercial set-top solution based on
1513 config TARGET_LS1012AQDS
1514 bool "Support ls1012aqds"
1517 select ARCH_SUPPORT_TFABOOT
1518 select BOARD_LATE_INIT
1519 select GPIO_EXTRA_HEADER
1521 Support for Freescale LS1012AQDS platform.
1522 The LS1012A Development System (QDS) is a high-performance
1523 development platform that supports the QorIQ LS1012A
1524 Layerscape Architecture processor.
1526 config TARGET_LS1012ARDB
1527 bool "Support ls1012ardb"
1530 select ARCH_SUPPORT_TFABOOT
1531 select BOARD_LATE_INIT
1532 select GPIO_EXTRA_HEADER
1536 Support for Freescale LS1012ARDB platform.
1537 The LS1012A Reference design board (RDB) is a high-performance
1538 development platform that supports the QorIQ LS1012A
1539 Layerscape Architecture processor.
1541 config TARGET_LS1012A2G5RDB
1542 bool "Support ls1012a2g5rdb"
1545 select ARCH_SUPPORT_TFABOOT
1546 select BOARD_LATE_INIT
1547 select GPIO_EXTRA_HEADER
1550 Support for Freescale LS1012A2G5RDB platform.
1551 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1552 development platform that supports the QorIQ LS1012A
1553 Layerscape Architecture processor.
1555 config TARGET_LS1012AFRWY
1556 bool "Support ls1012afrwy"
1559 select ARCH_SUPPORT_TFABOOT
1560 select BOARD_LATE_INIT
1561 select GPIO_EXTRA_HEADER
1565 Support for Freescale LS1012AFRWY platform.
1566 The LS1012A FRWY board (FRWY) is a high-performance
1567 development platform that supports the QorIQ LS1012A
1568 Layerscape Architecture processor.
1570 config TARGET_LS1012AFRDM
1571 bool "Support ls1012afrdm"
1574 select ARCH_SUPPORT_TFABOOT
1575 select GPIO_EXTRA_HEADER
1577 Support for Freescale LS1012AFRDM platform.
1578 The LS1012A Freedom board (FRDM) is a high-performance
1579 development platform that supports the QorIQ LS1012A
1580 Layerscape Architecture processor.
1582 config TARGET_LS1028AQDS
1583 bool "Support ls1028aqds"
1586 select ARMV8_MULTIENTRY
1587 select ARCH_SUPPORT_TFABOOT
1588 select BOARD_LATE_INIT
1589 select GPIO_EXTRA_HEADER
1591 Support for Freescale LS1028AQDS platform
1592 The LS1028A Development System (QDS) is a high-performance
1593 development platform that supports the QorIQ LS1028A
1594 Layerscape Architecture processor.
1596 config TARGET_LS1028ARDB
1597 bool "Support ls1028ardb"
1600 select ARMV8_MULTIENTRY
1601 select ARCH_SUPPORT_TFABOOT
1602 select BOARD_LATE_INIT
1603 select GPIO_EXTRA_HEADER
1605 Support for Freescale LS1028ARDB platform
1606 The LS1028A Development System (RDB) is a high-performance
1607 development platform that supports the QorIQ LS1028A
1608 Layerscape Architecture processor.
1610 config TARGET_LS1088ARDB
1611 bool "Support ls1088ardb"
1614 select ARMV8_MULTIENTRY
1615 select ARCH_SUPPORT_TFABOOT
1616 select BOARD_LATE_INIT
1618 select FSL_DDR_INTERACTIVE if !SD_BOOT
1619 select GPIO_EXTRA_HEADER
1621 Support for NXP LS1088ARDB platform.
1622 The LS1088A Reference design board (RDB) is a high-performance
1623 development platform that supports the QorIQ LS1088A
1624 Layerscape Architecture processor.
1626 config TARGET_LS1021AQDS
1627 bool "Support ls1021aqds"
1629 select ARCH_SUPPORT_PSCI
1630 select BOARD_EARLY_INIT_F
1631 select BOARD_LATE_INIT
1633 select CPU_V7_HAS_NONSEC
1634 select CPU_V7_HAS_VIRT
1635 select LS1_DEEP_SLEEP
1636 select PEN_ADDR_BIG_ENDIAN
1639 select FSL_DDR_INTERACTIVE
1640 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1641 select GPIO_EXTRA_HEADER
1642 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1645 config TARGET_LS1021ATWR
1646 bool "Support ls1021atwr"
1648 select ARCH_SUPPORT_PSCI
1649 select BOARD_EARLY_INIT_F
1650 select BOARD_LATE_INIT
1652 select CPU_V7_HAS_NONSEC
1653 select CPU_V7_HAS_VIRT
1654 select LS1_DEEP_SLEEP
1655 select PEN_ADDR_BIG_ENDIAN
1657 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1658 select GPIO_EXTRA_HEADER
1661 config TARGET_PG_WCOM_SELI8
1662 bool "Support Hitachi-Powergrids SELI8 service unit card"
1664 select ARCH_SUPPORT_PSCI
1665 select BOARD_EARLY_INIT_F
1666 select BOARD_LATE_INIT
1668 select CPU_V7_HAS_NONSEC
1669 select CPU_V7_HAS_VIRT
1671 select FSL_DDR_INTERACTIVE
1672 select GPIO_EXTRA_HEADER
1676 Support for Hitachi-Powergrids SELI8 service unit card.
1677 SELI8 is a QorIQ LS1021a based service unit card used
1678 in XMC20 and FOX615 product families.
1680 config TARGET_PG_WCOM_EXPU1
1681 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1683 select ARCH_SUPPORT_PSCI
1684 select BOARD_EARLY_INIT_F
1685 select BOARD_LATE_INIT
1687 select CPU_V7_HAS_NONSEC
1688 select CPU_V7_HAS_VIRT
1690 select FSL_DDR_INTERACTIVE
1694 Support for Hitachi-Powergrids EXPU1 service unit card.
1695 EXPU1 is a QorIQ LS1021a based service unit card used
1696 in XMC20 and FOX615 product families.
1698 config TARGET_LS1021ATSN
1699 bool "Support ls1021atsn"
1701 select ARCH_SUPPORT_PSCI
1702 select BOARD_EARLY_INIT_F
1703 select BOARD_LATE_INIT
1705 select CPU_V7_HAS_NONSEC
1706 select CPU_V7_HAS_VIRT
1707 select LS1_DEEP_SLEEP
1709 select GPIO_EXTRA_HEADER
1712 config TARGET_LS1021AIOT
1713 bool "Support ls1021aiot"
1715 select ARCH_SUPPORT_PSCI
1716 select BOARD_LATE_INIT
1718 select CPU_V7_HAS_NONSEC
1719 select CPU_V7_HAS_VIRT
1720 select PEN_ADDR_BIG_ENDIAN
1722 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1723 select GPIO_EXTRA_HEADER
1726 Support for Freescale LS1021AIOT platform.
1727 The LS1021A Freescale board (IOT) is a high-performance
1728 development platform that supports the QorIQ LS1021A
1729 Layerscape Architecture processor.
1731 config TARGET_LS1043AQDS
1732 bool "Support ls1043aqds"
1735 select ARMV8_MULTIENTRY
1736 select ARCH_SUPPORT_TFABOOT
1737 select BOARD_EARLY_INIT_F
1738 select BOARD_LATE_INIT
1740 select FSL_DDR_INTERACTIVE if !SPL
1741 select FSL_DSPI if !SPL_NO_DSPI
1742 select DM_SPI_FLASH if FSL_DSPI
1743 select GPIO_EXTRA_HEADER
1747 Support for Freescale LS1043AQDS platform.
1749 config TARGET_LS1043ARDB
1750 bool "Support ls1043ardb"
1753 select ARMV8_MULTIENTRY
1754 select ARCH_SUPPORT_TFABOOT
1755 select BOARD_EARLY_INIT_F
1756 select BOARD_LATE_INIT
1758 select FSL_DSPI if !SPL_NO_DSPI
1759 select DM_SPI_FLASH if FSL_DSPI
1760 select GPIO_EXTRA_HEADER
1762 Support for Freescale LS1043ARDB platform.
1764 config TARGET_LS1046AQDS
1765 bool "Support ls1046aqds"
1768 select ARMV8_MULTIENTRY
1769 select ARCH_SUPPORT_TFABOOT
1770 select BOARD_EARLY_INIT_F
1771 select BOARD_LATE_INIT
1772 select DM_SPI_FLASH if DM_SPI
1774 select FSL_DDR_BIST if !SPL
1775 select FSL_DDR_INTERACTIVE if !SPL
1776 select FSL_DDR_INTERACTIVE if !SPL
1777 select GPIO_EXTRA_HEADER
1780 Support for Freescale LS1046AQDS platform.
1781 The LS1046A Development System (QDS) is a high-performance
1782 development platform that supports the QorIQ LS1046A
1783 Layerscape Architecture processor.
1785 config TARGET_LS1046ARDB
1786 bool "Support ls1046ardb"
1789 select ARMV8_MULTIENTRY
1790 select ARCH_SUPPORT_TFABOOT
1791 select BOARD_EARLY_INIT_F
1792 select BOARD_LATE_INIT
1793 select DM_SPI_FLASH if DM_SPI
1794 select POWER_MC34VR500
1797 select FSL_DDR_INTERACTIVE if !SPL
1798 select GPIO_EXTRA_HEADER
1801 Support for Freescale LS1046ARDB platform.
1802 The LS1046A Reference Design Board (RDB) is a high-performance
1803 development platform that supports the QorIQ LS1046A
1804 Layerscape Architecture processor.
1806 config TARGET_LS1046AFRWY
1807 bool "Support ls1046afrwy"
1810 select ARMV8_MULTIENTRY
1811 select ARCH_SUPPORT_TFABOOT
1812 select BOARD_EARLY_INIT_F
1813 select BOARD_LATE_INIT
1814 select DM_SPI_FLASH if DM_SPI
1815 select GPIO_EXTRA_HEADER
1818 Support for Freescale LS1046AFRWY platform.
1819 The LS1046A Freeway Board (FRWY) is a high-performance
1820 development platform that supports the QorIQ LS1046A
1821 Layerscape Architecture processor.
1827 select ARMV8_MULTIENTRY
1842 select GPIO_EXTRA_HEADER
1843 select SPL_DM if SPL
1844 select SPL_DM_SPI if SPL
1845 select SPL_DM_SPI_FLASH if SPL
1846 select SPL_DM_I2C if SPL
1847 select SPL_DM_MMC if SPL
1848 select SPL_DM_SERIAL if SPL
1850 Support for Kontron SMARC-sAL28 board.
1853 bool "Support ten64"
1855 select ARCH_MISC_INIT
1857 select ARMV8_MULTIENTRY
1858 select ARCH_SUPPORT_TFABOOT
1859 select BOARD_LATE_INIT
1861 select FSL_DDR_INTERACTIVE if !SD_BOOT
1862 select GPIO_EXTRA_HEADER
1864 Support for Traverse Technologies Ten64 board, based
1867 config ARCH_UNIPHIER
1868 bool "Socionext UniPhier SoCs"
1869 select BOARD_LATE_INIT
1877 select OF_BOARD_SETUP
1881 select SPL_BOARD_INIT if SPL
1882 select SPL_DM if SPL
1883 select SPL_LIBCOMMON_SUPPORT if SPL
1884 select SPL_LIBGENERIC_SUPPORT if SPL
1885 select SPL_OF_CONTROL if SPL
1886 select SPL_PINCTRL if SPL
1889 imply DISTRO_DEFAULTS
1892 Support for UniPhier SoC family developed by Socionext Inc.
1893 (formerly, System LSI Business Division of Panasonic Corporation)
1895 config ARCH_SYNQUACER
1896 bool "Socionext SynQuacer SoCs"
1902 select SYSRESET_PSCI
1905 Support for SynQuacer SoC family developed by Socionext Inc.
1906 This SoC is used on 96boards EE DeveloperBox.
1909 bool "Support STMicroelectronics STM32 MCU with cortex M"
1916 bool "Support STMicroelectronics SoCs"
1925 Support for STMicroelectronics STiH407/10 SoC family.
1926 This SoC is used on Linaro 96Board STiH410-B2260
1929 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1930 select ARCH_MISC_INIT
1931 select ARCH_SUPPORT_TFABOOT
1932 select BOARD_LATE_INIT
1941 select OF_SYSTEM_SETUP
1946 select SYS_THUMB_BUILD
1950 imply OF_LIBFDT_OVERLAY
1951 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1955 Support for STM32MP SoC family developed by STMicroelectronics,
1956 MPUs based on ARM cortex A core
1957 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1958 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1960 SPL is the unsecure FSBL for the basic boot chain.
1962 config ARCH_ROCKCHIP
1963 bool "Support Rockchip SoCs"
1965 select BINMAN if SPL_OPTEE || SPL
1975 select ENABLE_ARM_SOC_BOOT0_HOOK
1978 select SPL_DM if SPL
1979 select SPL_DM_SPI if SPL
1980 select SPL_DM_SPI_FLASH if SPL
1982 select SYS_THUMB_BUILD if !ARM64
1985 imply DEBUG_UART_BOARD_INIT
1986 imply BOOTSTD_DEFAULTS
1988 imply SARADC_ROCKCHIP
1990 imply SPL_SYS_MALLOC_SIMPLE
1993 imply USB_FUNCTION_FASTBOOT
1995 config ARCH_OCTEONTX
1996 bool "Support OcteonTX SoCs"
1999 select GPIO_EXTRA_HEADER
2003 select BOARD_LATE_INIT
2004 select SYS_CACHE_SHIFT_7
2005 select SYS_PCI_64BIT if PCI
2006 imply OF_HAS_PRIOR_STAGE
2008 config ARCH_OCTEONTX2
2009 bool "Support OcteonTX2 SoCs"
2012 select GPIO_EXTRA_HEADER
2016 select BOARD_LATE_INIT
2017 select SYS_CACHE_SHIFT_7
2018 select SYS_PCI_64BIT if PCI
2019 imply OF_HAS_PRIOR_STAGE
2021 config TARGET_THUNDERX_88XX
2022 bool "Support ThunderX 88xx"
2024 select GPIO_EXTRA_HEADER
2027 select SYS_CACHE_SHIFT_7
2030 bool "Support Aspeed SoCs"
2035 config TARGET_DURIAN
2036 bool "Support Phytium Durian Platform"
2038 select GPIO_EXTRA_HEADER
2040 Support for durian platform.
2041 It has 2GB Sdram, uart and pcie.
2043 config TARGET_POMELO
2044 bool "Support Phytium Pomelo Platform"
2058 Support for pomelo platform.
2059 It has 8GB Sdram, uart and pcie.
2061 config TARGET_PRESIDIO_ASIC
2062 bool "Support Cortina Presidio ASIC Platform"
2066 config TARGET_XENGUEST_ARM64
2067 bool "Xen guest ARM64"
2071 select LINUX_KERNEL_IMAGE_HEADER
2073 imply OF_HAS_PRIOR_STAGE
2076 bool "Support HPE GXP SoCs"
2083 config SUPPORT_PASSING_ATAGS
2084 bool "Support pre-devicetree ATAG-based booting"
2086 imply SETUP_MEMORY_TAGS
2088 Support for booting older Linux kernels, using ATAGs rather than
2089 passing a devicetree. This is option is rarely used, and the
2090 semantics are defined at
2091 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2093 config SETUP_MEMORY_TAGS
2094 bool "Pass memory size information via ATAG"
2095 depends on SUPPORT_PASSING_ATAGS
2098 bool "Pass Linux kernel cmdline via ATAG"
2099 depends on SUPPORT_PASSING_ATAGS
2102 bool "Pass initrd starting point and size via ATAG"
2103 depends on SUPPORT_PASSING_ATAGS
2106 bool "Pass system revision via ATAG"
2107 depends on SUPPORT_PASSING_ATAGS
2110 bool "Pass system serial number via ATAG"
2111 depends on SUPPORT_PASSING_ATAGS
2113 config STATIC_MACH_TYPE
2114 bool "Statically define the Machine ID number"
2115 default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2117 When booting via ATAGs, enable this option if we know the correct
2118 machine ID number to use at compile time. Some systems will be
2119 passed the number dynamically by whatever loads U-Boot.
2122 int "Machine ID number"
2123 depends on STATIC_MACH_TYPE
2124 default 527 if TARGET_DS109
2125 default 1955 if TARGET_NOKIA_RX51
2126 default 3036 if TARGET_DS414
2127 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2129 When booting via ATAGs, the machine type must be passed as a number.
2130 For the full list see https://www.arm.linux.org.uk/developer/machines
2132 config ARCH_SUPPORT_TFABOOT
2136 bool "Support for booting from TF-A"
2137 depends on ARCH_SUPPORT_TFABOOT
2139 Some platforms support the setup of secure registers (for instance
2140 for CPU errata handling) or provide secure services like PSCI.
2141 Those services could also be provided by other firmware parts
2142 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2143 does not need to (and cannot) execute this code.
2144 Enabling this option will make a U-Boot binary that is relying
2145 on other firmware layers to provide secure functionality.
2147 config TI_SECURE_DEVICE
2148 bool "HS Device Type Support"
2149 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2151 If a high secure (HS) device type is being used, this config
2152 must be set. This option impacts various aspects of the
2153 build system (to create signed boot images that can be
2154 authenticated) and the code. See the doc/README.ti-secure
2155 file for further details.
2157 config SYS_KWD_CONFIG
2158 string "kwbimage config file path"
2159 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2160 default "arch/arm/mach-mvebu/kwbimage.cfg"
2162 Path within the source directory to the kwbimage.cfg file to use
2163 when packaging the U-Boot image for use.
2165 source "arch/arm/mach-apple/Kconfig"
2167 source "arch/arm/mach-aspeed/Kconfig"
2169 source "arch/arm/mach-at91/Kconfig"
2171 source "arch/arm/mach-bcm283x/Kconfig"
2173 source "arch/arm/mach-bcmbca/Kconfig"
2175 source "arch/arm/mach-bcmstb/Kconfig"
2177 source "arch/arm/mach-davinci/Kconfig"
2179 source "arch/arm/mach-exynos/Kconfig"
2181 source "arch/arm/mach-hpe/gxp/Kconfig"
2183 source "arch/arm/mach-highbank/Kconfig"
2185 source "arch/arm/mach-histb/Kconfig"
2187 source "arch/arm/mach-integrator/Kconfig"
2189 source "arch/arm/mach-ipq40xx/Kconfig"
2191 source "arch/arm/mach-k3/Kconfig"
2193 source "arch/arm/mach-keystone/Kconfig"
2195 source "arch/arm/mach-kirkwood/Kconfig"
2197 source "arch/arm/mach-lpc32xx/Kconfig"
2199 source "arch/arm/mach-mvebu/Kconfig"
2201 source "arch/arm/mach-octeontx/Kconfig"
2203 source "arch/arm/mach-octeontx2/Kconfig"
2205 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2207 source "arch/arm/mach-imx/mx3/Kconfig"
2209 source "arch/arm/mach-imx/mx5/Kconfig"
2211 source "arch/arm/mach-imx/mx6/Kconfig"
2213 source "arch/arm/mach-imx/mx7/Kconfig"
2215 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2217 source "arch/arm/mach-imx/imx8/Kconfig"
2219 source "arch/arm/mach-imx/imx8m/Kconfig"
2221 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2223 source "arch/arm/mach-imx/imx9/Kconfig"
2225 source "arch/arm/mach-imx/imxrt/Kconfig"
2227 source "arch/arm/mach-imx/mxs/Kconfig"
2229 source "arch/arm/mach-omap2/Kconfig"
2231 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2233 source "arch/arm/mach-orion5x/Kconfig"
2235 source "arch/arm/mach-owl/Kconfig"
2237 source "arch/arm/mach-rmobile/Kconfig"
2239 source "arch/arm/mach-meson/Kconfig"
2241 source "arch/arm/mach-mediatek/Kconfig"
2243 source "arch/arm/mach-qemu/Kconfig"
2245 source "arch/arm/mach-rockchip/Kconfig"
2247 source "arch/arm/mach-s5pc1xx/Kconfig"
2249 source "arch/arm/mach-snapdragon/Kconfig"
2251 source "arch/arm/mach-socfpga/Kconfig"
2253 source "arch/arm/mach-sti/Kconfig"
2255 source "arch/arm/mach-stm32/Kconfig"
2257 source "arch/arm/mach-stm32mp/Kconfig"
2259 source "arch/arm/mach-sunxi/Kconfig"
2261 source "arch/arm/mach-tegra/Kconfig"
2263 source "arch/arm/mach-u8500/Kconfig"
2265 source "arch/arm/mach-uniphier/Kconfig"
2267 source "arch/arm/cpu/armv7/vf610/Kconfig"
2269 source "arch/arm/mach-zynq/Kconfig"
2271 source "arch/arm/mach-zynqmp/Kconfig"
2273 source "arch/arm/mach-versal/Kconfig"
2275 source "arch/arm/mach-versal-net/Kconfig"
2277 source "arch/arm/mach-zynqmp-r5/Kconfig"
2279 source "arch/arm/cpu/armv7/Kconfig"
2281 source "arch/arm/cpu/armv8/Kconfig"
2283 source "arch/arm/mach-imx/Kconfig"
2285 source "arch/arm/mach-nexell/Kconfig"
2287 source "arch/arm/mach-npcm/Kconfig"
2289 source "board/armltd/total_compute/Kconfig"
2290 source "board/armltd/corstone1000/Kconfig"
2291 source "board/bosch/shc/Kconfig"
2292 source "board/bosch/guardian/Kconfig"
2293 source "board/Marvell/octeontx/Kconfig"
2294 source "board/Marvell/octeontx2/Kconfig"
2295 source "board/armltd/vexpress/Kconfig"
2296 source "board/armltd/vexpress64/Kconfig"
2297 source "board/cortina/presidio-asic/Kconfig"
2298 source "board/broadcom/bcmns/Kconfig"
2299 source "board/broadcom/bcmns3/Kconfig"
2300 source "board/cavium/thunderx/Kconfig"
2301 source "board/eets/pdu001/Kconfig"
2302 source "board/emulation/qemu-arm/Kconfig"
2303 source "board/freescale/ls2080aqds/Kconfig"
2304 source "board/freescale/ls2080ardb/Kconfig"
2305 source "board/freescale/ls1088a/Kconfig"
2306 source "board/freescale/ls1028a/Kconfig"
2307 source "board/freescale/ls1021aqds/Kconfig"
2308 source "board/freescale/ls1043aqds/Kconfig"
2309 source "board/freescale/ls1021atwr/Kconfig"
2310 source "board/freescale/ls1021atsn/Kconfig"
2311 source "board/freescale/ls1021aiot/Kconfig"
2312 source "board/freescale/ls1046aqds/Kconfig"
2313 source "board/freescale/ls1043ardb/Kconfig"
2314 source "board/freescale/ls1046ardb/Kconfig"
2315 source "board/freescale/ls1046afrwy/Kconfig"
2316 source "board/freescale/ls1012aqds/Kconfig"
2317 source "board/freescale/ls1012ardb/Kconfig"
2318 source "board/freescale/ls1012afrdm/Kconfig"
2319 source "board/freescale/lx2160a/Kconfig"
2320 source "board/grinn/chiliboard/Kconfig"
2321 source "board/hisilicon/hikey/Kconfig"
2322 source "board/hisilicon/hikey960/Kconfig"
2323 source "board/hisilicon/poplar/Kconfig"
2324 source "board/isee/igep003x/Kconfig"
2325 source "board/kontron/sl28/Kconfig"
2326 source "board/myir/mys_6ulx/Kconfig"
2327 source "board/samsung/common/Kconfig"
2328 source "board/siemens/common/Kconfig"
2329 source "board/seeed/npi_imx6ull/Kconfig"
2330 source "board/socionext/developerbox/Kconfig"
2331 source "board/st/stv0991/Kconfig"
2332 source "board/tcl/sl50/Kconfig"
2333 source "board/traverse/ten64/Kconfig"
2334 source "board/variscite/dart_6ul/Kconfig"
2335 source "board/vscom/baltos/Kconfig"
2336 source "board/phytium/durian/Kconfig"
2337 source "board/phytium/pomelo/Kconfig"
2338 source "board/xen/xenguest_arm64/Kconfig"
2340 source "arch/arm/Kconfig.debug"