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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / arch / arm / boot / dts / dra7.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
13
14 #define MAX_SOURCES 400
15
16 / {
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
22 chosen { };
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 spi0 = &qspi;
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
54 };
55
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
66 };
67
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a15";
83 reg = <0>;
84
85 operating-points-v2 = <&cpu0_opp_table>;
86
87 clocks = <&dpll_mpu_ck>;
88 clock-names = "cpu";
89
90 clock-latency = <300000>; /* From omap-cpufreq driver */
91
92 /* cooling options */
93 #cooling-cells = <2>; /* min followed by max */
94
95 vbb-supply = <&abb_mpu>;
96 };
97 };
98
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
101 syscon = <&scm_wkup>;
102
103 opp_nom-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
106 <1060000 850000 1150000>;
107 opp-supported-hw = <0xFF 0x01>;
108 opp-suspend;
109 };
110
111 opp_od-1176000000 {
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
114 <1160000 885000 1160000>;
115
116 opp-supported-hw = <0xFF 0x02>;
117 };
118
119 opp_high@1500000000 {
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
122 <1210000 950000 1250000>;
123 opp-supported-hw = <0xFF 0x04>;
124 };
125 };
126
127 /*
128 * The soc node represents the soc top level view. It is used for IPs
129 * that are not memory mapped in the MPU view or for the MPU itself.
130 */
131 soc {
132 compatible = "ti,omap-infra";
133 mpu {
134 compatible = "ti,omap5-mpu";
135 ti,hwmods = "mpu";
136 };
137 };
138
139 /*
140 * XXX: Use a flat representation of the SOC interconnect.
141 * The real OMAP interconnect network is quite complex.
142 * Since it will not bring real advantage to represent that in DT for
143 * the moment, just use a fake OCP bus entry to represent the whole bus
144 * hierarchy.
145 */
146 ocp: ocp {
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x0 0xc0000000>;
151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
152 ti,hwmods = "l3_main_1", "l3_main_2";
153 reg = <0x0 0x44000000 0x0 0x1000000>,
154 <0x0 0x45000000 0x0 0x1000>;
155 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
156 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
157
158 l4_cfg: interconnect@4a000000 {
159 };
160 l4_wkup: interconnect@4ae00000 {
161 };
162 l4_per1: interconnect@48000000 {
163 };
164 l4_per2: interconnect@48400000 {
165 };
166 l4_per3: interconnect@48800000 {
167 };
168
169 axi@0 {
170 compatible = "simple-bus";
171 #size-cells = <1>;
172 #address-cells = <1>;
173 ranges = <0x51000000 0x51000000 0x3000
174 0x0 0x20000000 0x10000000>;
175 dma-ranges;
176 /**
177 * To enable PCI endpoint mode, disable the pcie1_rc
178 * node and enable pcie1_ep mode.
179 */
180 pcie1_rc: pcie@51000000 {
181 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
182 reg-names = "rc_dbics", "ti_conf", "config";
183 interrupts = <0 232 0x4>, <0 233 0x4>;
184 #address-cells = <3>;
185 #size-cells = <2>;
186 device_type = "pci";
187 ranges = <0x81000000 0 0 0x03000 0 0x00010000
188 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
189 bus-range = <0x00 0xff>;
190 #interrupt-cells = <1>;
191 num-lanes = <1>;
192 linux,pci-domain = <0>;
193 ti,hwmods = "pcie1";
194 phys = <&pcie1_phy>;
195 phy-names = "pcie-phy0";
196 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
197 interrupt-map-mask = <0 0 0 7>;
198 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
199 <0 0 0 2 &pcie1_intc 2>,
200 <0 0 0 3 &pcie1_intc 3>,
201 <0 0 0 4 &pcie1_intc 4>;
202 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
203 status = "disabled";
204 pcie1_intc: interrupt-controller {
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <1>;
208 };
209 };
210
211 pcie1_ep: pcie_ep@51000000 {
212 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
213 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
214 interrupts = <0 232 0x4>;
215 num-lanes = <1>;
216 num-ib-windows = <4>;
217 num-ob-windows = <16>;
218 ti,hwmods = "pcie1";
219 phys = <&pcie1_phy>;
220 phy-names = "pcie-phy0";
221 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
223 status = "disabled";
224 };
225 };
226
227 axi@1 {
228 compatible = "simple-bus";
229 #size-cells = <1>;
230 #address-cells = <1>;
231 ranges = <0x51800000 0x51800000 0x3000
232 0x0 0x30000000 0x10000000>;
233 dma-ranges;
234 status = "disabled";
235 pcie2_rc: pcie@51800000 {
236 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
237 reg-names = "rc_dbics", "ti_conf", "config";
238 interrupts = <0 355 0x4>, <0 356 0x4>;
239 #address-cells = <3>;
240 #size-cells = <2>;
241 device_type = "pci";
242 ranges = <0x81000000 0 0 0x03000 0 0x00010000
243 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
244 bus-range = <0x00 0xff>;
245 #interrupt-cells = <1>;
246 num-lanes = <1>;
247 linux,pci-domain = <1>;
248 ti,hwmods = "pcie2";
249 phys = <&pcie2_phy>;
250 phy-names = "pcie-phy0";
251 interrupt-map-mask = <0 0 0 7>;
252 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
253 <0 0 0 2 &pcie2_intc 2>,
254 <0 0 0 3 &pcie2_intc 3>,
255 <0 0 0 4 &pcie2_intc 4>;
256 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
257 pcie2_intc: interrupt-controller {
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <1>;
261 };
262 };
263 };
264
265 ocmcram1: ocmcram@40300000 {
266 compatible = "mmio-sram";
267 reg = <0x40300000 0x80000>;
268 ranges = <0x0 0x40300000 0x80000>;
269 #address-cells = <1>;
270 #size-cells = <1>;
271 /*
272 * This is a placeholder for an optional reserved
273 * region for use by secure software. The size
274 * of this region is not known until runtime so it
275 * is set as zero to either be updated to reserve
276 * space or left unchanged to leave all SRAM for use.
277 * On HS parts that that require the reserved region
278 * either the bootloader can update the size to
279 * the required amount or the node can be overridden
280 * from the board dts file for the secure platform.
281 */
282 sram-hs@0 {
283 compatible = "ti,secure-ram";
284 reg = <0x0 0x0>;
285 };
286 };
287
288 /*
289 * NOTE: ocmcram2 and ocmcram3 are not available on all
290 * DRA7xx and AM57xx variants. Confirm availability in
291 * the data manual for the exact part number in use
292 * before enabling these nodes in the board dts file.
293 */
294 ocmcram2: ocmcram@40400000 {
295 status = "disabled";
296 compatible = "mmio-sram";
297 reg = <0x40400000 0x100000>;
298 ranges = <0x0 0x40400000 0x100000>;
299 #address-cells = <1>;
300 #size-cells = <1>;
301 };
302
303 ocmcram3: ocmcram@40500000 {
304 status = "disabled";
305 compatible = "mmio-sram";
306 reg = <0x40500000 0x100000>;
307 ranges = <0x0 0x40500000 0x100000>;
308 #address-cells = <1>;
309 #size-cells = <1>;
310 };
311
312 bandgap: bandgap@4a0021e0 {
313 reg = <0x4a0021e0 0xc
314 0x4a00232c 0xc
315 0x4a002380 0x2c
316 0x4a0023C0 0x3c
317 0x4a002564 0x8
318 0x4a002574 0x50>;
319 compatible = "ti,dra752-bandgap";
320 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
321 #thermal-sensor-cells = <1>;
322 };
323
324 dsp1_system: dsp_system@40d00000 {
325 compatible = "syscon";
326 reg = <0x40d00000 0x100>;
327 };
328
329 dra7_iodelay_core: padconf@4844a000 {
330 compatible = "ti,dra7-iodelay";
331 reg = <0x4844a000 0x0d1c>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 #pinctrl-cells = <2>;
335 };
336
337 target-module@43300000 {
338 compatible = "ti,sysc-omap4", "ti,sysc";
339 reg = <0x43300000 0x4>;
340 reg-names = "rev";
341 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
342 clock-names = "fck";
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges = <0x0 0x43300000 0x100000>;
346
347 edma: dma@0 {
348 compatible = "ti,edma3-tpcc";
349 reg = <0 0x100000>;
350 reg-names = "edma3_cc";
351 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-names = "edma3_ccint", "edma3_mperr",
355 "edma3_ccerrint";
356 dma-requests = <64>;
357 #dma-cells = <2>;
358
359 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
360
361 /*
362 * memcpy is disabled, can be enabled with:
363 * ti,edma-memcpy-channels = <20 21>;
364 * for example. Note that these channels need to be
365 * masked in the xbar as well.
366 */
367 };
368 };
369
370 target-module@43400000 {
371 compatible = "ti,sysc-omap4", "ti,sysc";
372 reg = <0x43400000 0x4>;
373 reg-names = "rev";
374 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
375 clock-names = "fck";
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges = <0x0 0x43400000 0x100000>;
379
380 edma_tptc0: dma@0 {
381 compatible = "ti,edma3-tptc";
382 reg = <0 0x100000>;
383 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-names = "edma3_tcerrint";
385 };
386 };
387
388 target-module@43500000 {
389 compatible = "ti,sysc-omap4", "ti,sysc";
390 reg = <0x43500000 0x4>;
391 reg-names = "rev";
392 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
393 clock-names = "fck";
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0x0 0x43500000 0x100000>;
397
398 edma_tptc1: dma@0 {
399 compatible = "ti,edma3-tptc";
400 reg = <0 0x100000>;
401 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "edma3_tcerrint";
403 };
404 };
405
406 dmm@4e000000 {
407 compatible = "ti,omap5-dmm";
408 reg = <0x4e000000 0x800>;
409 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
410 ti,hwmods = "dmm";
411 };
412
413 target-module@40d01000 {
414 compatible = "ti,sysc-omap2", "ti,sysc";
415 reg = <0x40d01000 0x4>,
416 <0x40d01010 0x4>,
417 <0x40d01014 0x4>;
418 reg-names = "rev", "sysc", "syss";
419 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
420 <SYSC_IDLE_NO>,
421 <SYSC_IDLE_SMART>;
422 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
423 SYSC_OMAP2_SOFTRESET |
424 SYSC_OMAP2_AUTOIDLE)>;
425 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
426 clock-names = "fck";
427 resets = <&prm_dsp1 1>;
428 reset-names = "rstctrl";
429 ranges = <0x0 0x40d01000 0x1000>;
430 #size-cells = <1>;
431 #address-cells = <1>;
432
433 mmu0_dsp1: mmu@0 {
434 compatible = "ti,dra7-dsp-iommu";
435 reg = <0x0 0x100>;
436 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
437 #iommu-cells = <0>;
438 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
439 };
440 };
441
442 target-module@40d02000 {
443 compatible = "ti,sysc-omap2", "ti,sysc";
444 reg = <0x40d02000 0x4>,
445 <0x40d02010 0x4>,
446 <0x40d02014 0x4>;
447 reg-names = "rev", "sysc", "syss";
448 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
449 <SYSC_IDLE_NO>,
450 <SYSC_IDLE_SMART>;
451 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
452 SYSC_OMAP2_SOFTRESET |
453 SYSC_OMAP2_AUTOIDLE)>;
454 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
455 clock-names = "fck";
456 resets = <&prm_dsp1 1>;
457 reset-names = "rstctrl";
458 ranges = <0x0 0x40d02000 0x1000>;
459 #size-cells = <1>;
460 #address-cells = <1>;
461
462 mmu1_dsp1: mmu@0 {
463 compatible = "ti,dra7-dsp-iommu";
464 reg = <0x0 0x100>;
465 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
466 #iommu-cells = <0>;
467 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
468 };
469 };
470
471 target-module@58882000 {
472 compatible = "ti,sysc-omap2", "ti,sysc";
473 reg = <0x58882000 0x4>,
474 <0x58882010 0x4>,
475 <0x58882014 0x4>;
476 reg-names = "rev", "sysc", "syss";
477 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
478 <SYSC_IDLE_NO>,
479 <SYSC_IDLE_SMART>;
480 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
481 SYSC_OMAP2_SOFTRESET |
482 SYSC_OMAP2_AUTOIDLE)>;
483 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
484 clock-names = "fck";
485 resets = <&prm_ipu 2>;
486 reset-names = "rstctrl";
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges = <0x0 0x58882000 0x100>;
490
491 mmu_ipu1: mmu@0 {
492 compatible = "ti,dra7-iommu";
493 reg = <0x0 0x100>;
494 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
495 #iommu-cells = <0>;
496 ti,iommu-bus-err-back;
497 };
498 };
499
500 target-module@55082000 {
501 compatible = "ti,sysc-omap2", "ti,sysc";
502 reg = <0x55082000 0x4>,
503 <0x55082010 0x4>,
504 <0x55082014 0x4>;
505 reg-names = "rev", "sysc", "syss";
506 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
507 <SYSC_IDLE_NO>,
508 <SYSC_IDLE_SMART>;
509 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
510 SYSC_OMAP2_SOFTRESET |
511 SYSC_OMAP2_AUTOIDLE)>;
512 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
513 clock-names = "fck";
514 resets = <&prm_core 2>;
515 reset-names = "rstctrl";
516 #address-cells = <1>;
517 #size-cells = <1>;
518 ranges = <0x0 0x55082000 0x100>;
519
520 mmu_ipu2: mmu@0 {
521 compatible = "ti,dra7-iommu";
522 reg = <0x0 0x100>;
523 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
524 #iommu-cells = <0>;
525 ti,iommu-bus-err-back;
526 };
527 };
528
529 abb_mpu: regulator-abb-mpu {
530 compatible = "ti,abb-v3";
531 regulator-name = "abb_mpu";
532 #address-cells = <0>;
533 #size-cells = <0>;
534 clocks = <&sys_clkin1>;
535 ti,settling-time = <50>;
536 ti,clock-cycles = <16>;
537
538 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
539 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
540 <0x4ae0c158 0x4>;
541 reg-names = "setup-address", "control-address",
542 "int-address", "efuse-address",
543 "ldo-address";
544 ti,tranxdone-status-mask = <0x80>;
545 /* LDOVBBMPU_FBB_MUX_CTRL */
546 ti,ldovbb-override-mask = <0x400>;
547 /* LDOVBBMPU_FBB_VSET_OUT */
548 ti,ldovbb-vset-mask = <0x1F>;
549
550 /*
551 * NOTE: only FBB mode used but actual vset will
552 * determine final biasing
553 */
554 ti,abb_info = <
555 /*uV ABB efuse rbb_m fbb_m vset_m*/
556 1060000 0 0x0 0 0x02000000 0x01F00000
557 1160000 0 0x4 0 0x02000000 0x01F00000
558 1210000 0 0x8 0 0x02000000 0x01F00000
559 >;
560 };
561
562 abb_ivahd: regulator-abb-ivahd {
563 compatible = "ti,abb-v3";
564 regulator-name = "abb_ivahd";
565 #address-cells = <0>;
566 #size-cells = <0>;
567 clocks = <&sys_clkin1>;
568 ti,settling-time = <50>;
569 ti,clock-cycles = <16>;
570
571 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
572 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
573 <0x4a002470 0x4>;
574 reg-names = "setup-address", "control-address",
575 "int-address", "efuse-address",
576 "ldo-address";
577 ti,tranxdone-status-mask = <0x40000000>;
578 /* LDOVBBIVA_FBB_MUX_CTRL */
579 ti,ldovbb-override-mask = <0x400>;
580 /* LDOVBBIVA_FBB_VSET_OUT */
581 ti,ldovbb-vset-mask = <0x1F>;
582
583 /*
584 * NOTE: only FBB mode used but actual vset will
585 * determine final biasing
586 */
587 ti,abb_info = <
588 /*uV ABB efuse rbb_m fbb_m vset_m*/
589 1055000 0 0x0 0 0x02000000 0x01F00000
590 1150000 0 0x4 0 0x02000000 0x01F00000
591 1250000 0 0x8 0 0x02000000 0x01F00000
592 >;
593 };
594
595 abb_dspeve: regulator-abb-dspeve {
596 compatible = "ti,abb-v3";
597 regulator-name = "abb_dspeve";
598 #address-cells = <0>;
599 #size-cells = <0>;
600 clocks = <&sys_clkin1>;
601 ti,settling-time = <50>;
602 ti,clock-cycles = <16>;
603
604 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
605 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
606 <0x4a00246c 0x4>;
607 reg-names = "setup-address", "control-address",
608 "int-address", "efuse-address",
609 "ldo-address";
610 ti,tranxdone-status-mask = <0x20000000>;
611 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
612 ti,ldovbb-override-mask = <0x400>;
613 /* LDOVBBDSPEVE_FBB_VSET_OUT */
614 ti,ldovbb-vset-mask = <0x1F>;
615
616 /*
617 * NOTE: only FBB mode used but actual vset will
618 * determine final biasing
619 */
620 ti,abb_info = <
621 /*uV ABB efuse rbb_m fbb_m vset_m*/
622 1055000 0 0x0 0 0x02000000 0x01F00000
623 1150000 0 0x4 0 0x02000000 0x01F00000
624 1250000 0 0x8 0 0x02000000 0x01F00000
625 >;
626 };
627
628 abb_gpu: regulator-abb-gpu {
629 compatible = "ti,abb-v3";
630 regulator-name = "abb_gpu";
631 #address-cells = <0>;
632 #size-cells = <0>;
633 clocks = <&sys_clkin1>;
634 ti,settling-time = <50>;
635 ti,clock-cycles = <16>;
636
637 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
638 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
639 <0x4ae0c154 0x4>;
640 reg-names = "setup-address", "control-address",
641 "int-address", "efuse-address",
642 "ldo-address";
643 ti,tranxdone-status-mask = <0x10000000>;
644 /* LDOVBBGPU_FBB_MUX_CTRL */
645 ti,ldovbb-override-mask = <0x400>;
646 /* LDOVBBGPU_FBB_VSET_OUT */
647 ti,ldovbb-vset-mask = <0x1F>;
648
649 /*
650 * NOTE: only FBB mode used but actual vset will
651 * determine final biasing
652 */
653 ti,abb_info = <
654 /*uV ABB efuse rbb_m fbb_m vset_m*/
655 1090000 0 0x0 0 0x02000000 0x01F00000
656 1210000 0 0x4 0 0x02000000 0x01F00000
657 1280000 0 0x8 0 0x02000000 0x01F00000
658 >;
659 };
660
661 qspi: spi@4b300000 {
662 compatible = "ti,dra7xxx-qspi";
663 reg = <0x4b300000 0x100>,
664 <0x5c000000 0x4000000>;
665 reg-names = "qspi_base", "qspi_mmap";
666 syscon-chipselects = <&scm_conf 0x558>;
667 #address-cells = <1>;
668 #size-cells = <0>;
669 ti,hwmods = "qspi";
670 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
671 clock-names = "fck";
672 num-cs = <4>;
673 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
674 status = "disabled";
675 };
676
677 /* OCP2SCP3 */
678 sata: sata@4a141100 {
679 compatible = "snps,dwc-ahci";
680 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
681 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
682 phys = <&sata_phy>;
683 phy-names = "sata-phy";
684 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
685 ti,hwmods = "sata";
686 ports-implemented = <0x1>;
687 };
688
689 /* OCP2SCP1 */
690 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
691 gpmc: gpmc@50000000 {
692 compatible = "ti,am3352-gpmc";
693 ti,hwmods = "gpmc";
694 reg = <0x50000000 0x37c>; /* device IO registers */
695 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
696 dmas = <&edma_xbar 4 0>;
697 dma-names = "rxtx";
698 gpmc,num-cs = <8>;
699 gpmc,num-waitpins = <2>;
700 #address-cells = <2>;
701 #size-cells = <1>;
702 interrupt-controller;
703 #interrupt-cells = <2>;
704 gpio-controller;
705 #gpio-cells = <2>;
706 status = "disabled";
707 };
708
709 target-module@56000000 {
710 compatible = "ti,sysc-omap4", "ti,sysc";
711 reg = <0x5600fe00 0x4>,
712 <0x5600fe10 0x4>;
713 reg-names = "rev", "sysc";
714 ti,sysc-midle = <SYSC_IDLE_FORCE>,
715 <SYSC_IDLE_NO>,
716 <SYSC_IDLE_SMART>;
717 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
718 <SYSC_IDLE_NO>,
719 <SYSC_IDLE_SMART>;
720 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
721 clock-names = "fck";
722 #address-cells = <1>;
723 #size-cells = <1>;
724 ranges = <0 0x56000000 0x2000000>;
725 };
726
727 crossbar_mpu: crossbar@4a002a48 {
728 compatible = "ti,irq-crossbar";
729 reg = <0x4a002a48 0x130>;
730 interrupt-controller;
731 interrupt-parent = <&wakeupgen>;
732 #interrupt-cells = <3>;
733 ti,max-irqs = <160>;
734 ti,max-crossbar-sources = <MAX_SOURCES>;
735 ti,reg-size = <2>;
736 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
737 ti,irqs-skip = <10 133 139 140>;
738 ti,irqs-safe-map = <0>;
739 };
740
741 target-module@58000000 {
742 compatible = "ti,sysc-omap2", "ti,sysc";
743 reg = <0x58000000 4>,
744 <0x58000014 4>;
745 reg-names = "rev", "syss";
746 ti,syss-mask = <1>;
747 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
748 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
749 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
750 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
751 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
752 #address-cells = <1>;
753 #size-cells = <1>;
754 ranges = <0 0x58000000 0x800000>;
755
756 dss: dss@0 {
757 compatible = "ti,dra7-dss";
758 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
759 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
760 status = "disabled";
761 /* CTRL_CORE_DSS_PLL_CONTROL */
762 syscon-pll-ctrl = <&scm_conf 0x538>;
763 #address-cells = <1>;
764 #size-cells = <1>;
765 ranges = <0 0 0x800000>;
766
767 target-module@1000 {
768 compatible = "ti,sysc-omap2", "ti,sysc";
769 reg = <0x1000 0x4>,
770 <0x1010 0x4>,
771 <0x1014 0x4>;
772 reg-names = "rev", "sysc", "syss";
773 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
774 <SYSC_IDLE_NO>,
775 <SYSC_IDLE_SMART>;
776 ti,sysc-midle = <SYSC_IDLE_FORCE>,
777 <SYSC_IDLE_NO>,
778 <SYSC_IDLE_SMART>;
779 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
780 SYSC_OMAP2_ENAWAKEUP |
781 SYSC_OMAP2_SOFTRESET |
782 SYSC_OMAP2_AUTOIDLE)>;
783 ti,syss-mask = <1>;
784 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
785 clock-names = "fck";
786 #address-cells = <1>;
787 #size-cells = <1>;
788 ranges = <0 0x1000 0x1000>;
789
790 dispc@0 {
791 compatible = "ti,dra7-dispc";
792 reg = <0 0x1000>;
793 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
795 clock-names = "fck";
796 /* CTRL_CORE_SMA_SW_1 */
797 syscon-pol = <&scm_conf 0x534>;
798 };
799 };
800
801 target-module@40000 {
802 compatible = "ti,sysc-omap4", "ti,sysc";
803 reg = <0x40000 0x4>,
804 <0x40010 0x4>;
805 reg-names = "rev", "sysc";
806 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
807 <SYSC_IDLE_NO>,
808 <SYSC_IDLE_SMART>,
809 <SYSC_IDLE_SMART_WKUP>;
810 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
811 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
812 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
813 clock-names = "fck", "dss_clk";
814 #address-cells = <1>;
815 #size-cells = <1>;
816 ranges = <0 0x40000 0x40000>;
817
818 hdmi: encoder@0 {
819 compatible = "ti,dra7-hdmi";
820 reg = <0 0x200>,
821 <0x200 0x80>,
822 <0x300 0x80>,
823 <0x20000 0x19000>;
824 reg-names = "wp", "pll", "phy", "core";
825 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
826 status = "disabled";
827 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
828 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
829 clock-names = "fck", "sys_clk";
830 dmas = <&sdma_xbar 76>;
831 dma-names = "audio_tx";
832 };
833 };
834 };
835 };
836
837 aes1_target: target-module@4b500000 {
838 compatible = "ti,sysc-omap2", "ti,sysc";
839 reg = <0x4b500080 0x4>,
840 <0x4b500084 0x4>,
841 <0x4b500088 0x4>;
842 reg-names = "rev", "sysc", "syss";
843 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
844 SYSC_OMAP2_AUTOIDLE)>;
845 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
846 <SYSC_IDLE_NO>,
847 <SYSC_IDLE_SMART>,
848 <SYSC_IDLE_SMART_WKUP>;
849 ti,syss-mask = <1>;
850 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
851 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
852 clock-names = "fck";
853 #address-cells = <1>;
854 #size-cells = <1>;
855 ranges = <0x0 0x4b500000 0x1000>;
856
857 aes1: aes@0 {
858 compatible = "ti,omap4-aes";
859 reg = <0 0xa0>;
860 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
861 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
862 dma-names = "tx", "rx";
863 clocks = <&l3_iclk_div>;
864 clock-names = "fck";
865 };
866 };
867
868 aes2_target: target-module@4b700000 {
869 compatible = "ti,sysc-omap2", "ti,sysc";
870 reg = <0x4b700080 0x4>,
871 <0x4b700084 0x4>,
872 <0x4b700088 0x4>;
873 reg-names = "rev", "sysc", "syss";
874 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
875 SYSC_OMAP2_AUTOIDLE)>;
876 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
877 <SYSC_IDLE_NO>,
878 <SYSC_IDLE_SMART>,
879 <SYSC_IDLE_SMART_WKUP>;
880 ti,syss-mask = <1>;
881 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
882 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
883 clock-names = "fck";
884 #address-cells = <1>;
885 #size-cells = <1>;
886 ranges = <0x0 0x4b700000 0x1000>;
887
888 aes2: aes@0 {
889 compatible = "ti,omap4-aes";
890 reg = <0 0xa0>;
891 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
892 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
893 dma-names = "tx", "rx";
894 clocks = <&l3_iclk_div>;
895 clock-names = "fck";
896 };
897 };
898
899 sham_target: target-module@4b101000 {
900 compatible = "ti,sysc-omap3-sham", "ti,sysc";
901 reg = <0x4b101100 0x4>,
902 <0x4b101110 0x4>,
903 <0x4b101114 0x4>;
904 reg-names = "rev", "sysc", "syss";
905 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
906 SYSC_OMAP2_AUTOIDLE)>;
907 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
908 <SYSC_IDLE_NO>,
909 <SYSC_IDLE_SMART>;
910 ti,syss-mask = <1>;
911 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
912 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
913 clock-names = "fck";
914 #address-cells = <1>;
915 #size-cells = <1>;
916 ranges = <0x0 0x4b101000 0x1000>;
917
918 sham: sham@0 {
919 compatible = "ti,omap5-sham";
920 reg = <0 0x300>;
921 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
922 dmas = <&edma_xbar 119 0>;
923 dma-names = "rx";
924 clocks = <&l3_iclk_div>;
925 clock-names = "fck";
926 };
927 };
928
929 opp_supply_mpu: opp-supply@4a003b20 {
930 compatible = "ti,omap5-opp-supply";
931 reg = <0x4a003b20 0xc>;
932 ti,efuse-settings = <
933 /* uV offset */
934 1060000 0x0
935 1160000 0x4
936 1210000 0x8
937 >;
938 ti,absolute-max-voltage-uv = <1500000>;
939 };
940
941 };
942
943 thermal_zones: thermal-zones {
944 #include "omap4-cpu-thermal.dtsi"
945 #include "omap5-gpu-thermal.dtsi"
946 #include "omap5-core-thermal.dtsi"
947 #include "dra7-dspeve-thermal.dtsi"
948 #include "dra7-iva-thermal.dtsi"
949 };
950
951 };
952
953 &cpu_thermal {
954 polling-delay = <500>; /* milliseconds */
955 coefficients = <0 2000>;
956 };
957
958 &gpu_thermal {
959 coefficients = <0 2000>;
960 };
961
962 &core_thermal {
963 coefficients = <0 2000>;
964 };
965
966 &dspeve_thermal {
967 coefficients = <0 2000>;
968 };
969
970 &iva_thermal {
971 coefficients = <0 2000>;
972 };
973
974 &cpu_crit {
975 temperature = <120000>; /* milli Celsius */
976 };
977
978 &core_crit {
979 temperature = <120000>; /* milli Celsius */
980 };
981
982 &gpu_crit {
983 temperature = <120000>; /* milli Celsius */
984 };
985
986 &dspeve_crit {
987 temperature = <120000>; /* milli Celsius */
988 };
989
990 &iva_crit {
991 temperature = <120000>; /* milli Celsius */
992 };
993
994 #include "dra7-l4.dtsi"
995 #include "dra7xx-clocks.dtsi"
996
997 &prm {
998 prm_dsp1: prm@400 {
999 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1000 reg = <0x400 0x100>;
1001 #reset-cells = <1>;
1002 };
1003
1004 prm_ipu: prm@500 {
1005 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1006 reg = <0x500 0x100>;
1007 #reset-cells = <1>;
1008 };
1009
1010 prm_core: prm@700 {
1011 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1012 reg = <0x700 0x100>;
1013 #reset-cells = <1>;
1014 };
1015
1016 prm_iva: prm@f00 {
1017 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1018 reg = <0xf00 0x100>;
1019 };
1020
1021 prm_dsp2: prm@1b00 {
1022 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1023 reg = <0x1b00 0x40>;
1024 #reset-cells = <1>;
1025 };
1026
1027 prm_eve1: prm@1b40 {
1028 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1029 reg = <0x1b40 0x40>;
1030 };
1031
1032 prm_eve2: prm@1b80 {
1033 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1034 reg = <0x1b80 0x40>;
1035 };
1036
1037 prm_eve3: prm@1bc0 {
1038 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1039 reg = <0x1bc0 0x40>;
1040 };
1041
1042 prm_eve4: prm@1c00 {
1043 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1044 reg = <0x1c00 0x60>;
1045 };
1046 };
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