arch/arm/boot/dts/r8a7740.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
   4  *
   5  * Copyright (C) 2012 Renesas Solutions Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a7740-clock.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         compatible = "renesas,r8a7740";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         compatible = "arm,cortex-a9";
  23                         device_type = "cpu";
  24                         reg = <0x0>;
  25                         clock-frequency = <800000000>;
  26                         power-domains = <&pd_a3sm>;
  27                         next-level-cache = <&L2>;
  28                 };
  29         };
  30
  31         gic: interrupt-controller@c2800000 {
  32                 compatible = "arm,pl390";
  33                 #interrupt-cells = <3>;
  34                 interrupt-controller;
  35                 reg = <0xc2800000 0x1000>,
  36                       <0xc2000000 0x1000>;
  37         };
  38
  39         L2: cache-controller@f0100000 {
  40                 compatible = "arm,pl310-cache";
  41                 reg = <0xf0100000 0x1000>;
  42                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  43                 power-domains = <&pd_a3sm>;
  44                 arm,data-latency = <3 3 3>;
  45                 arm,tag-latency = <2 2 2>;
  46                 arm,shared-override;
  47                 cache-unified;
  48                 cache-level = <2>;
  49         };
  50
  51         dbsc3: memory-controller@fe400000 {
  52                 compatible = "renesas,dbsc3-r8a7740";
  53                 reg = <0xfe400000 0x400>;
  54                 power-domains = <&pd_a4s>;
  55         };
  56
  57         pmu {
  58                 compatible = "arm,cortex-a9-pmu";
  59                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  60         };
  61
  62         ptm {
  63                 compatible = "arm,coresight-etm3x";
  64                 power-domains = <&pd_d4>;
  65         };
  66
  67         ceu0: ceu@fe910000 {
  68                 reg = <0xfe910000 0x3000>;
  69                 compatible = "renesas,r8a7740-ceu";
  70                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
  71                 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
  72                 power-domains = <&pd_a4r>;
  73                 status = "disabled";
  74         };
  75
  76         ceu1: ceu@fe914000 {
  77                 reg = <0xfe914000 0x3000>;
  78                 compatible = "renesas,r8a7740-ceu";
  79                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  80                 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
  81                 power-domains = <&pd_a4r>;
  82                 status = "disabled";
  83         };
  84
  85         cmt1: timer@e6138000 {
  86                 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
  87                 reg = <0xe6138000 0x170>;
  88                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  89                 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
  90                 clock-names = "fck";
  91                 power-domains = <&pd_c5>;
  92                 status = "disabled";
  93         };
  94
  95         /* irqpin0: IRQ0 - IRQ7 */
  96         irqpin0: interrupt-controller@e6900000 {
  97                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  98                 #interrupt-cells = <2>;
  99                 interrupt-controller;
 100                 reg = <0xe6900000 4>,
 101                         <0xe6900010 4>,
 102                         <0xe6900020 1>,
 103                         <0xe6900040 1>,
 104                         <0xe6900060 1>;
 105                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 108                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 109                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 110                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 111                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 112                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 113                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 114                 power-domains = <&pd_a4s>;
 115         };
 116
 117         /* irqpin1: IRQ8 - IRQ15 */
 118         irqpin1: interrupt-controller@e6900004 {
 119                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 120                 #interrupt-cells = <2>;
 121                 interrupt-controller;
 122                 reg = <0xe6900004 4>,
 123                         <0xe6900014 4>,
 124                         <0xe6900024 1>,
 125                         <0xe6900044 1>,
 126                         <0xe6900064 1>;
 127                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 128                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 130                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 131                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 135                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 136                 power-domains = <&pd_a4s>;
 137         };
 138
 139         /* irqpin2: IRQ16 - IRQ23 */
 140         irqpin2: interrupt-controller@e6900008 {
 141                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 142                 #interrupt-cells = <2>;
 143                 interrupt-controller;
 144                 reg = <0xe6900008 4>,
 145                         <0xe6900018 4>,
 146                         <0xe6900028 1>,
 147                         <0xe6900048 1>,
 148                         <0xe6900068 1>;
 149                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 157                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 158                 power-domains = <&pd_a4s>;
 159         };
 160
 161         /* irqpin3: IRQ24 - IRQ31 */
 162         irqpin3: interrupt-controller@e690000c {
 163                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 164                 #interrupt-cells = <2>;
 165                 interrupt-controller;
 166                 reg = <0xe690000c 4>,
 167                         <0xe690001c 4>,
 168                         <0xe690002c 1>,
 169                         <0xe690004c 1>,
 170                         <0xe690006c 1>;
 171                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 180                 power-domains = <&pd_a4s>;
 181         };
 182
 183         ether: ethernet@e9a00000 {
 184                 compatible = "renesas,gether-r8a7740";
 185                 reg = <0xe9a00000 0x800>,
 186                       <0xe9a01800 0x800>;
 187                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
 189                 power-domains = <&pd_a4s>;
 190                 phy-mode = "mii";
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193                 status = "disabled";
 194         };
 195
 196         i2c0: i2c@fff20000 {
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 200                 reg = <0xfff20000 0x425>;
 201                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
 206                 power-domains = <&pd_a4r>;
 207                 status = "disabled";
 208         };
 209
 210         i2c1: i2c@e6c20000 {
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 214                 reg = <0xe6c20000 0x425>;
 215                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
 220                 power-domains = <&pd_a3sp>;
 221                 status = "disabled";
 222         };
 223
 224         scifa0: serial@e6c40000 {
 225                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 226                 reg = <0xe6c40000 0x100>;
 227                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
 229                 clock-names = "fck";
 230                 power-domains = <&pd_a3sp>;
 231                 status = "disabled";
 232         };
 233
 234         scifa1: serial@e6c50000 {
 235                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 236                 reg = <0xe6c50000 0x100>;
 237                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
 239                 clock-names = "fck";
 240                 power-domains = <&pd_a3sp>;
 241                 status = "disabled";
 242         };
 243
 244         scifa2: serial@e6c60000 {
 245                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 246                 reg = <0xe6c60000 0x100>;
 247                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
 249                 clock-names = "fck";
 250                 power-domains = <&pd_a3sp>;
 251                 status = "disabled";
 252         };
 253
 254         scifa3: serial@e6c70000 {
 255                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 256                 reg = <0xe6c70000 0x100>;
 257                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
 259                 clock-names = "fck";
 260                 power-domains = <&pd_a3sp>;
 261                 status = "disabled";
 262         };
 263
 264         scifa4: serial@e6c80000 {
 265                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 266                 reg = <0xe6c80000 0x100>;
 267                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
 269                 clock-names = "fck";
 270                 power-domains = <&pd_a3sp>;
 271                 status = "disabled";
 272         };
 273
 274         scifa5: serial@e6cb0000 {
 275                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 276                 reg = <0xe6cb0000 0x100>;
 277                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
 279                 clock-names = "fck";
 280                 power-domains = <&pd_a3sp>;
 281                 status = "disabled";
 282         };
 283
 284         scifa6: serial@e6cc0000 {
 285                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 286                 reg = <0xe6cc0000 0x100>;
 287                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
 289                 clock-names = "fck";
 290                 power-domains = <&pd_a3sp>;
 291                 status = "disabled";
 292         };
 293
 294         scifa7: serial@e6cd0000 {
 295                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 296                 reg = <0xe6cd0000 0x100>;
 297                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
 299                 clock-names = "fck";
 300                 power-domains = <&pd_a3sp>;
 301                 status = "disabled";
 302         };
 303
 304         scifb: serial@e6c30000 {
 305                 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
 306                 reg = <0xe6c30000 0x100>;
 307                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
 309                 clock-names = "fck";
 310                 power-domains = <&pd_a3sp>;
 311                 status = "disabled";
 312         };
 313
 314         pfc: pin-controller@e6050000 {
 315                 compatible = "renesas,pfc-r8a7740";
 316                 reg = <0xe6050000 0x8000>,
 317                       <0xe605800c 0x20>;
 318                 gpio-controller;
 319                 #gpio-cells = <2>;
 320                 gpio-ranges = <&pfc 0 0 212>;
 321                 interrupts-extended =
 322                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 323                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 324                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 325                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 326                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 327                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 328                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 329                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 330                 power-domains = <&pd_c5>;
 331         };
 332
 333         tpu: pwm@e6600000 {
 334                 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
 335                 reg = <0xe6600000 0x148>;
 336                 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
 337                 power-domains = <&pd_a3sp>;
 338                 status = "disabled";
 339                 #pwm-cells = <3>;
 340         };
 341
 342         mmcif0: mmc@e6bd0000 {
 343                 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
 344                 reg = <0xe6bd0000 0x100>;
 345                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
 348                 power-domains = <&pd_a3sp>;
 349                 status = "disabled";
 350         };
 351
 352         sdhi0: sd@e6850000 {
 353                 compatible = "renesas,sdhi-r8a7740";
 354                 reg = <0xe6850000 0x100>;
 355                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 356                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 357                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
 359                 power-domains = <&pd_a3sp>;
 360                 cap-sd-highspeed;
 361                 cap-sdio-irq;
 362                 status = "disabled";
 363         };
 364
 365         sdhi1: sd@e6860000 {
 366                 compatible = "renesas,sdhi-r8a7740";
 367                 reg = <0xe6860000 0x100>;
 368                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 369                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 370                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
 372                 power-domains = <&pd_a3sp>;
 373                 cap-sd-highspeed;
 374                 cap-sdio-irq;
 375                 status = "disabled";
 376         };
 377
 378         sdhi2: sd@e6870000 {
 379                 compatible = "renesas,sdhi-r8a7740";
 380                 reg = <0xe6870000 0x100>;
 381                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 382                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 383                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
 385                 power-domains = <&pd_a3sp>;
 386                 cap-sd-highspeed;
 387                 cap-sdio-irq;
 388                 status = "disabled";
 389         };
 390
 391         sh_fsi2: sound@fe1f0000 {
 392                 #sound-dai-cells = <1>;
 393                 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
 394                 reg = <0xfe1f0000 0x400>;
 395                 interrupts = <GIC_SPI 9 0x4>;
 396                 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
 397                 power-domains = <&pd_a4mp>;
 398                 status = "disabled";
 399         };
 400
 401         tmu0: timer@fff80000 {
 402                 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 403                 reg = <0xfff80000 0x2c>;
 404                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 405                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 406                              <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
 408                 clock-names = "fck";
 409                 power-domains = <&pd_a4r>;
 410
 411                 #renesas,channels = <3>;
 412
 413                 status = "disabled";
 414         };
 415
 416         tmu1: timer@fff90000 {
 417                 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 418                 reg = <0xfff90000 0x2c>;
 419                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 420                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 421                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
 423                 clock-names = "fck";
 424                 power-domains = <&pd_a4r>;
 425
 426                 #renesas,channels = <3>;
 427
 428                 status = "disabled";
 429         };
 430
 431         clocks {
 432                 #address-cells = <1>;
 433                 #size-cells = <1>;
 434                 ranges;
 435
 436                 /* External root clock */
 437                 extalr_clk: extalr {
 438                         compatible = "fixed-clock";
 439                         #clock-cells = <0>;
 440                         clock-frequency = <32768>;
 441                 };
 442                 extal1_clk: extal1 {
 443                         compatible = "fixed-clock";
 444                         #clock-cells = <0>;
 445                         clock-frequency = <0>;
 446                 };
 447                 extal2_clk: extal2 {
 448                         compatible = "fixed-clock";
 449                         #clock-cells = <0>;
 450                         clock-frequency = <0>;
 451                 };
 452                 dv_clk: dv {
 453                         compatible = "fixed-clock";
 454                         #clock-cells = <0>;
 455                         clock-frequency = <27000000>;
 456                 };
 457                 fmsick_clk: fmsick {
 458                         compatible = "fixed-clock";
 459                         #clock-cells = <0>;
 460                         clock-frequency = <0>;
 461                 };
 462                 fmsock_clk: fmsock {
 463                         compatible = "fixed-clock";
 464                         #clock-cells = <0>;
 465                         clock-frequency = <0>;
 466                 };
 467                 fsiack_clk: fsiack {
 468                         compatible = "fixed-clock";
 469                         #clock-cells = <0>;
 470                         clock-frequency = <0>;
 471                 };
 472                 fsibck_clk: fsibck {
 473                         compatible = "fixed-clock";
 474                         #clock-cells = <0>;
 475                         clock-frequency = <0>;
 476                 };
 477
 478                 /* Special CPG clocks */
 479                 cpg_clocks: cpg_clocks@e6150000 {
 480                         compatible = "renesas,r8a7740-cpg-clocks";
 481                         reg = <0xe6150000 0x10000>;
 482                         clocks = <&extal1_clk>, <&extalr_clk>;
 483                         #clock-cells = <1>;
 484                         clock-output-names = "system", "pllc0", "pllc1",
 485                                              "pllc2", "r",
 486                                              "usb24s",
 487                                              "i", "zg", "b", "m1", "hp",
 488                                              "hpp", "usbp", "s", "zb", "m3",
 489                                              "cp";
 490                 };
 491
 492                 /* Variable factor clocks (DIV6) */
 493                 vclk1_clk: vclk1@e6150008 {
 494                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 495                         reg = <0xe6150008 4>;
 496                         clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
 497                                  <&cpg_clocks R8A7740_CLK_USB24S>,
 498                                  <&extal1_div2_clk>, <&extalr_clk>, <0>,
 499                                  <0>;
 500                         #clock-cells = <0>;
 501                 };
 502                 vclk2_clk: vclk2@e615000c {
 503                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 504                         reg = <0xe615000c 4>;
 505                         clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
 506                                  <&cpg_clocks R8A7740_CLK_USB24S>,
 507                                  <&extal1_div2_clk>, <&extalr_clk>, <0>,
 508                                  <0>;
 509                         #clock-cells = <0>;
 510                 };
 511                 fmsi_clk: fmsi@e6150010 {
 512                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 513                         reg = <0xe6150010 4>;
 514                         clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
 515                         #clock-cells = <0>;
 516                 };
 517                 fmso_clk: fmso@e6150014 {
 518                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 519                         reg = <0xe6150014 4>;
 520                         clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
 521                         #clock-cells = <0>;
 522                 };
 523                 fsia_clk: fsia@e6150018 {
 524                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 525                         reg = <0xe6150018 4>;
 526                         clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
 527                         #clock-cells = <0>;
 528                 };
 529                 sub_clk: sub@e6150080 {
 530                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 531                         reg = <0xe6150080 4>;
 532                         clocks = <&pllc1_div2_clk>,
 533                                  <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 534                         #clock-cells = <0>;
 535                 };
 536                 spu_clk: spu@e6150084 {
 537                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 538                         reg = <0xe6150084 4>;
 539                         clocks = <&pllc1_div2_clk>,
 540                                  <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 541                         #clock-cells = <0>;
 542                 };
 543                 vou_clk: vou@e6150088 {
 544                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 545                         reg = <0xe6150088 4>;
 546                         clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
 547                                  <0>;
 548                         #clock-cells = <0>;
 549                 };
 550                 stpro_clk: stpro@e615009c {
 551                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 552                         reg = <0xe615009c 4>;
 553                         clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
 554                         #clock-cells = <0>;
 555                 };
 556
 557                 /* Fixed factor clocks */
 558                 pllc1_div2_clk: pllc1_div2 {
 559                         compatible = "fixed-factor-clock";
 560                         clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
 561                         #clock-cells = <0>;
 562                         clock-div = <2>;
 563                         clock-mult = <1>;
 564                 };
 565                 extal1_div2_clk: extal1_div2 {
 566                         compatible = "fixed-factor-clock";
 567                         clocks = <&extal1_clk>;
 568                         #clock-cells = <0>;
 569                         clock-div = <2>;
 570                         clock-mult = <1>;
 571                 };
 572
 573                 /* Gate clocks */
 574                 subck_clks: subck_clks@e6150080 {
 575                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 576                         reg = <0xe6150080 4>;
 577                         clocks = <&sub_clk>, <&sub_clk>;
 578                         #clock-cells = <1>;
 579                         clock-indices = <
 580                                 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
 581                         >;
 582                         clock-output-names =
 583                                 "subck", "subck2";
 584                 };
 585                 mstp1_clks: mstp1_clks@e6150134 {
 586                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 587                         reg = <0xe6150134 4>, <0xe6150038 4>;
 588                         clocks = <&cpg_clocks R8A7740_CLK_S>,
 589                                  <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 590                                  <&cpg_clocks R8A7740_CLK_B>,
 591                                  <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
 592                                  <&cpg_clocks R8A7740_CLK_B>;
 593                         #clock-cells = <1>;
 594                         clock-indices = <
 595                                 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
 596                                 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
 597                                 R8A7740_CLK_LCDC0
 598                         >;
 599                         clock-output-names =
 600                                 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
 601                                 "tmu1", "lcdc0";
 602                 };
 603                 mstp2_clks: mstp2_clks@e6150138 {
 604                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 605                         reg = <0xe6150138 4>, <0xe6150040 4>;
 606                         clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
 607                                  <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
 608                                  <&cpg_clocks R8A7740_CLK_HP>,
 609                                  <&cpg_clocks R8A7740_CLK_HP>,
 610                                  <&cpg_clocks R8A7740_CLK_HP>,
 611                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 612                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 613                                  <&sub_clk>;
 614                         #clock-cells = <1>;
 615                         clock-indices = <
 616                                 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
 617                                 R8A7740_CLK_SCIFA7
 618                                 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
 619                                 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
 620                                 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
 621                                 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
 622                                 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
 623                                 R8A7740_CLK_SCIFA4
 624                         >;
 625                         clock-output-names =
 626                                 "scifa6", "intca",
 627                                 "scifa7", "dmac1", "dmac2", "dmac3",
 628                                 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
 629                                 "scifa2", "scifa3", "scifa4";
 630                 };
 631                 mstp3_clks: mstp3_clks@e615013c {
 632                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 633                         reg = <0xe615013c 4>, <0xe6150048 4>;
 634                         clocks = <&cpg_clocks R8A7740_CLK_R>,
 635                                  <&cpg_clocks R8A7740_CLK_HP>,
 636                                  <&sub_clk>,
 637                                  <&cpg_clocks R8A7740_CLK_HP>,
 638                                  <&cpg_clocks R8A7740_CLK_HP>,
 639                                  <&cpg_clocks R8A7740_CLK_HP>,
 640                                  <&cpg_clocks R8A7740_CLK_HP>,
 641                                  <&cpg_clocks R8A7740_CLK_HP>,
 642                                  <&cpg_clocks R8A7740_CLK_HP>;
 643                         #clock-cells = <1>;
 644                         clock-indices = <
 645                                 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
 646                                 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
 647                                 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
 648                         >;
 649                         clock-output-names =
 650                                 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
 651                                 "mmc", "gether", "tpu0";
 652                 };
 653                 mstp4_clks: mstp4_clks@e6150140 {
 654                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 655                         reg = <0xe6150140 4>, <0xe615004c 4>;
 656                         clocks = <&cpg_clocks R8A7740_CLK_HP>,
 657                                  <&cpg_clocks R8A7740_CLK_HP>,
 658                                  <&cpg_clocks R8A7740_CLK_HP>,
 659                                  <&cpg_clocks R8A7740_CLK_HP>;
 660                         #clock-cells = <1>;
 661                         clock-indices = <
 662                                 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
 663                                 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
 664                         >;
 665                         clock-output-names =
 666                                 "usbhost", "sdhi2", "usbfunc", "usphy";
 667                 };
 668         };
 669
 670         sysc: system-controller@e6180000 {
 671                 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
 672                 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
 673
 674                 pm-domains {
 675                         pd_c5: c5 {
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 #power-domain-cells = <0>;
 679
 680                                 pd_a4lc: a4lc@1 {
 681                                         reg = <1>;
 682                                         #power-domain-cells = <0>;
 683                                 };
 684
 685                                 pd_a4mp: a4mp@2 {
 686                                         reg = <2>;
 687                                         #power-domain-cells = <0>;
 688                                 };
 689
 690                                 pd_d4: d4@3 {
 691                                         reg = <3>;
 692                                         #power-domain-cells = <0>;
 693                                 };
 694
 695                                 pd_a4r: a4r@5 {
 696                                         reg = <5>;
 697                                         #address-cells = <1>;
 698                                         #size-cells = <0>;
 699                                         #power-domain-cells = <0>;
 700
 701                                         pd_a3rv: a3rv@6 {
 702                                                 reg = <6>;
 703                                                 #power-domain-cells = <0>;
 704                                         };
 705                                 };
 706
 707                                 pd_a4s: a4s@10 {
 708                                         reg = <10>;
 709                                         #address-cells = <1>;
 710                                         #size-cells = <0>;
 711                                         #power-domain-cells = <0>;
 712
 713                                         pd_a3sp: a3sp@11 {
 714                                                 reg = <11>;
 715                                                 #power-domain-cells = <0>;
 716                                         };
 717
 718                                         pd_a3sm: a3sm@12 {
 719                                                 reg = <12>;
 720                                                 #power-domain-cells = <0>;
 721                                         };
 722
 723                                         pd_a3sg: a3sg@13 {
 724                                                 reg = <13>;
 725                                                 #power-domain-cells = <0>;
 726                                         };
 727                                 };
 728
 729                                 pd_a4su: a4su@20 {
 730                                         reg = <20>;
 731                                         #power-domain-cells = <0>;
 732                                 };
 733                         };
 734                 };
 735         };
 736 };