arch/arm/boot/dts/rk3036.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3036-cru.h>
   8 #include <dt-bindings/soc/rockchip,boot-mode.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         compatible = "rockchip,rk3036";
  15
  16         interrupt-parent = <&gic>;
  17
  18         aliases {
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 mshc0 = &emmc;
  23                 mshc1 = &sdmmc;
  24                 mshc2 = &sdio;
  25                 serial0 = &uart0;
  26                 serial1 = &uart1;
  27                 serial2 = &uart2;
  28                 spi = &spi;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 enable-method = "rockchip,rk3036-smp";
  35
  36                 cpu0: cpu@f00 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a7";
  39                         reg = <0xf00>;
  40                         resets = <&cru SRST_CORE0>;
  41                         operating-points = <
  42                                 /* KHz    uV */
  43                                  816000 1000000
  44                         >;
  45                         clock-latency = <40000>;
  46                         clocks = <&cru ARMCLK>;
  47                 };
  48
  49                 cpu1: cpu@f01 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a7";
  52                         reg = <0xf01>;
  53                         resets = <&cru SRST_CORE1>;
  54                 };
  55         };
  56
  57         amba: bus {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 pdma: pdma@20078000 {
  64                         compatible = "arm,pl330", "arm,primecell";
  65                         reg = <0x20078000 0x4000>;
  66                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  67                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  68                         #dma-cells = <1>;
  69                         arm,pl330-broken-no-flushp;
  70                         clocks = <&cru ACLK_DMAC2>;
  71                         clock-names = "apb_pclk";
  72                 };
  73         };
  74
  75         arm-pmu {
  76                 compatible = "arm,cortex-a7-pmu";
  77                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  79                 interrupt-affinity = <&cpu0>, <&cpu1>;
  80         };
  81
  82         display-subsystem {
  83                 compatible = "rockchip,display-subsystem";
  84                 ports = <&vop_out>;
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 arm,cpu-registers-not-fw-configured;
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  91                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  93                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  94                 clock-frequency = <24000000>;
  95         };
  96
  97         xin24m: oscillator {
  98                 compatible = "fixed-clock";
  99                 clock-frequency = <24000000>;
 100                 clock-output-names = "xin24m";
 101                 #clock-cells = <0>;
 102         };
 103
 104         bus_intmem: sram@10080000 {
 105                 compatible = "mmio-sram";
 106                 reg = <0x10080000 0x2000>;
 107                 #address-cells = <1>;
 108                 #size-cells = <1>;
 109                 ranges = <0 0x10080000 0x2000>;
 110
 111                 smp-sram@0 {
 112                         compatible = "rockchip,rk3066-smp-sram";
 113                         reg = <0x00 0x10>;
 114                 };
 115         };
 116
 117         gpu: gpu@10090000 {
 118                 compatible = "rockchip,rk3036-mali", "arm,mali-400";
 119                 reg = <0x10090000 0x10000>;
 120                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 123                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 124                 interrupt-names = "gp",
 125                                   "gpmmu",
 126                                   "pp0",
 127                                   "ppmmu0";
 128                 assigned-clocks = <&cru SCLK_GPU>;
 129                 assigned-clock-rates = <100000000>;
 130                 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
 131                 clock-names = "core", "bus";
 132                 resets = <&cru SRST_GPU>;
 133                 status = "disabled";
 134         };
 135
 136         vop: vop@10118000 {
 137                 compatible = "rockchip,rk3036-vop";
 138                 reg = <0x10118000 0x19c>;
 139                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 140                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 141                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 142                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 143                 reset-names = "axi", "ahb", "dclk";
 144                 iommus = <&vop_mmu>;
 145                 status = "disabled";
 146
 147                 vop_out: port {
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                         vop_out_hdmi: endpoint@0 {
 151                                 reg = <0>;
 152                                 remote-endpoint = <&hdmi_in_vop>;
 153                         };
 154                 };
 155         };
 156
 157         vop_mmu: iommu@10118300 {
 158                 compatible = "rockchip,iommu";
 159                 reg = <0x10118300 0x100>;
 160                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 161                 interrupt-names = "vop_mmu";
 162                 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
 163                 clock-names = "aclk", "iface";
 164                 #iommu-cells = <0>;
 165                 status = "disabled";
 166         };
 167
 168         gic: interrupt-controller@10139000 {
 169                 compatible = "arm,gic-400";
 170                 interrupt-controller;
 171                 #interrupt-cells = <3>;
 172                 #address-cells = <0>;
 173
 174                 reg = <0x10139000 0x1000>,
 175                       <0x1013a000 0x2000>,
 176                       <0x1013c000 0x2000>,
 177                       <0x1013e000 0x2000>;
 178                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 179         };
 180
 181         usb_otg: usb@10180000 {
 182                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 183                                 "snps,dwc2";
 184                 reg = <0x10180000 0x40000>;
 185                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&cru HCLK_OTG0>;
 187                 clock-names = "otg";
 188                 dr_mode = "otg";
 189                 g-np-tx-fifo-size = <16>;
 190                 g-rx-fifo-size = <275>;
 191                 g-tx-fifo-size = <256 128 128 64 64 32>;
 192                 status = "disabled";
 193         };
 194
 195         usb_host: usb@101c0000 {
 196                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 197                                 "snps,dwc2";
 198                 reg = <0x101c0000 0x40000>;
 199                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru HCLK_OTG1>;
 201                 clock-names = "otg";
 202                 dr_mode = "host";
 203                 status = "disabled";
 204         };
 205
 206         emac: ethernet@10200000 {
 207                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 208                 reg = <0x10200000 0x4000>;
 209                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 rockchip,grf = <&grf>;
 213                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 214                 clock-names = "hclk", "macref", "macclk";
 215                 /*
 216                  * Fix the emac parent clock is DPLL instead of APLL.
 217                  * since that will cause some unstable things if the cpufreq
 218                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 219                  */
 220                 assigned-clocks = <&cru SCLK_MACPLL>;
 221                 assigned-clock-parents = <&cru PLL_DPLL>;
 222                 max-speed = <100>;
 223                 phy-mode = "rmii";
 224                 status = "disabled";
 225         };
 226
 227         sdmmc: mmc@10214000 {
 228                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 229                 reg = <0x10214000 0x4000>;
 230                 clock-frequency = <37500000>;
 231                 max-frequency = <37500000>;
 232                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 233                 clock-names = "biu", "ciu";
 234                 fifo-depth = <0x100>;
 235                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 236                 resets = <&cru SRST_MMC0>;
 237                 reset-names = "reset";
 238                 status = "disabled";
 239         };
 240
 241         sdio: mmc@10218000 {
 242                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 243                 reg = <0x10218000 0x4000>;
 244                 max-frequency = <37500000>;
 245                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 246                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 250                 resets = <&cru SRST_SDIO>;
 251                 reset-names = "reset";
 252                 status = "disabled";
 253         };
 254
 255         emmc: mmc@1021c000 {
 256                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 257                 reg = <0x1021c000 0x4000>;
 258                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 259                 bus-width = <8>;
 260                 cap-mmc-highspeed;
 261                 clock-frequency = <37500000>;
 262                 max-frequency = <37500000>;
 263                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 264                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 265                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 266                 rockchip,default-sample-phase = <158>;
 267                 disable-wp;
 268                 dmas = <&pdma 12>;
 269                 dma-names = "rx-tx";
 270                 fifo-depth = <0x100>;
 271                 mmc-ddr-1_8v;
 272                 non-removable;
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 275                 resets = <&cru SRST_EMMC>;
 276                 reset-names = "reset";
 277                 status = "disabled";
 278         };
 279
 280         i2s: i2s@10220000 {
 281                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 282                 reg = <0x10220000 0x4000>;
 283                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 284                 clock-names = "i2s_clk", "i2s_hclk";
 285                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 286                 dmas = <&pdma 0>, <&pdma 1>;
 287                 dma-names = "tx", "rx";
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&i2s_bus>;
 290                 #sound-dai-cells = <0>;
 291                 status = "disabled";
 292         };
 293
 294         cru: clock-controller@20000000 {
 295                 compatible = "rockchip,rk3036-cru";
 296                 reg = <0x20000000 0x1000>;
 297                 rockchip,grf = <&grf>;
 298                 #clock-cells = <1>;
 299                 #reset-cells = <1>;
 300                 assigned-clocks = <&cru PLL_GPLL>;
 301                 assigned-clock-rates = <594000000>;
 302         };
 303
 304         grf: syscon@20008000 {
 305                 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 306                 reg = <0x20008000 0x1000>;
 307
 308                 reboot-mode {
 309                         compatible = "syscon-reboot-mode";
 310                         offset = <0x1d8>;
 311                         mode-normal = <BOOT_NORMAL>;
 312                         mode-recovery = <BOOT_RECOVERY>;
 313                         mode-bootloader = <BOOT_FASTBOOT>;
 314                         mode-loader = <BOOT_BL_DOWNLOAD>;
 315                 };
 316         };
 317
 318         acodec: acodec-ana@20030000 {
 319                 compatible = "rk3036-codec";
 320                 reg = <0x20030000 0x4000>;
 321                 rockchip,grf = <&grf>;
 322                 clock-names = "acodec_pclk";
 323                 clocks = <&cru PCLK_ACODEC>;
 324                 status = "disabled";
 325         };
 326
 327         hdmi: hdmi@20034000 {
 328                 compatible = "rockchip,rk3036-inno-hdmi";
 329                 reg = <0x20034000 0x4000>;
 330                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&cru  PCLK_HDMI>;
 332                 clock-names = "pclk";
 333                 rockchip,grf = <&grf>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&hdmi_ctl>;
 336                 status = "disabled";
 337
 338                 hdmi_in: port {
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         hdmi_in_vop: endpoint@0 {
 342                                 reg = <0>;
 343                                 remote-endpoint = <&vop_out_hdmi>;
 344                         };
 345                 };
 346         };
 347
 348         timer: timer@20044000 {
 349                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 350                 reg = <0x20044000 0x20>;
 351                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 353                 clock-names = "timer", "pclk";
 354         };
 355
 356         pwm0: pwm@20050000 {
 357                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 358                 reg = <0x20050000 0x10>;
 359                 #pwm-cells = <3>;
 360                 clocks = <&cru PCLK_PWM>;
 361                 clock-names = "pwm";
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&pwm0_pin>;
 364                 status = "disabled";
 365         };
 366
 367         pwm1: pwm@20050010 {
 368                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 369                 reg = <0x20050010 0x10>;
 370                 #pwm-cells = <3>;
 371                 clocks = <&cru PCLK_PWM>;
 372                 clock-names = "pwm";
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&pwm1_pin>;
 375                 status = "disabled";
 376         };
 377
 378         pwm2: pwm@20050020 {
 379                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 380                 reg = <0x20050020 0x10>;
 381                 #pwm-cells = <3>;
 382                 clocks = <&cru PCLK_PWM>;
 383                 clock-names = "pwm";
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&pwm2_pin>;
 386                 status = "disabled";
 387         };
 388
 389         pwm3: pwm@20050030 {
 390                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 391                 reg = <0x20050030 0x10>;
 392                 #pwm-cells = <2>;
 393                 clocks = <&cru PCLK_PWM>;
 394                 clock-names = "pwm";
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pwm3_pin>;
 397                 status = "disabled";
 398         };
 399
 400         i2c1: i2c@20056000 {
 401                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 402                 reg = <0x20056000 0x1000>;
 403                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clock-names = "i2c";
 407                 clocks = <&cru PCLK_I2C1>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&i2c1_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         i2c2: i2c@2005a000 {
 414                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 415                 reg = <0x2005a000 0x1000>;
 416                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clock-names = "i2c";
 420                 clocks = <&cru PCLK_I2C2>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&i2c2_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         uart0: serial@20060000 {
 427                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 428                 reg = <0x20060000 0x100>;
 429                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 430                 reg-shift = <2>;
 431                 reg-io-width = <4>;
 432                 clock-frequency = <24000000>;
 433                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 437                 status = "disabled";
 438         };
 439
 440         uart1: serial@20064000 {
 441                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 442                 reg = <0x20064000 0x100>;
 443                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 444                 reg-shift = <2>;
 445                 reg-io-width = <4>;
 446                 clock-frequency = <24000000>;
 447                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 448                 clock-names = "baudclk", "apb_pclk";
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&uart1_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         uart2: serial@20068000 {
 455                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 456                 reg = <0x20068000 0x100>;
 457                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 clock-frequency = <24000000>;
 461                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 462                 clock-names = "baudclk", "apb_pclk";
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&uart2_xfer>;
 465                 status = "disabled";
 466         };
 467
 468         i2c0: i2c@20072000 {
 469                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 470                 reg = <0x20072000 0x1000>;
 471                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 clock-names = "i2c";
 475                 clocks = <&cru PCLK_I2C0>;
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&i2c0_xfer>;
 478                 status = "disabled";
 479         };
 480
 481         spi: spi@20074000 {
 482                 compatible = "rockchip,rockchip-spi";
 483                 reg = <0x20074000 0x1000>;
 484                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 485                 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
 486                 clock-names = "apb-pclk","spi_pclk";
 487                 dmas = <&pdma 8>, <&pdma 9>;
 488                 dma-names = "tx", "rx";
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 status = "disabled";
 494         };
 495
 496         pinctrl: pinctrl {
 497                 compatible = "rockchip,rk3036-pinctrl";
 498                 rockchip,grf = <&grf>;
 499                 #address-cells = <1>;
 500                 #size-cells = <1>;
 501                 ranges;
 502
 503                 gpio0: gpio0@2007c000 {
 504                         compatible = "rockchip,gpio-bank";
 505                         reg = <0x2007c000 0x100>;
 506                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&cru PCLK_GPIO0>;
 508
 509                         gpio-controller;
 510                         #gpio-cells = <2>;
 511
 512                         interrupt-controller;
 513                         #interrupt-cells = <2>;
 514                 };
 515
 516                 gpio1: gpio1@20080000 {
 517                         compatible = "rockchip,gpio-bank";
 518                         reg = <0x20080000 0x100>;
 519                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&cru PCLK_GPIO1>;
 521
 522                         gpio-controller;
 523                         #gpio-cells = <2>;
 524
 525                         interrupt-controller;
 526                         #interrupt-cells = <2>;
 527                 };
 528
 529                 gpio2: gpio2@20084000 {
 530                         compatible = "rockchip,gpio-bank";
 531                         reg = <0x20084000 0x100>;
 532                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&cru PCLK_GPIO2>;
 534
 535                         gpio-controller;
 536                         #gpio-cells = <2>;
 537
 538                         interrupt-controller;
 539                         #interrupt-cells = <2>;
 540                 };
 541
 542                 pcfg_pull_default: pcfg_pull_default {
 543                         bias-pull-pin-default;
 544                 };
 545
 546                 pcfg_pull_none: pcfg-pull-none {
 547                         bias-disable;
 548                 };
 549
 550                 pwm0 {
 551                         pwm0_pin: pwm0-pin {
 552                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
 553                         };
 554                 };
 555
 556                 pwm1 {
 557                         pwm1_pin: pwm1-pin {
 558                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 559                         };
 560                 };
 561
 562                 pwm2 {
 563                         pwm2_pin: pwm2-pin {
 564                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 565                         };
 566                 };
 567
 568                 pwm3 {
 569                         pwm3_pin: pwm3-pin {
 570                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 571                         };
 572                 };
 573
 574                 sdmmc {
 575                         sdmmc_clk: sdmmc-clk {
 576                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 577                         };
 578
 579                         sdmmc_cmd: sdmmc-cmd {
 580                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
 581                         };
 582
 583                         sdmmc_cd: sdmmc-cd {
 584                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
 585                         };
 586
 587                         sdmmc_bus1: sdmmc-bus1 {
 588                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
 589                         };
 590
 591                         sdmmc_bus4: sdmmc-bus4 {
 592                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
 593                                                 <1 RK_PC3 1 &pcfg_pull_default>,
 594                                                 <1 RK_PC4 1 &pcfg_pull_default>,
 595                                                 <1 RK_PC5 1 &pcfg_pull_default>;
 596                         };
 597                 };
 598
 599                 sdio {
 600                         sdio_bus1: sdio-bus1 {
 601                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
 602                         };
 603
 604                         sdio_bus4: sdio-bus4 {
 605                                 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
 606                                                 <0 RK_PB4 1 &pcfg_pull_default>,
 607                                                 <0 RK_PB5 1 &pcfg_pull_default>,
 608                                                 <0 RK_PB6 1 &pcfg_pull_default>;
 609                         };
 610
 611                         sdio_cmd: sdio-cmd {
 612                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
 613                         };
 614
 615                         sdio_clk: sdio-clk {
 616                                 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
 617                         };
 618                 };
 619
 620                 emmc {
 621                         /*
 622                          * We run eMMC at max speed; bump up drive strength.
 623                          * We also have external pulls, so disable the internal ones.
 624                          */
 625                         emmc_clk: emmc-clk {
 626                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 627                         };
 628
 629                         emmc_cmd: emmc-cmd {
 630                                 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
 631                         };
 632
 633                         emmc_bus8: emmc-bus8 {
 634                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 635                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 636                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 637                                                 <1 RK_PD3 2 &pcfg_pull_default>,
 638                                                 <1 RK_PD4 2 &pcfg_pull_default>,
 639                                                 <1 RK_PD5 2 &pcfg_pull_default>,
 640                                                 <1 RK_PD6 2 &pcfg_pull_default>,
 641                                                 <1 RK_PD7 2 &pcfg_pull_default>;
 642                         };
 643                 };
 644
 645                 emac {
 646                         emac_xfer: emac-xfer {
 647                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
 648                                                 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
 649                                                 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
 650                                                 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
 651                                                 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
 652                                                 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
 653                                                 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
 654                                                 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
 655                         };
 656
 657                         emac_mdio: emac-mdio {
 658                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
 659                                                 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
 660                         };
 661                 };
 662
 663                 i2c0 {
 664                         i2c0_xfer: i2c0-xfer {
 665                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 666                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 667                         };
 668                 };
 669
 670                 i2c1 {
 671                         i2c1_xfer: i2c1-xfer {
 672                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 673                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 674                         };
 675                 };
 676
 677                 i2c2 {
 678                         i2c2_xfer: i2c2-xfer {
 679                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
 680                                                 <2 RK_PC5 1 &pcfg_pull_none>;
 681                         };
 682                 };
 683
 684                 i2s {
 685                         i2s_bus: i2s-bus {
 686                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
 687                                                 <1 RK_PA1 1 &pcfg_pull_default>,
 688                                                 <1 RK_PA2 1 &pcfg_pull_default>,
 689                                                 <1 RK_PA3 1 &pcfg_pull_default>,
 690                                                 <1 RK_PA4 1 &pcfg_pull_default>,
 691                                                 <1 RK_PA5 1 &pcfg_pull_default>;
 692                         };
 693                 };
 694
 695                 hdmi {
 696                         hdmi_ctl: hdmi-ctl {
 697                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
 698                                                 <1 RK_PB1 1 &pcfg_pull_none>,
 699                                                 <1 RK_PB2 1 &pcfg_pull_none>,
 700                                                 <1 RK_PB3 1 &pcfg_pull_none>;
 701                         };
 702                 };
 703
 704                 uart0 {
 705                         uart0_xfer: uart0-xfer {
 706                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
 707                                                 <0 RK_PC1 1 &pcfg_pull_none>;
 708                         };
 709
 710                         uart0_cts: uart0-cts {
 711                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
 712                         };
 713
 714                         uart0_rts: uart0-rts {
 715                                 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
 716                         };
 717                 };
 718
 719                 uart1 {
 720                         uart1_xfer: uart1-xfer {
 721                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
 722                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 723                         };
 724                         /* no rts / cts for uart1 */
 725                 };
 726
 727                 uart2 {
 728                         uart2_xfer: uart2-xfer {
 729                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
 730                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 731                         };
 732                         /* no rts / cts for uart2 */
 733                 };
 734
 735                 spi-pins {
 736                         spi_txd:spi-txd {
 737                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
 738                         };
 739
 740                         spi_rxd:spi-rxd {
 741                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
 742                         };
 743
 744                         spi_clk:spi-clk {
 745                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
 746                         };
 747
 748                         spi_cs0:spi-cs0 {
 749                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
 750
 751                         };
 752
 753                         spi_cs1:spi-cs1 {
 754                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
 755
 756                         };
 757                 };
 758         };
 759 };