arch/arm/boot/dts/rk322x.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3228-cru.h>
   8 #include <dt-bindings/thermal/thermal.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 spi0 = &spi0;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@f00 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0xf00>;
  31                         resets = <&cru SRST_CORE0>;
  32                         operating-points-v2 = <&cpu0_opp_table>;
  33                         #cooling-cells = <2>; /* min followed by max */
  34                         clock-latency = <40000>;
  35                         clocks = <&cru ARMCLK>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 cpu1: cpu@f01 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a7";
  42                         reg = <0xf01>;
  43                         resets = <&cru SRST_CORE1>;
  44                         operating-points-v2 = <&cpu0_opp_table>;
  45                         #cooling-cells = <2>; /* min followed by max */
  46                         enable-method = "psci";
  47                 };
  48
  49                 cpu2: cpu@f02 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a7";
  52                         reg = <0xf02>;
  53                         resets = <&cru SRST_CORE2>;
  54                         operating-points-v2 = <&cpu0_opp_table>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                         enable-method = "psci";
  57                 };
  58
  59                 cpu3: cpu@f03 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a7";
  62                         reg = <0xf03>;
  63                         resets = <&cru SRST_CORE3>;
  64                         operating-points-v2 = <&cpu0_opp_table>;
  65                         #cooling-cells = <2>; /* min followed by max */
  66                         enable-method = "psci";
  67                 };
  68         };
  69
  70         cpu0_opp_table: opp_table0 {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73
  74                 opp-408000000 {
  75                         opp-hz = /bits/ 64 <408000000>;
  76                         opp-microvolt = <950000>;
  77                         clock-latency-ns = <40000>;
  78                         opp-suspend;
  79                 };
  80                 opp-600000000 {
  81                         opp-hz = /bits/ 64 <600000000>;
  82                         opp-microvolt = <975000>;
  83                 };
  84                 opp-816000000 {
  85                         opp-hz = /bits/ 64 <816000000>;
  86                         opp-microvolt = <1000000>;
  87                 };
  88                 opp-1008000000 {
  89                         opp-hz = /bits/ 64 <1008000000>;
  90                         opp-microvolt = <1175000>;
  91                 };
  92                 opp-1200000000 {
  93                         opp-hz = /bits/ 64 <1200000000>;
  94                         opp-microvolt = <1275000>;
  95                 };
  96         };
  97
  98         amba: bus {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 pdma: pdma@110f0000 {
 105                         compatible = "arm,pl330", "arm,primecell";
 106                         reg = <0x110f0000 0x4000>;
 107                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 108                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 109                         #dma-cells = <1>;
 110                         clocks = <&cru ACLK_DMAC>;
 111                         clock-names = "apb_pclk";
 112                 };
 113         };
 114
 115         arm-pmu {
 116                 compatible = "arm,cortex-a7-pmu";
 117                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 119                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 121                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 122         };
 123
 124         psci {
 125                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 126                 method = "smc";
 127         };
 128
 129         timer {
 130                 compatible = "arm,armv7-timer";
 131                 arm,cpu-registers-not-fw-configured;
 132                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 133                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 134                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 135                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 136                 clock-frequency = <24000000>;
 137         };
 138
 139         xin24m: oscillator {
 140                 compatible = "fixed-clock";
 141                 clock-frequency = <24000000>;
 142                 clock-output-names = "xin24m";
 143                 #clock-cells = <0>;
 144         };
 145
 146         display_subsystem: display-subsystem {
 147                 compatible = "rockchip,display-subsystem";
 148                 ports = <&vop_out>;
 149         };
 150
 151         i2s1: i2s1@100b0000 {
 152                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 153                 reg = <0x100b0000 0x4000>;
 154                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 155                 clock-names = "i2s_clk", "i2s_hclk";
 156                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 157                 dmas = <&pdma 14>, <&pdma 15>;
 158                 dma-names = "tx", "rx";
 159                 pinctrl-names = "default";
 160                 pinctrl-0 = <&i2s1_bus>;
 161                 status = "disabled";
 162         };
 163
 164         i2s0: i2s0@100c0000 {
 165                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 166                 reg = <0x100c0000 0x4000>;
 167                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 168                 clock-names = "i2s_clk", "i2s_hclk";
 169                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 170                 dmas = <&pdma 11>, <&pdma 12>;
 171                 dma-names = "tx", "rx";
 172                 status = "disabled";
 173         };
 174
 175         spdif: spdif@100d0000 {
 176                 compatible = "rockchip,rk3228-spdif";
 177                 reg = <0x100d0000 0x1000>;
 178                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 180                 clock-names = "mclk", "hclk";
 181                 dmas = <&pdma 10>;
 182                 dma-names = "tx";
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&spdif_tx>;
 185                 status = "disabled";
 186         };
 187
 188         i2s2: i2s2@100e0000 {
 189                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 190                 reg = <0x100e0000 0x4000>;
 191                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 192                 clock-names = "i2s_clk", "i2s_hclk";
 193                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 194                 dmas = <&pdma 0>, <&pdma 1>;
 195                 dma-names = "tx", "rx";
 196                 status = "disabled";
 197         };
 198
 199         grf: syscon@11000000 {
 200                 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
 201                 reg = <0x11000000 0x1000>;
 202                 #address-cells = <1>;
 203                 #size-cells = <1>;
 204
 205                 io_domains: io-domains {
 206                         compatible = "rockchip,rk3228-io-voltage-domain";
 207                         status = "disabled";
 208                 };
 209
 210                 u2phy0: usb2-phy@760 {
 211                         compatible = "rockchip,rk3228-usb2phy";
 212                         reg = <0x0760 0x0c>;
 213                         clocks = <&cru SCLK_OTGPHY0>;
 214                         clock-names = "phyclk";
 215                         clock-output-names = "usb480m_phy0";
 216                         #clock-cells = <0>;
 217                         status = "disabled";
 218
 219                         u2phy0_otg: otg-port {
 220                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 221                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 222                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 223                                 interrupt-names = "otg-bvalid", "otg-id",
 224                                                   "linestate";
 225                                 #phy-cells = <0>;
 226                                 status = "disabled";
 227                         };
 228
 229                         u2phy0_host: host-port {
 230                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 231                                 interrupt-names = "linestate";
 232                                 #phy-cells = <0>;
 233                                 status = "disabled";
 234                         };
 235                 };
 236
 237                 u2phy1: usb2-phy@800 {
 238                         compatible = "rockchip,rk3228-usb2phy";
 239                         reg = <0x0800 0x0c>;
 240                         clocks = <&cru SCLK_OTGPHY1>;
 241                         clock-names = "phyclk";
 242                         clock-output-names = "usb480m_phy1";
 243                         #clock-cells = <0>;
 244                         status = "disabled";
 245
 246                         u2phy1_otg: otg-port {
 247                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 248                                 interrupt-names = "linestate";
 249                                 #phy-cells = <0>;
 250                                 status = "disabled";
 251                         };
 252
 253                         u2phy1_host: host-port {
 254                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 255                                 interrupt-names = "linestate";
 256                                 #phy-cells = <0>;
 257                                 status = "disabled";
 258                         };
 259                 };
 260         };
 261
 262         uart0: serial@11010000 {
 263                 compatible = "snps,dw-apb-uart";
 264                 reg = <0x11010000 0x100>;
 265                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 266                 clock-frequency = <24000000>;
 267                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 268                 clock-names = "baudclk", "apb_pclk";
 269                 pinctrl-names = "default";
 270                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 271                 reg-shift = <2>;
 272                 reg-io-width = <4>;
 273                 status = "disabled";
 274         };
 275
 276         uart1: serial@11020000 {
 277                 compatible = "snps,dw-apb-uart";
 278                 reg = <0x11020000 0x100>;
 279                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 280                 clock-frequency = <24000000>;
 281                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 282                 clock-names = "baudclk", "apb_pclk";
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&uart1_xfer>;
 285                 reg-shift = <2>;
 286                 reg-io-width = <4>;
 287                 status = "disabled";
 288         };
 289
 290         uart2: serial@11030000 {
 291                 compatible = "snps,dw-apb-uart";
 292                 reg = <0x11030000 0x100>;
 293                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 294                 clock-frequency = <24000000>;
 295                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 296                 clock-names = "baudclk", "apb_pclk";
 297                 pinctrl-names = "default";
 298                 pinctrl-0 = <&uart2_xfer>;
 299                 reg-shift = <2>;
 300                 reg-io-width = <4>;
 301                 status = "disabled";
 302         };
 303
 304         efuse: efuse@11040000 {
 305                 compatible = "rockchip,rk3228-efuse";
 306                 reg = <0x11040000 0x20>;
 307                 clocks = <&cru PCLK_EFUSE_256>;
 308                 clock-names = "pclk_efuse";
 309                 #address-cells = <1>;
 310                 #size-cells = <1>;
 311
 312                 /* Data cells */
 313                 efuse_id: id@7 {
 314                         reg = <0x7 0x10>;
 315                 };
 316                 cpu_leakage: cpu_leakage@17 {
 317                         reg = <0x17 0x1>;
 318                 };
 319         };
 320
 321         i2c0: i2c@11050000 {
 322                 compatible = "rockchip,rk3228-i2c";
 323                 reg = <0x11050000 0x1000>;
 324                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 clock-names = "i2c";
 328                 clocks = <&cru PCLK_I2C0>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&i2c0_xfer>;
 331                 status = "disabled";
 332         };
 333
 334         i2c1: i2c@11060000 {
 335                 compatible = "rockchip,rk3228-i2c";
 336                 reg = <0x11060000 0x1000>;
 337                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clock-names = "i2c";
 341                 clocks = <&cru PCLK_I2C1>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&i2c1_xfer>;
 344                 status = "disabled";
 345         };
 346
 347         i2c2: i2c@11070000 {
 348                 compatible = "rockchip,rk3228-i2c";
 349                 reg = <0x11070000 0x1000>;
 350                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 clock-names = "i2c";
 354                 clocks = <&cru PCLK_I2C2>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&i2c2_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         i2c3: i2c@11080000 {
 361                 compatible = "rockchip,rk3228-i2c";
 362                 reg = <0x11080000 0x1000>;
 363                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clock-names = "i2c";
 367                 clocks = <&cru PCLK_I2C3>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&i2c3_xfer>;
 370                 status = "disabled";
 371         };
 372
 373         spi0: spi@11090000 {
 374                 compatible = "rockchip,rk3228-spi";
 375                 reg = <0x11090000 0x1000>;
 376                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 380                 clock-names = "spiclk", "apb_pclk";
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 383                 status = "disabled";
 384         };
 385
 386         wdt: watchdog@110a0000 {
 387                 compatible = "snps,dw-wdt";
 388                 reg = <0x110a0000 0x100>;
 389                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&cru PCLK_CPU>;
 391                 status = "disabled";
 392         };
 393
 394         pwm0: pwm@110b0000 {
 395                 compatible = "rockchip,rk3288-pwm";
 396                 reg = <0x110b0000 0x10>;
 397                 #pwm-cells = <3>;
 398                 clocks = <&cru PCLK_PWM>;
 399                 clock-names = "pwm";
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&pwm0_pin>;
 402                 status = "disabled";
 403         };
 404
 405         pwm1: pwm@110b0010 {
 406                 compatible = "rockchip,rk3288-pwm";
 407                 reg = <0x110b0010 0x10>;
 408                 #pwm-cells = <3>;
 409                 clocks = <&cru PCLK_PWM>;
 410                 clock-names = "pwm";
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&pwm1_pin>;
 413                 status = "disabled";
 414         };
 415
 416         pwm2: pwm@110b0020 {
 417                 compatible = "rockchip,rk3288-pwm";
 418                 reg = <0x110b0020 0x10>;
 419                 #pwm-cells = <3>;
 420                 clocks = <&cru PCLK_PWM>;
 421                 clock-names = "pwm";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&pwm2_pin>;
 424                 status = "disabled";
 425         };
 426
 427         pwm3: pwm@110b0030 {
 428                 compatible = "rockchip,rk3288-pwm";
 429                 reg = <0x110b0030 0x10>;
 430                 #pwm-cells = <2>;
 431                 clocks = <&cru PCLK_PWM>;
 432                 clock-names = "pwm";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&pwm3_pin>;
 435                 status = "disabled";
 436         };
 437
 438         timer: timer@110c0000 {
 439                 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
 440                 reg = <0x110c0000 0x20>;
 441                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 443                 clock-names = "timer", "pclk";
 444         };
 445
 446         cru: clock-controller@110e0000 {
 447                 compatible = "rockchip,rk3228-cru";
 448                 reg = <0x110e0000 0x1000>;
 449                 rockchip,grf = <&grf>;
 450                 #clock-cells = <1>;
 451                 #reset-cells = <1>;
 452                 assigned-clocks =
 453                         <&cru PLL_GPLL>, <&cru ARMCLK>,
 454                         <&cru PLL_CPLL>, <&cru ACLK_PERI>,
 455                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 456                         <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 457                         <&cru PCLK_CPU>;
 458                 assigned-clock-rates =
 459                         <594000000>, <816000000>,
 460                         <500000000>, <150000000>,
 461                         <150000000>, <75000000>,
 462                         <150000000>, <150000000>,
 463                         <75000000>;
 464         };
 465
 466         thermal-zones {
 467                 cpu_thermal: cpu-thermal {
 468                         polling-delay-passive = <100>; /* milliseconds */
 469                         polling-delay = <5000>; /* milliseconds */
 470
 471                         thermal-sensors = <&tsadc 0>;
 472
 473                         trips {
 474                                 cpu_alert0: cpu_alert0 {
 475                                         temperature = <70000>; /* millicelsius */
 476                                         hysteresis = <2000>; /* millicelsius */
 477                                         type = "passive";
 478                                 };
 479                                 cpu_alert1: cpu_alert1 {
 480                                         temperature = <75000>; /* millicelsius */
 481                                         hysteresis = <2000>; /* millicelsius */
 482                                         type = "passive";
 483                                 };
 484                                 cpu_crit: cpu_crit {
 485                                         temperature = <90000>; /* millicelsius */
 486                                         hysteresis = <2000>; /* millicelsius */
 487                                         type = "critical";
 488                                 };
 489                         };
 490
 491                         cooling-maps {
 492                                 map0 {
 493                                         trip = <&cpu_alert0>;
 494                                         cooling-device =
 495                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 496                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 497                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 498                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 499                                 };
 500                                 map1 {
 501                                         trip = <&cpu_alert1>;
 502                                         cooling-device =
 503                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 504                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 505                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 506                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 507                                 };
 508                         };
 509                 };
 510         };
 511
 512         tsadc: tsadc@11150000 {
 513                 compatible = "rockchip,rk3228-tsadc";
 514                 reg = <0x11150000 0x100>;
 515                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 517                 clock-names = "tsadc", "apb_pclk";
 518                 assigned-clocks = <&cru SCLK_TSADC>;
 519                 assigned-clock-rates = <32768>;
 520                 resets = <&cru SRST_TSADC>;
 521                 reset-names = "tsadc-apb";
 522                 pinctrl-names = "init", "default", "sleep";
 523                 pinctrl-0 = <&otp_gpio>;
 524                 pinctrl-1 = <&otp_out>;
 525                 pinctrl-2 = <&otp_gpio>;
 526                 #thermal-sensor-cells = <0>;
 527                 rockchip,hw-tshut-temp = <95000>;
 528                 status = "disabled";
 529         };
 530
 531         hdmi_phy: hdmi-phy@12030000 {
 532                 compatible = "rockchip,rk3228-hdmi-phy";
 533                 reg = <0x12030000 0x10000>;
 534                 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
 535                 clock-names = "sysclk", "refoclk", "refpclk";
 536                 #clock-cells = <0>;
 537                 clock-output-names = "hdmiphy_phy";
 538                 #phy-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         gpu: gpu@20000000 {
 543                 compatible = "rockchip,rk3228-mali", "arm,mali-400";
 544                 reg = <0x20000000 0x10000>;
 545                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 546                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 547                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 548                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 549                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 550                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 551                 interrupt-names = "gp",
 552                                   "gpmmu",
 553                                   "pp0",
 554                                   "ppmmu0",
 555                                   "pp1",
 556                                   "ppmmu1";
 557                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 558                 clock-names = "bus", "core";
 559                 resets = <&cru SRST_GPU_A>;
 560                 status = "disabled";
 561         };
 562
 563         vpu_mmu: iommu@20020800 {
 564                 compatible = "rockchip,iommu";
 565                 reg = <0x20020800 0x100>;
 566                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 567                 interrupt-names = "vpu_mmu";
 568                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 569                 clock-names = "aclk", "iface";
 570                 iommu-cells = <0>;
 571                 status = "disabled";
 572         };
 573
 574         vdec_mmu: iommu@20030480 {
 575                 compatible = "rockchip,iommu";
 576                 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
 577                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 578                 interrupt-names = "vdec_mmu";
 579                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 580                 clock-names = "aclk", "iface";
 581                 iommu-cells = <0>;
 582                 status = "disabled";
 583         };
 584
 585         vop: vop@20050000 {
 586                 compatible = "rockchip,rk3228-vop";
 587                 reg = <0x20050000 0x1ffc>;
 588                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 589                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 590                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 591                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 592                 reset-names = "axi", "ahb", "dclk";
 593                 iommus = <&vop_mmu>;
 594                 status = "disabled";
 595
 596                 vop_out: port {
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599
 600                         vop_out_hdmi: endpoint@0 {
 601                                 reg = <0>;
 602                                 remote-endpoint = <&hdmi_in_vop>;
 603                         };
 604                 };
 605         };
 606
 607         vop_mmu: iommu@20053f00 {
 608                 compatible = "rockchip,iommu";
 609                 reg = <0x20053f00 0x100>;
 610                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 611                 interrupt-names = "vop_mmu";
 612                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 613                 clock-names = "aclk", "iface";
 614                 #iommu-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         iep_mmu: iommu@20070800 {
 619                 compatible = "rockchip,iommu";
 620                 reg = <0x20070800 0x100>;
 621                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 622                 interrupt-names = "iep_mmu";
 623                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 624                 clock-names = "aclk", "iface";
 625                 iommu-cells = <0>;
 626                 status = "disabled";
 627         };
 628
 629         hdmi: hdmi@200a0000 {
 630                 compatible = "rockchip,rk3228-dw-hdmi";
 631                 reg = <0x200a0000 0x20000>;
 632                 reg-io-width = <4>;
 633                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 634                 assigned-clocks = <&cru SCLK_HDMI_PHY>;
 635                 assigned-clock-parents = <&hdmi_phy>;
 636                 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
 637                 clock-names = "isfr", "iahb", "cec";
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
 640                 resets = <&cru SRST_HDMI_P>;
 641                 reset-names = "hdmi";
 642                 phys = <&hdmi_phy>;
 643                 phy-names = "hdmi";
 644                 rockchip,grf = <&grf>;
 645                 status = "disabled";
 646
 647                 ports {
 648                         hdmi_in: port {
 649                                 #address-cells = <1>;
 650                                 #size-cells = <0>;
 651                                 hdmi_in_vop: endpoint@0 {
 652                                         reg = <0>;
 653                                         remote-endpoint = <&vop_out_hdmi>;
 654                                 };
 655                         };
 656                 };
 657         };
 658
 659         sdmmc: mmc@30000000 {
 660                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 661                 reg = <0x30000000 0x4000>;
 662                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 663                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 664                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 665                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 666                 fifo-depth = <0x100>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
 669                 status = "disabled";
 670         };
 671
 672         sdio: mmc@30010000 {
 673                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 674                 reg = <0x30010000 0x4000>;
 675                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 676                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 677                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 678                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 679                 fifo-depth = <0x100>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
 682                 status = "disabled";
 683         };
 684
 685         emmc: mmc@30020000 {
 686                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 687                 reg = <0x30020000 0x4000>;
 688                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 689                 clock-frequency = <37500000>;
 690                 max-frequency = <37500000>;
 691                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 692                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 693                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 694                 bus-width = <8>;
 695                 rockchip,default-sample-phase = <158>;
 696                 fifo-depth = <0x100>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 699                 resets = <&cru SRST_EMMC>;
 700                 reset-names = "reset";
 701                 status = "disabled";
 702         };
 703
 704         usb_otg: usb@30040000 {
 705                 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
 706                              "snps,dwc2";
 707                 reg = <0x30040000 0x40000>;
 708                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&cru HCLK_OTG>;
 710                 clock-names = "otg";
 711                 dr_mode = "otg";
 712                 g-np-tx-fifo-size = <16>;
 713                 g-rx-fifo-size = <280>;
 714                 g-tx-fifo-size = <256 128 128 64 32 16>;
 715                 phys = <&u2phy0_otg>;
 716                 phy-names = "usb2-phy";
 717                 status = "disabled";
 718         };
 719
 720         usb_host0_ehci: usb@30080000 {
 721                 compatible = "generic-ehci";
 722                 reg = <0x30080000 0x20000>;
 723                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 725                 phys = <&u2phy0_host>;
 726                 phy-names = "usb";
 727                 status = "disabled";
 728         };
 729
 730         usb_host0_ohci: usb@300a0000 {
 731                 compatible = "generic-ohci";
 732                 reg = <0x300a0000 0x20000>;
 733                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 734                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 735                 phys = <&u2phy0_host>;
 736                 phy-names = "usb";
 737                 status = "disabled";
 738         };
 739
 740         usb_host1_ehci: usb@300c0000 {
 741                 compatible = "generic-ehci";
 742                 reg = <0x300c0000 0x20000>;
 743                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 744                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 745                 phys = <&u2phy1_otg>;
 746                 phy-names = "usb";
 747                 status = "disabled";
 748         };
 749
 750         usb_host1_ohci: usb@300e0000 {
 751                 compatible = "generic-ohci";
 752                 reg = <0x300e0000 0x20000>;
 753                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 755                 phys = <&u2phy1_otg>;
 756                 phy-names = "usb";
 757                 status = "disabled";
 758         };
 759
 760         usb_host2_ehci: usb@30100000 {
 761                 compatible = "generic-ehci";
 762                 reg = <0x30100000 0x20000>;
 763                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 764                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 765                 phys = <&u2phy1_host>;
 766                 phy-names = "usb";
 767                 status = "disabled";
 768         };
 769
 770         usb_host2_ohci: usb@30120000 {
 771                 compatible = "generic-ohci";
 772                 reg = <0x30120000 0x20000>;
 773                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 774                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 775                 phys = <&u2phy1_host>;
 776                 phy-names = "usb";
 777                 status = "disabled";
 778         };
 779
 780         gmac: ethernet@30200000 {
 781                 compatible = "rockchip,rk3228-gmac";
 782                 reg = <0x30200000 0x10000>;
 783                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 784                 interrupt-names = "macirq";
 785                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 786                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 787                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 788                         <&cru PCLK_GMAC>;
 789                 clock-names = "stmmaceth", "mac_clk_rx",
 790                         "mac_clk_tx", "clk_mac_ref",
 791                         "clk_mac_refout", "aclk_mac",
 792                         "pclk_mac";
 793                 resets = <&cru SRST_GMAC>;
 794                 reset-names = "stmmaceth";
 795                 rockchip,grf = <&grf>;
 796                 status = "disabled";
 797         };
 798
 799         gic: interrupt-controller@32010000 {
 800                 compatible = "arm,gic-400";
 801                 interrupt-controller;
 802                 #interrupt-cells = <3>;
 803                 #address-cells = <0>;
 804
 805                 reg = <0x32011000 0x1000>,
 806                       <0x32012000 0x2000>,
 807                       <0x32014000 0x2000>,
 808                       <0x32016000 0x2000>;
 809                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 810         };
 811
 812         pinctrl: pinctrl {
 813                 compatible = "rockchip,rk3228-pinctrl";
 814                 rockchip,grf = <&grf>;
 815                 #address-cells = <1>;
 816                 #size-cells = <1>;
 817                 ranges;
 818
 819                 gpio0: gpio0@11110000 {
 820                         compatible = "rockchip,gpio-bank";
 821                         reg = <0x11110000 0x100>;
 822                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 823                         clocks = <&cru PCLK_GPIO0>;
 824
 825                         gpio-controller;
 826                         #gpio-cells = <2>;
 827
 828                         interrupt-controller;
 829                         #interrupt-cells = <2>;
 830                 };
 831
 832                 gpio1: gpio1@11120000 {
 833                         compatible = "rockchip,gpio-bank";
 834                         reg = <0x11120000 0x100>;
 835                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 836                         clocks = <&cru PCLK_GPIO1>;
 837
 838                         gpio-controller;
 839                         #gpio-cells = <2>;
 840
 841                         interrupt-controller;
 842                         #interrupt-cells = <2>;
 843                 };
 844
 845                 gpio2: gpio2@11130000 {
 846                         compatible = "rockchip,gpio-bank";
 847                         reg = <0x11130000 0x100>;
 848                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 849                         clocks = <&cru PCLK_GPIO2>;
 850
 851                         gpio-controller;
 852                         #gpio-cells = <2>;
 853
 854                         interrupt-controller;
 855                         #interrupt-cells = <2>;
 856                 };
 857
 858                 gpio3: gpio3@11140000 {
 859                         compatible = "rockchip,gpio-bank";
 860                         reg = <0x11140000 0x100>;
 861                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 862                         clocks = <&cru PCLK_GPIO3>;
 863
 864                         gpio-controller;
 865                         #gpio-cells = <2>;
 866
 867                         interrupt-controller;
 868                         #interrupt-cells = <2>;
 869                 };
 870
 871                 pcfg_pull_up: pcfg-pull-up {
 872                         bias-pull-up;
 873                 };
 874
 875                 pcfg_pull_down: pcfg-pull-down {
 876                         bias-pull-down;
 877                 };
 878
 879                 pcfg_pull_none: pcfg-pull-none {
 880                         bias-disable;
 881                 };
 882
 883                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 884                         drive-strength = <12>;
 885                 };
 886
 887                 sdmmc {
 888                         sdmmc_clk: sdmmc-clk {
 889                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
 890                         };
 891
 892                         sdmmc_cmd: sdmmc-cmd {
 893                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
 894                         };
 895
 896                         sdmmc_bus4: sdmmc-bus4 {
 897                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
 898                                                 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
 899                                                 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
 900                                                 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
 901                         };
 902                 };
 903
 904                 sdio {
 905                         sdio_clk: sdio-clk {
 906                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
 907                         };
 908
 909                         sdio_cmd: sdio-cmd {
 910                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
 911                         };
 912
 913                         sdio_bus4: sdio-bus4 {
 914                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
 915                                                 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
 916                                                 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
 917                                                 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
 918                         };
 919                 };
 920
 921                 emmc {
 922                         emmc_clk: emmc-clk {
 923                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
 924                         };
 925
 926                         emmc_cmd: emmc-cmd {
 927                                 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
 928                         };
 929
 930                         emmc_bus8: emmc-bus8 {
 931                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
 932                                                 <1 RK_PD1 2 &pcfg_pull_none>,
 933                                                 <1 RK_PD2 2 &pcfg_pull_none>,
 934                                                 <1 RK_PD3 2 &pcfg_pull_none>,
 935                                                 <1 RK_PD4 2 &pcfg_pull_none>,
 936                                                 <1 RK_PD5 2 &pcfg_pull_none>,
 937                                                 <1 RK_PD6 2 &pcfg_pull_none>,
 938                                                 <1 RK_PD7 2 &pcfg_pull_none>;
 939                         };
 940                 };
 941
 942                 gmac {
 943                         rgmii_pins: rgmii-pins {
 944                                 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
 945                                                 <2 RK_PB4 1 &pcfg_pull_none>,
 946                                                 <2 RK_PD1 1 &pcfg_pull_none>,
 947                                                 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
 948                                                 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
 949                                                 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
 950                                                 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
 951                                                 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
 952                                                 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
 953                                                 <2 RK_PC1 1 &pcfg_pull_none>,
 954                                                 <2 RK_PC0 1 &pcfg_pull_none>,
 955                                                 <2 RK_PC5 2 &pcfg_pull_none>,
 956                                                 <2 RK_PC4 2 &pcfg_pull_none>,
 957                                                 <2 RK_PB3 1 &pcfg_pull_none>,
 958                                                 <2 RK_PB0 1 &pcfg_pull_none>;
 959                         };
 960
 961                         rmii_pins: rmii-pins {
 962                                 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
 963                                                 <2 RK_PB4 1 &pcfg_pull_none>,
 964                                                 <2 RK_PD1 1 &pcfg_pull_none>,
 965                                                 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
 966                                                 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
 967                                                 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
 968                                                 <2 RK_PC1 1 &pcfg_pull_none>,
 969                                                 <2 RK_PC0 1 &pcfg_pull_none>,
 970                                                 <2 RK_PB0 1 &pcfg_pull_none>,
 971                                                 <2 RK_PB7 1 &pcfg_pull_none>;
 972                         };
 973
 974                         phy_pins: phy-pins {
 975                                 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
 976                                                 <2 RK_PB0 2 &pcfg_pull_none>;
 977                         };
 978                 };
 979
 980                 hdmi {
 981                         hdmi_hpd: hdmi-hpd {
 982                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
 983                         };
 984
 985                         hdmii2c_xfer: hdmii2c-xfer {
 986                                 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
 987                                                 <0 RK_PA7 2 &pcfg_pull_none>;
 988                         };
 989
 990                         hdmi_cec: hdmi-cec {
 991                                 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
 992                         };
 993                 };
 994
 995                 i2c0 {
 996                         i2c0_xfer: i2c0-xfer {
 997                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 998                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 999                         };
1000                 };
1001
1002                 i2c1 {
1003                         i2c1_xfer: i2c1-xfer {
1004                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1005                                                 <0 RK_PA3 1 &pcfg_pull_none>;
1006                         };
1007                 };
1008
1009                 i2c2 {
1010                         i2c2_xfer: i2c2-xfer {
1011                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1012                                                 <2 RK_PC5 1 &pcfg_pull_none>;
1013                         };
1014                 };
1015
1016                 i2c3 {
1017                         i2c3_xfer: i2c3-xfer {
1018                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1019                                                 <0 RK_PA7 1 &pcfg_pull_none>;
1020                         };
1021                 };
1022
1023                 spi0 {
1024                         spi0_clk: spi0-clk {
1025                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1026                         };
1027                         spi0_cs0: spi0-cs0 {
1028                                 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1029                         };
1030                         spi0_tx: spi0-tx {
1031                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1032                         };
1033                         spi0_rx: spi0-rx {
1034                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1035                         };
1036                         spi0_cs1: spi0-cs1 {
1037                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1038                         };
1039                 };
1040
1041                 spi1 {
1042                         spi1_clk: spi1-clk {
1043                                 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1044                         };
1045                         spi1_cs0: spi1-cs0 {
1046                                 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1047                         };
1048                         spi1_rx: spi1-rx {
1049                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1050                         };
1051                         spi1_tx: spi1-tx {
1052                                 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1053                         };
1054                         spi1_cs1: spi1-cs1 {
1055                                 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1056                         };
1057                 };
1058
1059                 i2s1 {
1060                         i2s1_bus: i2s1-bus {
1061                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1062                                                 <0 RK_PB1 1 &pcfg_pull_none>,
1063                                                 <0 RK_PB3 1 &pcfg_pull_none>,
1064                                                 <0 RK_PB4 1 &pcfg_pull_none>,
1065                                                 <0 RK_PB5 1 &pcfg_pull_none>,
1066                                                 <0 RK_PB6 1 &pcfg_pull_none>,
1067                                                 <1 RK_PA2 2 &pcfg_pull_none>,
1068                                                 <1 RK_PA4 2 &pcfg_pull_none>,
1069                                                 <1 RK_PA5 2 &pcfg_pull_none>;
1070                         };
1071                 };
1072
1073                 pwm0 {
1074                         pwm0_pin: pwm0-pin {
1075                                 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 pwm1 {
1080                         pwm1_pin: pwm1-pin {
1081                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1082                         };
1083                 };
1084
1085                 pwm2 {
1086                         pwm2_pin: pwm2-pin {
1087                                 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1088                         };
1089                 };
1090
1091                 pwm3 {
1092                         pwm3_pin: pwm3-pin {
1093                                 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1094                         };
1095                 };
1096
1097                 spdif {
1098                         spdif_tx: spdif-tx {
1099                                 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 tsadc {
1104                         otp_gpio: otp-gpio {
1105                                 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1106                         };
1107
1108                         otp_out: otp-out {
1109                                 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1110                         };
1111                 };
1112
1113                 uart0 {
1114                         uart0_xfer: uart0-xfer {
1115                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1116                                                 <2 RK_PD3 1 &pcfg_pull_none>;
1117                         };
1118
1119                         uart0_cts: uart0-cts {
1120                                 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1121                         };
1122
1123                         uart0_rts: uart0-rts {
1124                                 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1125                         };
1126                 };
1127
1128                 uart1 {
1129                         uart1_xfer: uart1-xfer {
1130                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1131                                                 <1 RK_PB2 1 &pcfg_pull_none>;
1132                         };
1133
1134                         uart1_cts: uart1-cts {
1135                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1136                         };
1137
1138                         uart1_rts: uart1-rts {
1139                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1140                         };
1141                 };
1142
1143                 uart2 {
1144                         uart2_xfer: uart2-xfer {
1145                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1146                                                 <1 RK_PC3 2 &pcfg_pull_none>;
1147                         };
1148
1149                         uart21_xfer: uart21-xfer {
1150                                 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1151                                                 <1 RK_PB1 2 &pcfg_pull_none>;
1152                         };
1153
1154                         uart2_cts: uart2-cts {
1155                                 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1156                         };
1157
1158                         uart2_rts: uart2-rts {
1159                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1160                         };
1161                 };
1162         };
1163 };