arch/arm/boot/dts/stih410-clock.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics R&D Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <dt-bindings/clock/stih410-clks.h>
   9 / {
  10         /*
  11          * Fixed 30MHz oscillator inputs to SoC
  12          */
  13         clk_sysin: clk-sysin {
  14                 #clock-cells = <0>;
  15                 compatible = "fixed-clock";
  16                 clock-frequency = <30000000>;
  17                 clock-output-names = "CLK_SYSIN";
  18         };
  19
  20         clk_tmdsout_hdmi: clk-tmdsout-hdmi {
  21                 #clock-cells = <0>;
  22                 compatible = "fixed-clock";
  23                 clock-frequency = <0>;
  24         };
  25
  26         clocks {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges;
  30
  31                 compatible = "st,stih410-clk", "simple-bus";
  32
  33                 /*
  34                  * A9 PLL.
  35                  */
  36                 clockgen-a9@92b0000 {
  37                         compatible = "st,clkgen-c32";
  38                         reg = <0x92b0000 0xffff>;
  39
  40                         clockgen_a9_pll: clockgen-a9-pll {
  41                                 #clock-cells = <1>;
  42                                 compatible = "st,stih407-clkgen-plla9";
  43
  44                                 clocks = <&clk_sysin>;
  45
  46                                 clock-output-names = "clockgen-a9-pll-odf";
  47                         };
  48                 };
  49
  50                 /*
  51                  * ARM CPU related clocks.
  52                  */
  53                 clk_m_a9: clk-m-a9@92b0000 {
  54                         #clock-cells = <0>;
  55                         compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
  56                         reg = <0x92b0000 0x10000>;
  57
  58                         clocks = <&clockgen_a9_pll 0>,
  59                                  <&clockgen_a9_pll 0>,
  60                                  <&clk_s_c0_flexgen 13>,
  61                                  <&clk_m_a9_ext2f_div2>;
  62                         /*
  63                          * ARM Peripheral clock for timers
  64                          */
  65                         arm_periph_clk: clk-m-a9-periphs {
  66                                 #clock-cells = <0>;
  67                                 compatible = "fixed-factor-clock";
  68                                 clocks = <&clk_m_a9>;
  69                                 clock-div = <2>;
  70                                 clock-mult = <1>;
  71                         };
  72                 };
  73
  74                 clockgen-a@90ff000 {
  75                         compatible = "st,clkgen-c32";
  76                         reg = <0x90ff000 0x1000>;
  77
  78                         clk_s_a0_pll: clk-s-a0-pll {
  79                                 #clock-cells = <1>;
  80                                 compatible = "st,clkgen-pll0";
  81
  82                                 clocks = <&clk_sysin>;
  83
  84                                 clock-output-names = "clk-s-a0-pll-ofd-0";
  85                                 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
  86                         };
  87
  88                         clk_s_a0_flexgen: clk-s-a0-flexgen {
  89                                 compatible = "st,flexgen";
  90
  91                                 #clock-cells = <1>;
  92
  93                                 clocks = <&clk_s_a0_pll 0>,
  94                                          <&clk_sysin>;
  95
  96                                 clock-output-names = "clk-ic-lmi0",
  97                                                      "clk-ic-lmi1";
  98                                 clock-critical = <CLK_IC_LMI0>;
  99                         };
 100                 };
 101
 102                 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
 103                         #clock-cells = <1>;
 104                         compatible = "st,quadfs-pll";
 105                         reg = <0x9103000 0x1000>;
 106
 107                         clocks = <&clk_sysin>;
 108
 109                         clock-output-names = "clk-s-c0-fs0-ch0",
 110                                              "clk-s-c0-fs0-ch1",
 111                                              "clk-s-c0-fs0-ch2",
 112                                              "clk-s-c0-fs0-ch3";
 113                         clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
 114                 };
 115
 116                 clk_s_c0: clockgen-c@9103000 {
 117                         compatible = "st,clkgen-c32";
 118                         reg = <0x9103000 0x1000>;
 119
 120                         clk_s_c0_pll0: clk-s-c0-pll0 {
 121                                 #clock-cells = <1>;
 122                                 compatible = "st,clkgen-pll0";
 123
 124                                 clocks = <&clk_sysin>;
 125
 126                                 clock-output-names = "clk-s-c0-pll0-odf-0";
 127                                 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
 128                         };
 129
 130                         clk_s_c0_pll1: clk-s-c0-pll1 {
 131                                 #clock-cells = <1>;
 132                                 compatible = "st,clkgen-pll1";
 133
 134                                 clocks = <&clk_sysin>;
 135
 136                                 clock-output-names = "clk-s-c0-pll1-odf-0";
 137                         };
 138
 139                         clk_s_c0_flexgen: clk-s-c0-flexgen {
 140                                 #clock-cells = <1>;
 141                                 compatible = "st,flexgen";
 142
 143                                 clocks = <&clk_s_c0_pll0 0>,
 144                                          <&clk_s_c0_pll1 0>,
 145                                          <&clk_s_c0_quadfs 0>,
 146                                          <&clk_s_c0_quadfs 1>,
 147                                          <&clk_s_c0_quadfs 2>,
 148                                          <&clk_s_c0_quadfs 3>,
 149                                          <&clk_sysin>;
 150
 151                                 clock-output-names = "clk-icn-gpu",
 152                                                      "clk-fdma",
 153                                                      "clk-nand",
 154                                                      "clk-hva",
 155                                                      "clk-proc-stfe",
 156                                                      "clk-proc-tp",
 157                                                      "clk-rx-icn-dmu",
 158                                                      "clk-rx-icn-hva",
 159                                                      "clk-icn-cpu",
 160                                                      "clk-tx-icn-dmu",
 161                                                      "clk-mmc-0",
 162                                                      "clk-mmc-1",
 163                                                      "clk-jpegdec",
 164                                                      "clk-ext2fa9",
 165                                                      "clk-ic-bdisp-0",
 166                                                      "clk-ic-bdisp-1",
 167                                                      "clk-pp-dmu",
 168                                                      "clk-vid-dmu",
 169                                                      "clk-dss-lpc",
 170                                                      "clk-st231-aud-0",
 171                                                      "clk-st231-gp-1",
 172                                                      "clk-st231-dmu",
 173                                                      "clk-icn-lmi",
 174                                                      "clk-tx-icn-disp-1",
 175                                                      "clk-icn-sbc",
 176                                                      "clk-stfe-frc2",
 177                                                      "clk-eth-phy",
 178                                                      "clk-eth-ref-phyclk",
 179                                                      "clk-flash-promip",
 180                                                      "clk-main-disp",
 181                                                      "clk-aux-disp",
 182                                                      "clk-compo-dvp",
 183                                                      "clk-tx-icn-hades",
 184                                                      "clk-rx-icn-hades",
 185                                                      "clk-icn-reg-16",
 186                                                      "clk-pp-hades",
 187                                                      "clk-clust-hades",
 188                                                      "clk-hwpe-hades",
 189                                                      "clk-fc-hades";
 190                                 clock-critical = <CLK_PROC_STFE>,
 191                                                  <CLK_ICN_CPU>,
 192                                                  <CLK_TX_ICN_DMU>,
 193                                                  <CLK_EXT2F_A9>,
 194                                                  <CLK_ICN_LMI>,
 195                                                  <CLK_ICN_SBC>;
 196
 197                                 /*
 198                                  * ARM Peripheral clock for timers
 199                                  */
 200                                 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
 201                                         #clock-cells = <0>;
 202                                         compatible = "fixed-factor-clock";
 203
 204                                         clocks = <&clk_s_c0_flexgen 13>;
 205
 206                                         clock-output-names = "clk-m-a9-ext2f-div2";
 207
 208                                         clock-div = <2>;
 209                                         clock-mult = <1>;
 210                                 };
 211                         };
 212                 };
 213
 214                 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
 215                         #clock-cells = <1>;
 216                         compatible = "st,quadfs";
 217                         reg = <0x9104000 0x1000>;
 218
 219                         clocks = <&clk_sysin>;
 220
 221                         clock-output-names = "clk-s-d0-fs0-ch0",
 222                                              "clk-s-d0-fs0-ch1",
 223                                              "clk-s-d0-fs0-ch2",
 224                                              "clk-s-d0-fs0-ch3";
 225                 };
 226
 227                 clockgen-d0@9104000 {
 228                         compatible = "st,clkgen-c32";
 229                         reg = <0x9104000 0x1000>;
 230
 231                         clk_s_d0_flexgen: clk-s-d0-flexgen {
 232                                 #clock-cells = <1>;
 233                                 compatible = "st,flexgen-audio", "st,flexgen";
 234
 235                                 clocks = <&clk_s_d0_quadfs 0>,
 236                                          <&clk_s_d0_quadfs 1>,
 237                                          <&clk_s_d0_quadfs 2>,
 238                                          <&clk_s_d0_quadfs 3>,
 239                                          <&clk_sysin>;
 240
 241                                 clock-output-names = "clk-pcm-0",
 242                                                      "clk-pcm-1",
 243                                                      "clk-pcm-2",
 244                                                      "clk-spdiff",
 245                                                      "clk-pcmr10-master",
 246                                                      "clk-usb2-phy";
 247                         };
 248                 };
 249
 250                 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
 251                         #clock-cells = <1>;
 252                         compatible = "st,quadfs";
 253                         reg = <0x9106000 0x1000>;
 254
 255                         clocks = <&clk_sysin>;
 256
 257                         clock-output-names = "clk-s-d2-fs0-ch0",
 258                                              "clk-s-d2-fs0-ch1",
 259                                              "clk-s-d2-fs0-ch2",
 260                                              "clk-s-d2-fs0-ch3";
 261                 };
 262
 263                 clockgen-d2@9106000 {
 264                         compatible = "st,clkgen-c32";
 265                         reg = <0x9106000 0x1000>;
 266
 267                         clk_s_d2_flexgen: clk-s-d2-flexgen {
 268                                 #clock-cells = <1>;
 269                                 compatible = "st,flexgen-video", "st,flexgen";
 270
 271                                 clocks = <&clk_s_d2_quadfs 0>,
 272                                          <&clk_s_d2_quadfs 1>,
 273                                          <&clk_s_d2_quadfs 2>,
 274                                          <&clk_s_d2_quadfs 3>,
 275                                          <&clk_sysin>,
 276                                          <&clk_sysin>,
 277                                          <&clk_tmdsout_hdmi>;
 278
 279                                 clock-output-names = "clk-pix-main-disp",
 280                                                      "clk-pix-pip",
 281                                                      "clk-pix-gdp1",
 282                                                      "clk-pix-gdp2",
 283                                                      "clk-pix-gdp3",
 284                                                      "clk-pix-gdp4",
 285                                                      "clk-pix-aux-disp",
 286                                                      "clk-denc",
 287                                                      "clk-pix-hddac",
 288                                                      "clk-hddac",
 289                                                      "clk-sddac",
 290                                                      "clk-pix-dvo",
 291                                                      "clk-dvo",
 292                                                      "clk-pix-hdmi",
 293                                                      "clk-tmds-hdmi",
 294                                                      "clk-ref-hdmiphy";
 295                                                      };
 296                 };
 297
 298                 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
 299                         #clock-cells = <1>;
 300                         compatible = "st,quadfs";
 301                         reg = <0x9107000 0x1000>;
 302
 303                         clocks = <&clk_sysin>;
 304
 305                         clock-output-names = "clk-s-d3-fs0-ch0",
 306                                              "clk-s-d3-fs0-ch1",
 307                                              "clk-s-d3-fs0-ch2",
 308                                              "clk-s-d3-fs0-ch3";
 309                 };
 310
 311                 clockgen-d3@9107000 {
 312                         compatible = "st,clkgen-c32";
 313                         reg = <0x9107000 0x1000>;
 314
 315                         clk_s_d3_flexgen: clk-s-d3-flexgen {
 316                                 #clock-cells = <1>;
 317                                 compatible = "st,flexgen";
 318
 319                                 clocks = <&clk_s_d3_quadfs 0>,
 320                                          <&clk_s_d3_quadfs 1>,
 321                                          <&clk_s_d3_quadfs 2>,
 322                                          <&clk_s_d3_quadfs 3>,
 323                                          <&clk_sysin>;
 324
 325                                 clock-output-names = "clk-stfe-frc1",
 326                                                      "clk-tsout-0",
 327                                                      "clk-tsout-1",
 328                                                      "clk-mchi",
 329                                                      "clk-vsens-compo",
 330                                                      "clk-frc1-remote",
 331                                                      "clk-lpc-0",
 332                                                      "clk-lpc-1";
 333                         };
 334                 };
 335         };
 336 };