arch/arm/cpu/arm1136/mx35/generic.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/errno.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <netdev.h>
  34
  35 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  36 #define CLK_CODE_ARM(c)         (((c) >> 16) & 0xFF)
  37 #define CLK_CODE_AHB(c)         (((c) >>  8) & 0xFF)
  38 #define CLK_CODE_PATH(c)        ((c) & 0xFF)
  39
  40 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  41
  42 #ifdef CONFIG_FSL_ESDHC
  43 DECLARE_GLOBAL_DATA_PTR;
  44 #endif
  45
  46 static int g_clk_mux_auto[8] = {
  47         CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  48         CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  49 };
  50
  51 static int g_clk_mux_consumer[16] = {
  52         CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  53         -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  54         CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  55         -1, -1, CLK_CODE(4, 2, 0), -1,
  56 };
  57
  58 static int hsp_div_table[3][16] = {
  59         {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  60         {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  61         {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  62 };
  63
  64 u32 get_cpu_rev(void)
  65 {
  66         int reg;
  67         struct iim_regs *iim =
  68                 (struct iim_regs *)IIM_BASE_ADDR;
  69         reg = readl(&iim->iim_srev);
  70         if (!reg) {
  71                 reg = readw(ROMPATCH_REV);
  72                 reg <<= 4;
  73         } else {
  74                 reg += CHIP_REV_1_0;
  75         }
  76
  77         return 0x35000 + (reg & 0xFF);
  78 }
  79
  80 static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  81 {
  82         int *pclk_mux;
  83         if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  84                 pclk_mux = g_clk_mux_consumer +
  85                         ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  86                         MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  87         } else {
  88                 pclk_mux = g_clk_mux_auto +
  89                         ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  90                         MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  91         }
  92
  93         if ((*pclk_mux) == -1)
  94                 return -1;
  95
  96         if (fi && fd) {
  97                 if (!CLK_CODE_PATH(*pclk_mux)) {
  98                         *fi = *fd = 1;
  99                         return CLK_CODE_ARM(*pclk_mux);
 100                 }
 101                 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
 102                         *fi = 3;
 103                         *fd = 4;
 104                 } else {
 105                         *fi = 2;
 106                         *fd = 3;
 107                 }
 108         }
 109         return CLK_CODE_ARM(*pclk_mux);
 110 }
 111
 112 static int get_ahb_div(u32 pdr0)
 113 {
 114         int *pclk_mux;
 115
 116         pclk_mux = g_clk_mux_consumer +
 117                 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
 118                 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
 119
 120         if ((*pclk_mux) == -1)
 121                 return -1;
 122
 123         return CLK_CODE_AHB(*pclk_mux);
 124 }
 125
 126 static u32 decode_pll(u32 reg, u32 infreq)
 127 {
 128         u32 mfi = (reg >> 10) & 0xf;
 129         u32 mfn = reg & 0x3f;
 130         u32 mfd = (reg >> 16) & 0x3f;
 131         u32 pd = (reg >> 26) & 0xf;
 132
 133         mfi = mfi <= 5 ? 5 : mfi;
 134         mfd += 1;
 135         pd += 1;
 136
 137         return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
 138 }
 139
 140 static u32 get_mcu_main_clk(void)
 141 {
 142         u32 arm_div = 0, fi = 0, fd = 0;
 143         struct ccm_regs *ccm =
 144                 (struct ccm_regs *)IMX_CCM_BASE;
 145         arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
 146         fi *=
 147                 decode_pll(readl(&ccm->mpctl),
 148                         CONFIG_MX35_HCLK_FREQ);
 149         return fi / (arm_div * fd);
 150 }
 151
 152 static u32 get_ipg_clk(void)
 153 {
 154         u32 freq = get_mcu_main_clk();
 155         struct ccm_regs *ccm =
 156                 (struct ccm_regs *)IMX_CCM_BASE;
 157         u32 pdr0 = readl(&ccm->pdr0);
 158
 159         return freq / (get_ahb_div(pdr0) * 2);
 160 }
 161
 162 static u32 get_ipg_per_clk(void)
 163 {
 164         u32 freq = get_mcu_main_clk();
 165         struct ccm_regs *ccm =
 166                 (struct ccm_regs *)IMX_CCM_BASE;
 167         u32 pdr0 = readl(&ccm->pdr0);
 168         u32 pdr4 = readl(&ccm->pdr4);
 169         u32 div;
 170         if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
 171                 div = (CCM_GET_DIVIDER(pdr4,
 172                         MXC_CCM_PDR4_PER0_PRDF_MASK,
 173                         MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
 174                         (CCM_GET_DIVIDER(pdr4,
 175                         MXC_CCM_PDR4_PER0_PODF_MASK,
 176                         MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
 177         } else {
 178                 div = CCM_GET_DIVIDER(pdr0,
 179                         MXC_CCM_PDR0_PER_PODF_MASK,
 180                         MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
 181                 freq /= get_ahb_div(pdr0);
 182         }
 183         return freq / div;
 184 }
 185
 186 u32 imx_get_uartclk(void)
 187 {
 188         u32 freq;
 189         struct ccm_regs *ccm =
 190                 (struct ccm_regs *)IMX_CCM_BASE;
 191         u32 pdr4 = readl(&ccm->pdr4);
 192
 193         if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
 194                 freq = get_mcu_main_clk();
 195         } else {
 196                 freq = decode_pll(readl(&ccm->ppctl),
 197                         CONFIG_MX35_HCLK_FREQ);
 198         }
 199         freq /= ((CCM_GET_DIVIDER(pdr4,
 200                         MXC_CCM_PDR4_UART_PRDF_MASK,
 201                         MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
 202                 (CCM_GET_DIVIDER(pdr4,
 203                         MXC_CCM_PDR4_UART_PODF_MASK,
 204                         MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
 205         return freq;
 206 }
 207
 208 unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
 209 {
 210         u32 nfc_pdf, hsp_podf;
 211         u32 pll, ret_val = 0, usb_prdf, usb_podf;
 212         struct ccm_regs *ccm =
 213                 (struct ccm_regs *)IMX_CCM_BASE;
 214
 215         u32 reg = readl(&ccm->pdr0);
 216         u32 reg4 = readl(&ccm->pdr4);
 217
 218         reg |= 0x1;
 219
 220         switch (clk) {
 221         case CPU_CLK:
 222                 ret_val = get_mcu_main_clk();
 223                 break;
 224         case AHB_CLK:
 225                 ret_val = get_mcu_main_clk();
 226                 break;
 227         case HSP_CLK:
 228                 if (reg & CLKMODE_CONSUMER) {
 229                         hsp_podf = (reg >> 20) & 0x3;
 230                         pll = get_mcu_main_clk();
 231                         hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
 232                         if (hsp_podf > 0) {
 233                                 ret_val = pll / hsp_podf;
 234                         } else {
 235                                 puts("mismatch HSP with ARM clock setting\n");
 236                                 ret_val = 0;
 237                         }
 238                 } else {
 239                         ret_val = get_mcu_main_clk();
 240                 }
 241                 break;
 242         case IPG_CLK:
 243                 ret_val = get_ipg_clk();
 244                 break;
 245         case IPG_PER_CLK:
 246                 ret_val = get_ipg_per_clk();
 247                 break;
 248         case NFC_CLK:
 249                 nfc_pdf = (reg4 >> 28) & 0xF;
 250                 pll = get_mcu_main_clk();
 251                 /* AHB/nfc_pdf */
 252                 ret_val = pll / (nfc_pdf + 1);
 253                 break;
 254         case USB_CLK:
 255                 usb_prdf = (reg4 >> 25) & 0x7;
 256                 usb_podf = (reg4 >> 22) & 0x7;
 257                 if (reg4 & 0x200) {
 258                         pll = get_mcu_main_clk();
 259                 } else {
 260                         pll = decode_pll(readl(&ccm->ppctl),
 261                                 CONFIG_MX35_HCLK_FREQ);
 262                 }
 263
 264                 ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
 265                 break;
 266         default:
 267                 printf("Unknown clock: %d\n", clk);
 268                 break;
 269         }
 270
 271         return ret_val;
 272 }
 273 unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
 274 {
 275         u32 ret_val = 0, pdf, pre_pdf, clk_sel;
 276         struct ccm_regs *ccm =
 277                 (struct ccm_regs *)IMX_CCM_BASE;
 278         u32 mpdr2 = readl(&ccm->pdr2);
 279         u32 mpdr3 = readl(&ccm->pdr3);
 280         u32 mpdr4 = readl(&ccm->pdr4);
 281
 282         switch (clk) {
 283         case UART1_BAUD:
 284         case UART2_BAUD:
 285         case UART3_BAUD:
 286                 clk_sel = mpdr3 & (1 << 14);
 287                 pre_pdf = (mpdr4 >> 13) & 0x7;
 288                 pdf = (mpdr4 >> 10) & 0x7;
 289                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 290                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 291                                 ((pre_pdf + 1) * (pdf + 1));
 292                 break;
 293         case SSI1_BAUD:
 294                 pre_pdf = (mpdr2 >> 24) & 0x7;
 295                 pdf = mpdr2 & 0x3F;
 296                 clk_sel = mpdr2 & (1 << 6);
 297                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 298                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 299                                 ((pre_pdf + 1) * (pdf + 1));
 300                 break;
 301         case SSI2_BAUD:
 302                 pre_pdf = (mpdr2 >> 27) & 0x7;
 303                 pdf = (mpdr2 >> 8) & 0x3F;
 304                 clk_sel = mpdr2 & (1 << 6);
 305                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 306                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 307                                 ((pre_pdf + 1) * (pdf + 1));
 308                 break;
 309         case CSI_BAUD:
 310                 clk_sel = mpdr2 & (1 << 7);
 311                 pre_pdf = (mpdr2 >> 16) & 0x7;
 312                 pdf = (mpdr2 >> 19) & 0x7;
 313                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 314                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 315                                 ((pre_pdf + 1) * (pdf + 1));
 316                 break;
 317         case MSHC_CLK:
 318                 pre_pdf = readl(&ccm->pdr1);
 319                 clk_sel = (pre_pdf & 0x80);
 320                 pdf = (pre_pdf >> 22) & 0x3F;
 321                 pre_pdf = (pre_pdf >> 28) & 0x7;
 322                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 323                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 324                                 ((pre_pdf + 1) * (pdf + 1));
 325                 break;
 326         case ESDHC1_CLK:
 327                 clk_sel = mpdr3 & 0x40;
 328                 pre_pdf = mpdr3 & 0x7;
 329                 pdf = (mpdr3>>3) & 0x7;
 330                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 331                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 332                                 ((pre_pdf + 1) * (pdf + 1));
 333                 break;
 334         case ESDHC2_CLK:
 335                 clk_sel = mpdr3 & 0x40;
 336                 pre_pdf = (mpdr3 >> 8) & 0x7;
 337                 pdf = (mpdr3 >> 11) & 0x7;
 338                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 339                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 340                                 ((pre_pdf + 1) * (pdf + 1));
 341                 break;
 342         case ESDHC3_CLK:
 343                 clk_sel = mpdr3 & 0x40;
 344                 pre_pdf = (mpdr3 >> 16) & 0x7;
 345                 pdf = (mpdr3 >> 19) & 0x7;
 346                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 347                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 348                                 ((pre_pdf + 1) * (pdf + 1));
 349                 break;
 350         case SPDIF_CLK:
 351                 clk_sel = mpdr3 & 0x400000;
 352                 pre_pdf = (mpdr3 >> 29) & 0x7;
 353                 pdf = (mpdr3 >> 23) & 0x3F;
 354                 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
 355                         decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
 356                                 ((pre_pdf + 1) * (pdf + 1));
 357                 break;
 358         default:
 359                 printf("%s(): This clock: %d not supported yet\n",
 360                                 __func__, clk);
 361                 break;
 362         }
 363
 364         return ret_val;
 365 }
 366
 367 unsigned int mxc_get_clock(enum mxc_clock clk)
 368 {
 369         switch (clk) {
 370         case MXC_ARM_CLK:
 371                 return get_mcu_main_clk();
 372         case MXC_AHB_CLK:
 373                 break;
 374         case MXC_IPG_CLK:
 375                 return get_ipg_clk();
 376         case MXC_IPG_PERCLK:
 377                 return get_ipg_per_clk();
 378         case MXC_UART_CLK:
 379                 return imx_get_uartclk();
 380         case MXC_ESDHC_CLK:
 381                 return mxc_get_peri_clock(ESDHC1_CLK);
 382         case MXC_USB_CLK:
 383                 return mxc_get_main_clock(USB_CLK);
 384         case MXC_FEC_CLK:
 385                 return get_ipg_clk();
 386         case MXC_CSPI_CLK:
 387                 return get_ipg_clk();
 388         }
 389         return -1;
 390 }
 391
 392 #ifdef CONFIG_FEC_MXC
 393 /*
 394  * The MX35 has no fuse for MAC, return a NULL MAC
 395  */
 396 void imx_get_mac_from_fuse(unsigned char *mac)
 397 {
 398         memset(mac, 0, 6);
 399 }
 400
 401 u32 imx_get_fecclk(void)
 402 {
 403         return mxc_get_clock(MXC_IPG_CLK);
 404 }
 405 #endif
 406
 407 int do_mx35_showclocks(cmd_tbl_t *cmdtp,
 408         int flag, int argc, char * const argv[])
 409 {
 410         u32 cpufreq = get_mcu_main_clk();
 411         printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
 412         printf("ipg clock     : %dHz\n", get_ipg_clk());
 413         printf("ipg per clock : %dHz\n", get_ipg_per_clk());
 414         printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
 415
 416         return 0;
 417 }
 418
 419 U_BOOT_CMD(
 420         clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
 421         "display clocks",
 422         ""
 423 );
 424
 425 #if defined(CONFIG_DISPLAY_CPUINFO)
 426 int print_cpuinfo(void)
 427 {
 428         printf("CPU:   Freescale i.MX35 at %d MHz\n",
 429                 get_mcu_main_clk() / 1000000);
 430         /* mxc_dump_clocks(); */
 431         return 0;
 432 }
 433 #endif
 434
 435 /*
 436  * Initializes on-chip ethernet controllers.
 437  * to override, implement board_eth_init()
 438  */
 439
 440 int cpu_eth_init(bd_t *bis)
 441 {
 442         int rc = -ENODEV;
 443
 444 #if defined(CONFIG_FEC_MXC)
 445         rc = fecmxc_initialize(bis);
 446 #endif
 447
 448         return rc;
 449 }
 450
 451 int get_clocks(void)
 452 {
 453 #ifdef CONFIG_FSL_ESDHC
 454         gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 455 #endif
 456         return 0;
 457 }
 458
 459 void reset_cpu(ulong addr)
 460 {
 461         struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
 462         writew(4, &wdog->wcr);
 463 }