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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/arm/cpu/arm1136/mx35/mx35_sdram.c
2 * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <linux/types.h>
11 #include <asm/arch/sys_proto.h>
13 #define ESDCTL_DDR2_EMR2 0x04000000
14 #define ESDCTL_DDR2_EMR3 0x06000000
15 #define ESDCTL_PRECHARGE 0x00000400
16 #define ESDCTL_DDR2_EN_DLL 0x02000400
17 #define ESDCTL_DDR2_RESET_DLL 0x00000333
18 #define ESDCTL_DDR2_MR 0x00000233
19 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
29 #define set_mode(x, en, m) (x | (en << 31) | (m << 28))
31 static inline void dram_wait(unsigned int count
)
33 volatile unsigned int wait
= count
;
40 void mx3_setup_sdram_bank(u32 start_address
, u32 ddr2_config
,
41 u32 row
, u32 col
, u32 dsize
, u32 refresh
)
43 struct esdc_regs
*esdc
= (struct esdc_regs
*)ESDCTL_BASE_ADDR
;
44 u32
*cfg_reg
, *ctl_reg
;
48 switch (start_address
) {
50 cfg_reg
= &esdc
->esdcfg0
;
51 ctl_reg
= &esdc
->esdctl0
;
54 cfg_reg
= &esdc
->esdcfg1
;
55 ctl_reg
= &esdc
->esdctl1
;
61 /* The MX35 supports 11 up to 14 rows */
62 if (row
< 11 || row
> 14 || col
< 8 || col
> 10)
64 ctlval
= (row
- 11) << 24 | (col
- 8) << 20 | (dsize
<< 16);
66 /* Initialize MISC register for DDR2 */
67 val
= ESDC_MISC_RST
| ESDC_MISC_MDDR_EN
| ESDC_MISC_MDDR_DL_RST
|
68 ESDC_MISC_DDR_EN
| ESDC_MISC_DDR2_EN
;
69 writel(val
, &esdc
->esdmisc
);
70 val
&= ~(ESDC_MISC_RST
| ESDC_MISC_MDDR_DL_RST
);
71 writel(val
, &esdc
->esdmisc
);
74 * according to DDR2 specs, wait a while before
75 * the PRECHARGE_ALL command
79 /* Load DDR2 config and timing */
80 writel(ddr2_config
, cfg_reg
);
83 writel(set_mode(ctlval
, 1, SMODE_PRECHARGE
),
85 writel(0xda, start_address
+ ESDCTL_PRECHARGE
);
88 writel(set_mode(ctlval
, 1, SMODE_LOAD_REG
),
90 writeb(0xda, start_address
+ ESDCTL_DDR2_EMR2
); /* EMRS2 */
91 writeb(0xda, start_address
+ ESDCTL_DDR2_EMR3
); /* EMRS3 */
92 writeb(0xda, start_address
+ ESDCTL_DDR2_EN_DLL
); /* Enable DLL */
93 writeb(0xda, start_address
+ ESDCTL_DDR2_RESET_DLL
); /* Reset DLL */
96 writel(set_mode(ctlval
, 1, SMODE_PRECHARGE
),
98 writel(0xda, start_address
+ ESDCTL_PRECHARGE
);
100 /* Set mode auto refresh : at least two refresh are required */
101 writel(set_mode(ctlval
, 1, SMODE_AUTO_REFRESH
),
103 writel(0xda, start_address
);
104 writel(0xda, start_address
);
106 writel(set_mode(ctlval
, 1, SMODE_LOAD_REG
),
108 writeb(0xda, start_address
+ ESDCTL_DDR2_MR
);
109 writeb(0xda, start_address
+ ESDCTL_DDR2_OCD_DEFAULT
);
112 writeb(0xda, start_address
+ ESDCTL_DDR2_EN_DLL
); /* Enable DLL */
114 /* Set normal mode */
115 writel(set_mode(ctlval
, 1, SMODE_NORMAL
) | refresh
,
120 /* Do not set delay lines, only for MDDR */