2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm-offsets.h>
36 #ifdef CONFIG_SPL_BUILD
53 .word 0x12345678 /* now 16*4=64 */
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction: .word undefined_instruction
64 _software_interrupt: .word software_interrupt
65 _prefetch_abort: .word prefetch_abort
66 _data_abort: .word data_abort
67 _not_used: .word not_used
70 _pad: .word 0x12345678 /* now 16*4=64 */
71 #endif /* CONFIG_SPL_BUILD */
75 .balignl 16,0xdeadbeef
77 *************************************************************************
79 * Startup Code (reset vector)
81 * do important init only if we don't start from memory!
82 * setup Memory and board specific bits prior to relocation.
83 * relocate armboot to ram
86 *************************************************************************
91 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
92 .word CONFIG_SPL_TEXT_BASE
94 .word CONFIG_SYS_TEXT_BASE
98 * These are defined in the board-specific linker script.
99 * Subtracting _start from them lets the linker put their
100 * relative position in the executable instead of leaving
103 .globl _bss_start_ofs
105 .word __bss_start - _start
107 .global _image_copy_end_ofs
109 .word __image_copy_end - _start
113 .word __bss_end - _start
119 #ifdef CONFIG_USE_IRQ
120 /* IRQ stack memory (calculated at run-time) */
121 .globl IRQ_STACK_START
125 /* IRQ stack memory (calculated at run-time) */
126 .globl FIQ_STACK_START
131 /* IRQ stack memory (calculated at run-time) + 8 bytes */
132 .globl IRQ_STACK_START_IN
137 * the actual reset code
142 * set the cpu to SVC32 mode
149 #ifdef CONFIG_OMAP2420H4
150 /* Copy vectors to mask ROM indirect addr */
151 adr r0, _start /* r0 <- current position of code */
152 add r0, r0, #4 /* skip reset vector */
153 mov r2, #64 /* r2 <- size to copy */
154 add r2, r0, r2 /* r2 <- source end address */
155 mov r1, #SRAM_OFFSET0 /* build vect addr */
156 mov r3, #SRAM_OFFSET1
158 mov r3, #SRAM_OFFSET2
161 ldmia r0!, {r3-r10} /* copy from source address [r0] */
162 stmia r1!, {r3-r10} /* copy to target address [r1] */
163 cmp r0, r2 /* until source end address [r2] */
164 bne next /* loop until equal */
165 bl cpy_clk_code /* put dpll adjust code behind vectors */
167 /* the mask ROM code should have PLL and others stable */
168 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
174 /*------------------------------------------------------------------------------*/
177 * void relocate_code (addr_sp, gd, addr_moni)
179 * This "function" does not return, instead it continues in RAM
180 * after relocating the monitor code.
185 mov r4, r0 /* save addr_sp */
186 mov r5, r1 /* save addr of gd */
187 mov r6, r2 /* save addr of destination */
191 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
192 beq relocate_done /* skip relocation */
193 mov r1, r6 /* r1 <- scratch for copy_loop */
194 ldr r3, _image_copy_end_ofs
195 add r2, r0, r3 /* r2 <- source end address */
198 ldmia r0!, {r9-r10} /* copy from source address [r0] */
199 stmia r1!, {r9-r10} /* copy to target address [r1] */
200 cmp r0, r2 /* until source end address [r2] */
203 #ifndef CONFIG_SPL_BUILD
205 * fix .rel.dyn relocations
207 ldr r0, _TEXT_BASE /* r0 <- Text base */
208 sub r9, r6, r0 /* r9 <- relocation offset */
209 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
210 add r10, r10, r0 /* r10 <- sym table in FLASH */
211 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
212 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
213 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
214 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
216 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
217 add r0, r0, r9 /* r0 <- location to fix up in RAM */
220 cmp r7, #23 /* relative fixup? */
222 cmp r7, #2 /* absolute fixup? */
224 /* ignore unknown type of fixup */
227 /* absolute fix: set location to (offset) symbol value */
228 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
229 add r1, r10, r1 /* r1 <- address of symbol in table */
230 ldr r1, [r1, #4] /* r1 <- symbol value */
231 add r1, r1, r9 /* r1 <- relocated sym addr */
234 /* relative fix: increase location by offset */
239 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
250 #ifndef CONFIG_SPL_BUILD
253 .word __rel_dyn_start - _start
255 .word __rel_dyn_end - _start
257 .word __dynsym_start - _start
261 .globl c_runtime_cpu_setup
267 *************************************************************************
269 * CPU_init_critical registers
271 * setup important registers
272 * setup memory timing
274 *************************************************************************
276 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
279 * flush v4 I/D caches
282 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
283 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
286 * disable MMU stuff and caches
288 mrc p15, 0, r0, c1, c0, 0
289 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
290 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
291 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
292 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
293 mcr p15, 0, r0, c1, c0, 0
296 * Jump to board specific initialization... The Mask ROM will have already initialized
297 * basic memory. Go here to bump up clock rate and handle wake up conditions.
299 mov ip, lr /* persevere link reg across call */
300 bl lowlevel_init /* go setup pll,mux,memory */
301 mov lr, ip /* restore link */
302 mov pc, lr /* back to my caller */
303 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
305 #ifndef CONFIG_SPL_BUILD
307 *************************************************************************
311 *************************************************************************
316 #define S_FRAME_SIZE 72
338 #define MODE_SVC 0x13
342 * use bad_save_user_regs for abort/prefetch/undef/swi ...
343 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
346 .macro bad_save_user_regs
347 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
348 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
350 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
351 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
352 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
356 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
357 mov r0, sp @ save current stack into r0 (param register)
360 .macro irq_save_user_regs
361 sub sp, sp, #S_FRAME_SIZE
362 stmia sp, {r0 - r12} @ Calling r0-r12
363 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
364 stmdb r8, {sp, lr}^ @ Calling SP, LR
365 str lr, [r8, #0] @ Save calling PC
367 str r6, [r8, #4] @ Save CPSR
368 str r0, [r8, #8] @ Save OLD_R0
372 .macro irq_restore_user_regs
373 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
375 ldr lr, [sp, #S_PC] @ Get PC
376 add sp, sp, #S_FRAME_SIZE
377 subs pc, lr, #4 @ return & move spsr_svc into cpsr
381 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
383 str lr, [r13] @ save caller lr in position 0 of saved stack
384 mrs lr, spsr @ get the spsr
385 str lr, [r13, #4] @ save spsr in position 1 of saved stack
387 mov r13, #MODE_SVC @ prepare SVC-Mode
389 msr spsr, r13 @ switch modes, make sure moves will execute
390 mov lr, pc @ capture return pc
391 movs pc, lr @ jump to next instruction & switch modes.
394 .macro get_bad_stack_swi
395 sub r13, r13, #4 @ space on current stack for scratch reg.
396 str r0, [r13] @ save R0's value.
397 ldr r0, IRQ_STACK_START_IN @ get data regions start
398 str lr, [r0] @ save caller lr in position 0 of saved stack
399 mrs r0, spsr @ get the spsr
400 str lr, [r0, #4] @ save spsr in position 1 of saved stack
401 ldr r0, [r13] @ restore r0
402 add r13, r13, #4 @ pop stack entry
405 .macro get_irq_stack @ setup IRQ stack
406 ldr sp, IRQ_STACK_START
409 .macro get_fiq_stack @ setup FIQ stack
410 ldr sp, FIQ_STACK_START
412 #endif /* CONFIG_SPL_BUILD */
417 #ifdef CONFIG_SPL_BUILD
420 ldr sp, _TEXT_BASE /* use 32 words about stack */
421 bl hang /* hang and never return */
422 #else /* !CONFIG_SPL_BUILD */
424 undefined_instruction:
427 bl do_undefined_instruction
433 bl do_software_interrupt
453 #ifdef CONFIG_USE_IRQ
460 irq_restore_user_regs
465 /* someone ought to write a more effiction fiq_save_user_regs */
468 irq_restore_user_regs
486 .global arm1136_cache_flush
488 #if !defined(CONFIG_SYS_ICACHE_OFF)
489 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
491 #if !defined(CONFIG_SYS_DCACHE_OFF)
492 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
494 mov pc, lr @ back to caller
495 #endif /* CONFIG_SPL_BUILD */