arch/arm/cpu/arm720t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM720 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <asm-offsets.h>
  27 #include <config.h>
  28 #include <version.h>
  29 #include <asm/hardware.h>
  30
  31 /*
  32  *************************************************************************
  33  *
  34  * Jump vector table as in table 3.1 in [1]
  35  *
  36  *************************************************************************
  37  */
  38
  39
  40 .globl _start
  41 _start: b       reset
  42         ldr     pc, _undefined_instruction
  43         ldr     pc, _software_interrupt
  44         ldr     pc, _prefetch_abort
  45         ldr     pc, _data_abort
  46         ldr     pc, _not_used
  47         ldr     pc, _irq
  48         ldr     pc, _fiq
  49
  50 #ifdef CONFIG_SPL_BUILD
  51 _undefined_instruction: .word _undefined_instruction
  52 _software_interrupt:    .word _software_interrupt
  53 _prefetch_abort:        .word _prefetch_abort
  54 _data_abort:            .word _data_abort
  55 _not_used:              .word _not_used
  56 _irq:                   .word _irq
  57 _fiq:                   .word _fiq
  58 _pad:                   .word 0x12345678 /* now 16*4=64 */
  59 #else
  60 _undefined_instruction: .word undefined_instruction
  61 _software_interrupt:    .word software_interrupt
  62 _prefetch_abort:        .word prefetch_abort
  63 _data_abort:            .word data_abort
  64 _not_used:              .word not_used
  65 _irq:                   .word irq
  66 _fiq:                   .word fiq
  67 _pad:                   .word 0x12345678 /* now 16*4=64 */
  68 #endif  /* CONFIG_SPL_BUILD */
  69
  70         .balignl 16,0xdeadbeef
  71
  72
  73 /*
  74  *************************************************************************
  75  *
  76  * Startup Code (reset vector)
  77  *
  78  * do important init only if we don't start from RAM!
  79  * relocate armboot to ram
  80  * setup stack
  81  * jump to second stage
  82  *
  83  *************************************************************************
  84  */
  85
  86 .globl _TEXT_BASE
  87 _TEXT_BASE:
  88 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  89         .word   CONFIG_SPL_TEXT_BASE
  90 #else
  91         .word   CONFIG_SYS_TEXT_BASE
  92 #endif
  93
  94 /*
  95  * These are defined in the board-specific linker script.
  96  * Subtracting _start from them lets the linker put their
  97  * relative position in the executable instead of leaving
  98  * them null.
  99  */
 100 .globl _bss_start_ofs
 101 _bss_start_ofs:
 102         .word __bss_start - _start
 103
 104 .globl _bss_end_ofs
 105 _bss_end_ofs:
 106         .word __bss_end - _start
 107
 108 .globl _end_ofs
 109 _end_ofs:
 110         .word _end - _start
 111
 112 #ifdef CONFIG_USE_IRQ
 113 /* IRQ stack memory (calculated at run-time) */
 114 .globl IRQ_STACK_START
 115 IRQ_STACK_START:
 116         .word   0x0badc0de
 117
 118 /* IRQ stack memory (calculated at run-time) */
 119 .globl FIQ_STACK_START
 120 FIQ_STACK_START:
 121         .word 0x0badc0de
 122 #endif
 123
 124 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 125 .globl IRQ_STACK_START_IN
 126 IRQ_STACK_START_IN:
 127         .word   0x0badc0de
 128
 129 /*
 130  * the actual reset code
 131  */
 132
 133 reset:
 134         /*
 135          * set the cpu to SVC32 mode
 136          */
 137         mrs     r0,cpsr
 138         bic     r0,r0,#0x1f
 139         orr     r0,r0,#0xd3
 140         msr     cpsr,r0
 141
 142         /*
 143          * we do sys-critical inits only at reboot,
 144          * not when booting from ram!
 145          */
 146 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 147         bl      cpu_init_crit
 148 #endif
 149
 150         bl      _main
 151
 152 /*------------------------------------------------------------------------------*/
 153
 154 /*
 155  * void relocate_code (addr_sp, gd, addr_moni)
 156  *
 157  * This "function" does not return, instead it continues in RAM
 158  * after relocating the monitor code.
 159  *
 160  */
 161         .globl  relocate_code
 162 relocate_code:
 163         mov     r4, r0  /* save addr_sp */
 164         mov     r5, r1  /* save addr of gd */
 165         mov     r6, r2  /* save addr of destination */
 166
 167         adr     r0, _start
 168         cmp     r0, r6
 169         moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
 170         beq     relocate_done           /* skip relocation */
 171         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 172         ldr     r3, _bss_start_ofs
 173         add     r2, r0, r3              /* r2 <- source end address         */
 174
 175 copy_loop:
 176         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 177         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 178         cmp     r0, r2                  /* until source end address [r2]    */
 179         blo     copy_loop
 180
 181 #ifndef CONFIG_SPL_BUILD
 182         /*
 183          * fix .rel.dyn relocations
 184          */
 185         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 186         sub     r9, r6, r0              /* r9 <- relocation offset */
 187         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 188         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 189         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 190         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 191         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 192         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 193 fixloop:
 194         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 195         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 196         ldr     r1, [r2, #4]
 197         and     r7, r1, #0xff
 198         cmp     r7, #23                 /* relative fixup? */
 199         beq     fixrel
 200         cmp     r7, #2                  /* absolute fixup? */
 201         beq     fixabs
 202         /* ignore unknown type of fixup */
 203         b       fixnext
 204 fixabs:
 205         /* absolute fix: set location to (offset) symbol value */
 206         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 207         add     r1, r10, r1             /* r1 <- address of symbol in table */
 208         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 209         add     r1, r1, r9              /* r1 <- relocated sym addr */
 210         b       fixnext
 211 fixrel:
 212         /* relative fix: increase location by offset */
 213         ldr     r1, [r0]
 214         add     r1, r1, r9
 215 fixnext:
 216         str     r1, [r0]
 217         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 218         cmp     r2, r3
 219         blo     fixloop
 220 #endif
 221
 222 relocate_done:
 223
 224         mov     pc, lr
 225
 226 _rel_dyn_start_ofs:
 227         .word __rel_dyn_start - _start
 228 _rel_dyn_end_ofs:
 229         .word __rel_dyn_end - _start
 230 _dynsym_start_ofs:
 231         .word __dynsym_start - _start
 232
 233         .globl  c_runtime_cpu_setup
 234 c_runtime_cpu_setup:
 235
 236         mov     pc, lr
 237
 238 /*
 239  *************************************************************************
 240  *
 241  * CPU_init_critical registers
 242  *
 243  * setup important registers
 244  * setup memory timing
 245  *
 246  *************************************************************************
 247  */
 248
 249 cpu_init_crit:
 250
 251 #if !defined(CONFIG_TEGRA)
 252         mov     ip, lr
 253         /*
 254          * before relocating, we have to setup RAM timing
 255          * because memory timing is board-dependent, you will
 256          * find a lowlevel_init.S in your board directory.
 257          */
 258         bl      lowlevel_init
 259         mov     lr, ip
 260 #endif
 261
 262         mov     pc, lr
 263
 264
 265 #ifndef CONFIG_SPL_BUILD
 266 /*
 267  *************************************************************************
 268  *
 269  * Interrupt handling
 270  *
 271  *************************************************************************
 272  */
 273
 274 @
 275 @ IRQ stack frame.
 276 @
 277 #define S_FRAME_SIZE    72
 278
 279 #define S_OLD_R0        68
 280 #define S_PSR           64
 281 #define S_PC            60
 282 #define S_LR            56
 283 #define S_SP            52
 284
 285 #define S_IP            48
 286 #define S_FP            44
 287 #define S_R10           40
 288 #define S_R9            36
 289 #define S_R8            32
 290 #define S_R7            28
 291 #define S_R6            24
 292 #define S_R5            20
 293 #define S_R4            16
 294 #define S_R3            12
 295 #define S_R2            8
 296 #define S_R1            4
 297 #define S_R0            0
 298
 299 #define MODE_SVC 0x13
 300 #define I_BIT    0x80
 301
 302 /*
 303  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 304  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 305  */
 306
 307         .macro  bad_save_user_regs
 308         sub     sp, sp, #S_FRAME_SIZE
 309         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 310         add     r8, sp, #S_PC
 311
 312         ldr     r2, IRQ_STACK_START_IN
 313         ldmia   r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 314         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 315
 316         add     r5, sp, #S_SP
 317         mov     r1, lr
 318         stmia   r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 319         mov     r0, sp
 320         .endm
 321
 322         .macro  irq_save_user_regs
 323         sub     sp, sp, #S_FRAME_SIZE
 324         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 325         add     r8, sp, #S_PC
 326         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 327         str     lr, [r8, #0]                    @ Save calling PC
 328         mrs     r6, spsr
 329         str     r6, [r8, #4]                    @ Save CPSR
 330         str     r0, [r8, #8]                    @ Save OLD_R0
 331         mov     r0, sp
 332         .endm
 333
 334         .macro  irq_restore_user_regs
 335         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 336         mov     r0, r0
 337         ldr     lr, [sp, #S_PC]                 @ Get PC
 338         add     sp, sp, #S_FRAME_SIZE
 339         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 340         .endm
 341
 342         .macro get_bad_stack
 343         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 344
 345         str     lr, [r13]                       @ save caller lr / spsr
 346         mrs     lr, spsr
 347         str     lr, [r13, #4]
 348
 349         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 350         msr     spsr_c, r13
 351         mov     lr, pc
 352         movs    pc, lr
 353         .endm
 354
 355         .macro get_irq_stack                    @ setup IRQ stack
 356         ldr     sp, IRQ_STACK_START
 357         .endm
 358
 359         .macro get_fiq_stack                    @ setup FIQ stack
 360         ldr     sp, FIQ_STACK_START
 361         .endm
 362
 363 /*
 364  * exception handlers
 365  */
 366         .align  5
 367 undefined_instruction:
 368         get_bad_stack
 369         bad_save_user_regs
 370         bl      do_undefined_instruction
 371
 372         .align  5
 373 software_interrupt:
 374         get_bad_stack
 375         bad_save_user_regs
 376         bl      do_software_interrupt
 377
 378         .align  5
 379 prefetch_abort:
 380         get_bad_stack
 381         bad_save_user_regs
 382         bl      do_prefetch_abort
 383
 384         .align  5
 385 data_abort:
 386         get_bad_stack
 387         bad_save_user_regs
 388         bl      do_data_abort
 389
 390         .align  5
 391 not_used:
 392         get_bad_stack
 393         bad_save_user_regs
 394         bl      do_not_used
 395
 396 #ifdef CONFIG_USE_IRQ
 397
 398         .align  5
 399 irq:
 400         get_irq_stack
 401         irq_save_user_regs
 402         bl      do_irq
 403         irq_restore_user_regs
 404
 405         .align  5
 406 fiq:
 407         get_fiq_stack
 408         /* someone ought to write a more effiction fiq_save_user_regs */
 409         irq_save_user_regs
 410         bl      do_fiq
 411         irq_restore_user_regs
 412
 413 #else
 414
 415         .align  5
 416 irq:
 417         get_bad_stack
 418         bad_save_user_regs
 419         bl      do_irq
 420
 421         .align  5
 422 fiq:
 423         get_bad_stack
 424         bad_save_user_regs
 425         bl      do_fiq
 426
 427 #endif
 428 #endif /* CONFIG_SPL_BUILD */